JPS59132003A - Signal generator - Google Patents

Abstract

PURPOSE:To simplify a circuit and to perform the operation surely by storing preliminarily data corresponding to program signals of plural channels in a memory. CONSTITUTION:Plural controlling program signals of optical fiber tubes or the like are generated by a signal generating circuit 11. A counter 13 of the circuit 11 counts the clock signal from an oscillator 12 and outputs a parallel n-bit count value signal 131 each time when it counts the clock signal once. Data for generating said program signals are stored preliminarily as one group in respective addresses of an ROM14, and this ROM14 is addressed successively by the output signal 131, and a parallel m-bit output 141 is transmitted to a latch 15 for every address. This latch 15 holds the output 141 during the time corresponding to one clock and transmits it as an output 16 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal ordering device for generating a plurality of program signals (programmed control signals, etc.) in parallel.

(Prior Art) Conventionally, in order to generate multiple program signals simultaneously, that is, in parallel, a signal generation device was constructed by combining a counter, a digital comparator, various gates, etc. for each signal output channel. When the number of channels is extremely large, it becomes complicated and large, which not only causes a disadvantage in terms of cost, but also makes it difficult to change the program.

(Object of the Invention) The present invention has been made in view of the above points, and its purpose is to solve the above-mentioned problems. This data is stored and read out over time.

(Example) Hereinafter, an example in which the present invention is applied to an electrophotographic recording device will be described. FIG. 1 schematically shows an electrophotographic recording apparatus using an OFT as an exposure device. A charging electrode 2 for charging a
The photosensitive drum 1 charged by the charging electrode 2 is exposed to light to form an electrostatic latent image.The optical fiber tube (hereinafter referred to as OFT) 3 attracts toner to the part of the electrostatic latent image. a developing section 4 for forming a toner image by
, a transfer pole 5 for transferring the developed image on the photosensitive drum 1 onto copy paper (its path is indicated by a broken line arrow), a separation pole 6 for separating the copy paper from the photosensitive drum 1, and a transfer pole. A cleaning section 7 is provided for cleaning the surface of the photosensitive drum 1 that has been completely cleaned.

The 0FT3 described above is a CR that scans a fluorescent surface by sweeping a beam of brightness corresponding to a human-powered video signal in the horizontal direction.
The CRT 3 is composed of a cathode ray tube (T) and a plurality of optical fibers arranged in front of the fluorescent surface of the CRT 3 in the main scanning direction (perpendicular to the plane of the drawing). and,
The tips of the plurality of optical fibers are set so as to be perpendicular to the moving direction of the photosensitive surface of the photosensitive drum 1 (the rotational direction of the photosensitive drum 1 indicated by the arrow in the figure).

Reference numeral 8 denotes a reflection type photosensor for detecting the reflection density of the punch pattern image formed by the toner on the photosensitive drum 1 by 0FT3.
The toner concentration of the toner image formed on the photoreceptor is automatically controlled by controlling the opening and closing of the toner supply valve 4a to the developing section 4 based on the detection output.

9 is a drive/amplification circuit for driving the 0FT3 and amplifying the video signal, and 10 is a control circuit.

Now, the signal generation circuit that is built into the control circuit 10 and capable of parallel output does not have a counter or a digital comparator for each channel as described above, but a counter and an RO.
It is constructed by M and Lunch, and is capable of outputting multi-channel serial signals in parallel despite its relatively simple construction. An example in which this signal generating circuit is applied to the electrophotographic recording apparatus described above will be described below.

Well, control time +! A program signal for controlling 0FT3 from 810 and controlling other devices is generated by a signal generating circuit 11 (encircled by a broken line) shown in FIG. - In FIG. 2, I2 is an oscillator that generates a clock signal; 13 is a counter that counts the Q clock ref and generates a count value signal 131 of T1 bits for each count; the counter 1
ROM sequentially addressed by the output signal 131 of 3.
Then, an m-bit parallel output 141 is generated for each address. 15 is the parallel m-bit output signal 1 of the ROM 14.
41 for one clock time, and RO
M14 includes a punch pattern signal for toner density control, a Tessellation pattern signal, a horizontal synchronizing signal for 0FT3 scanning, a water drop signal indicating a period during which effective recording can be performed in the horizontal scanning period, and a dynamic focus signal. , a blank signal, etc. are stored as one group at each address. That is, ROM
Each bit of the m-bit data corresponding to each of the 14 addresses means data at a certain timing (corresponding to a count value) of each of these signals. And this circuit 11
In this case, one pin of the m-bit output 16 of the latch 15 is the clear signal of the counter 13 (previously stored in the ROM 13 as clear timing data) a.
Alternatively, the various signals mentioned above are taken out in parallel through a logic circuit.

Note that the latch 15 receives the address (count value signal 131) specified by the counter 13 by applying a large clock force.
When switching, the output 141 in the ROM 13 changes or becomes transiently unstable, and if the ROM output is directly applied to the controlled circuit or other various signal generation circuits, there is a risk of malfunction. This is provided to prevent this and maintain reliable operation.

FIG. 3 is a diagram for explaining the effects of each signal generated by the signal generating circuit 11, and 111 indicates a signal generating circuit including a logic circuit portion not shown in FIG. The video signal is input as a dot pattern signal from a post-computer character generator (not shown), and is input to the drive/amplification circuit 9 of 0FT3 via an OR gate 17 and an AND gate I8.
is applied between the cathode and the grid. Signal generation circuit 1
The batch pattern signal C from 1 is input to the AND gate 19 which opens the gate by inputting the PA/NOCH ON signal d or from an external control system (not shown), and the output of the AND gate 19 can be input as an interrupt to the OR gate I7. Further, the test pattern signal e is outputted from the AND gates 1-20 which open the gates 1-20 by inputting the test-on signal f from the external control system, and can be input to the OR gate 17 by interruption. The AND gate 18 opens when the inverted blank signal g' obtained by inverting the blank signal g by the inverter 33 arrives. The signal generating circuit 111 also outputs a blank No. 100 g, a clock signal h, a horizontal Harisode signal l determining the horizontal effective range of the luminance signal, a horizontal synchronizing signal j, and a dynamic focus signal k.

Figure 4 shows the image (image) generated by the video signal at 0F.
This shows the horizontal scanning timing of OF 'r3 when reproducing at T3.A horizontal sweep signal j' is formed in the drive/amplifier circuit 9 by the horizontal synchronization signal j, and the forward period t1 of this horizontal sweep signal j' is A beam whose brightness partially corresponds to the video signal is scanned in the horizontal forward direction, and returns in the reverse period t2. In addition, the horizontal varisoto signal i,
The blank signal g is set so that the video signal is swept within the image forming range L2 within the self-effective range L1 of ○FT3.
This is a signal sent from the signal generation circuit 11 to a hiteo signal generation section (not shown) so that the video signal is outputted in a timely manner.

Figure 5 shows the timing of each horizontal scanning signal for the lifetime scanning of ○FT3 when reproducing an image based on punch pattern signal C2 or test pattern signal e on 0FT3. Since this corresponds to the period when no test is performed, the video signal is not input, and the AND gate 19 is opened by the punch-on signal d, or the test signal is not input.
When the AND gate 20 is opened by the ON signal f, the
Notch pattern signal C5 or test pattern signal e
are respectively input from the signal generating circuit 11 to the OR gate 17.

FIG. 6 is an explanatory diagram of the recording operation state, and shows the photosensitive drum I.
The relationship between the images formed on the surface of the image is shown expanded in the sub-scanning direction (indicated by the arrow ■) (arrow H indicates the main scanning direction). The image E shown in FIG.
1, but the image C generated by the punch pattern signal C is generated during a period when no recording is performed on the copy paper 2, that is, outside the vertical valid signal output period, and when the punch-on signal is output. It is formed. This image C, while being formed on the photosensitive drum 1, is detected by a photosensor 8 not shown in FIG.
It is input to 0 and used for controlling the toner replenishment valve 4a of the developing section 4.

As shown in FIG. 7, the dynamic adjustment signal output from the signal generation circuit 111 is converted into a signal as shown in FIG. It is converted into a bottom make voltage (2) and applied to 0FT3. This focus signal contains 6 +1lil
Taking as an example a signal that changes with one cycle as one cycle, the pulse train is 10f)0.00°100000 at the left end of FIG. 8, and 0IIIL 011111 at the right end.

The number of clocks for this cycle can be set to 6 or 8. The D/A conversion circuit 22 has a type of pulse width. h-pressure converter, which includes a Swissochinku Trannostar 23, a Suinochinku Inno 1 to lance 24, a rectifying diode 25, an integrating capacitor 26, a discharge resistor 27,
Human resistance 28, bias electric lIK! 29, and retrograde
It is composed of a C1 force absorbing tie-auto 30, and is applied to an input terminal 31 for a dynamic nail signal.

Then, a curved focus voltage ■ is generated from the output terminal 32 for each scan, and the out-of-focus caused by the linear fluorescent surface of the OF T 3 is corrected.

Incidentally, in order to increase the number of program signals to be outputted in the signal generation circuit 11 described above, as shown in FIG.
, 142 in its ROM 14.

It is sufficient to provide latches 15+ and i52 corresponding to the number of latches 142.

Furthermore, in the above embodiment, the clear timing data is stored in the ROM 14 so that the counter 13 is cleared at a predetermined count time, and the data is cleared by the 1-bit output of the latch 15. counter 1
The overflow output of 3 may be applied to the clear terminal to force clear. In this case, the signal is generated cyclically and a continuous signal generator can be realized.・In addition, an external signal of a different system from the various signals output from the latch 15, such as an edge beam detection signal (Bohm position return signal) that detects the maximum deflection position of the beam, is applied to the clear terminal and It may be automatically cleared every time the beam scans.

Furthermore, although the above embodiments have been described with respect to an electrophotographic recording device, the signal generating device according to the present invention can also be applied to devices that require predetermined program signals for multiple channels, such as synthesizers, and others. Of course.

In addition, the present invention can be applied not only to the type of exposure device that uses OFT, but also to laser scanning devices that are controlled by electrical signals, and can also be used to drive and control various other mechanical parts of the exposure device. A generator can be used.

(Structure of the Invention) As described above, the signal destination 4L device according to the present invention includes a memory having parallel outputs, a counter for counting clock input and addressing the memory according to the count value, and a parallel connection of the memory. A launcher for holding an output is provided, and a program signal is generated from the output of each bit of the parallel output of the launcher in accordance with the program input.

(Effect of the invention) Therefore, when generating multiple program signals, conventionally many counters, digital comparators, and gates were required, but with the present invention, only one counter is required. Not only does the circuit become extremely simple, but the program E numbers to be generated can be changed by simply changing the contents of the memory, and the number of program signals can be increased simply by adding memory and launches.

In addition, since the output of the ROM, which is addressed by a single clock and output simultaneously in parallel, is used as the program signal, the time or phase relationship between each signal can be reproduced extremely accurately, using multiple counters and gate circuits. There is no risk of unstable operation due to synchronization failure or unevenness of signal delay times that occur when the configuration is configured as shown in FIG.

Furthermore, since the output of the ROM is first input to the launch before generating various signals, reliable operation is ensured without transient malfunctions or noise generation when the clock changes or when the counter is switched. You can expect it.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of an electrophotographic recording device, Fig. 2 is a schematic circuit diagram of a signal generation circuit according to the present invention, Fig. 3 is an explanatory diagram of the action of signals necessary for exposure scanning, and Fig. 4 is an exposure scanning diagram. 5 is a timing chart of the horizontal scanning of the Tetos pattern signal and batch pattern signal, FIG. 6 is an explanatory diagram of recording image formation, and FIG. 7 is the D /A conversion circuit circuit diagram, Figure 8 is a characteristic diagram of dynamic focus signal and focus voltage,
FIG. 9 is a circuit diagram of another embodiment of the signal generating circuit. 11.111...Signal generation times (Raku, 13...Counter, 14...ROM, 15...Lunch. Patent applicant Tsuneaki Nagao, patent attorney, Konishiroku Photo Industry Co., Ltd.

Claims (1)

[Claims] a memory having a parallel output; a counter for counting a clock input and addressing the memory according to the count; and a launch for holding the parallel output of the memory; A signal generating device characterized in that a program signal is generated from the output of each bit of the output.