JPS59129209U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS59129209U
JPS59129209U JP2255383U JP2255383U JPS59129209U JP S59129209 U JPS59129209 U JP S59129209U JP 2255383 U JP2255383 U JP 2255383U JP 2255383 U JP2255383 U JP 2255383U JP S59129209 U JPS59129209 U JP S59129209U
Authority
JP
Japan
Prior art keywords
pair
muting
power
voltages
clamping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2255383U
Other languages
Japanese (ja)
Inventor
和男 黒田
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP2255383U priority Critical patent/JPS59129209U/en
Publication of JPS59129209U publication Critical patent/JPS59129209U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来のミューティング回路の例を示
す図、第3図〜第7図は本考案の実施例の回路を夫々示
す図である。 主要部分の符号の説明、1・・・信号ライン、2・・・
ミューティング用トランジスタ、6・・・クランプ用ト
ランジスタ、D6.D7・・・ダイオード、D8・・・
ツェナーダイオード、C6,、C7・・・コンデンサ。 す5V o−一−4−−−丁−7え−(l;■Jでつ1
1−二371−1ζトー2育目−・ 1 517 す5V ゛′汁予♀” −1−、I D=9亨多 tz’、  1
1 and 2 are diagrams showing examples of conventional muting circuits, and FIGS. 3 to 7 are diagrams showing circuits according to embodiments of the present invention, respectively. Explanation of symbols of main parts, 1...Signal line, 2...
Muting transistor, 6... Clamping transistor, D6. D7...Diode, D8...
Zener diode, C6, C7... capacitor. Su5V o-1-4---D-7E-(l;■J detsu1
1-2371-1ζTo 2nd Ikume-・ 1 517 Su5V ゛′ Juice♀” -1-, ID=9亨多tz', 1

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)信号ラインと基準電位点との間に設けられたミュ
ーティングスイッチを有するミューティング回路であっ
て、前記基準電位点の電位を中間に有する1対の電圧を
発生する1対の電源と、前記1対の電圧の1方により充
電されこの充電電圧が前記ミューティングスイッチの制
御端子へ供給された蓄電手段と、前記電源オン時から所
定期間及び電源オフ時を除く残余の期間前記制御端子を
略前記1対の電圧の他方にクランプするクランプ手段と
を含むことを特徴とするミューティング回路。
(1) A muting circuit having a muting switch provided between a signal line and a reference potential point, the muting circuit including a pair of power supplies that generate a pair of voltages having the potential of the reference potential point in between. , a power storage means charged with one of the pair of voltages and this charging voltage being supplied to the control terminal of the muting switch; and the control terminal for a predetermined period from the time the power is turned on and for the remaining period excluding the time the power is turned off. clamping means for clamping substantially the other of the pair of voltages.
(2)前記クランプ手段は、前記電源のオン動作に応答
して所定時定数をもって前記1方の電圧へ向けて立上り
また前記電源のオフ動作に応答して略瞬時に立下る時定
数回路と、前記時定数回路の出力電圧が所定値以上のと
き前記クランプ動作をなすスイッチング素子とからなる
ことを特徴とする実用新案登録請求の範囲第1項記載の
ミューティング回路。
(2) the clamping means includes a time constant circuit that rises toward the one voltage with a predetermined time constant in response to an on operation of the power source and falls almost instantaneously in response to an off operation of the power source; 2. The muting circuit according to claim 1, further comprising a switching element that performs the clamping operation when the output voltage of the time constant circuit is equal to or higher than a predetermined value.
JP2255383U 1983-02-18 1983-02-18 Muting circuit Pending JPS59129209U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2255383U JPS59129209U (en) 1983-02-18 1983-02-18 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2255383U JPS59129209U (en) 1983-02-18 1983-02-18 Muting circuit

Publications (1)

Publication Number Publication Date
JPS59129209U true JPS59129209U (en) 1984-08-30

Family

ID=30153649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2255383U Pending JPS59129209U (en) 1983-02-18 1983-02-18 Muting circuit

Country Status (1)

Country Link
JP (1) JPS59129209U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027756B2 (en) * 1971-10-20 1975-09-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027756B2 (en) * 1971-10-20 1975-09-10

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