JPS59127856A - Semiconductor integrated circuit device with multiple layered semiconductor chip - Google Patents

Semiconductor integrated circuit device with multiple layered semiconductor chip

Info

Publication number
JPS59127856A
JPS59127856A JP58003092A JP309283A JPS59127856A JP S59127856 A JPS59127856 A JP S59127856A JP 58003092 A JP58003092 A JP 58003092A JP 309283 A JP309283 A JP 309283A JP S59127856 A JPS59127856 A JP S59127856A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
semiconductor integrated
chips
ceramic layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58003092A
Other languages
Japanese (ja)
Inventor
Makoto Harigaya
針ケ谷　誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58003092A priority Critical patent/JPS59127856A/en
Publication of JPS59127856A publication Critical patent/JPS59127856A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Abstract

PURPOSE:To enable the titled device to be miniaturized by a method wherein smaller semiconductor integrated circuit chips are successively deposited on larger semiconductor integrated circuit chips contained in a container. CONSTITUTION:Memories 2, 3, 4 are connected with one another on a microcomputer 1 by means of bumps 10 to form chips like a pyramid. A container is provided with holes respectively with the same sizes as that of a chip 1 on the first ceramic layer 16, a chip 2 on the second ceramic layer 15, a chip 3 on the third ceramic layer 14, an another chip 4 on the fourth ceramic layer 13. In the fifth ceramic layer, internal leads are formed on the same position as that of the bump on the chip 4 and the chips 1, 2, 3 on the second, third and fourth ceramic layers. Each layer is deposited to be sintered while the deposited chips are sealed 18 being fixed by pressure of another bump 11. Through these procedures, the titled device may improve integration thereof having no influence upon the miniaturization as the merit of LSI.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置に係り、特にその容器に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a container thereof.

通常、半導体集積回路残置はシリコンウェハー上に拡散
、メタライズ等を行ｔ【（・半導体集積回路残置を製造
したウェハーをチップに切断しプラスチック、セラミッ
ク等の容器に入れ使用している。Normally, the remaining semiconductor integrated circuit is processed by diffusion, metallization, etc. on a silicon wafer.(The wafer on which the remaining semiconductor integrated circuit is manufactured is cut into chips and placed in a container made of plastic, ceramic, etc.).

この場合容器の中には１つのチップが入っており、この
チップはケースのリードとボンディング線にて接続され
ている（第１，２図）。In this case, one chip is contained in the container, and this chip is connected to the leads of the case by bonding wires (FIGS. 1 and 2).

近年、技術の発達により集積度の高い半導体集積回路残
置（ＬＳＩ）が必要とされてきて（・る。In recent years, with the development of technology, there has been a need for highly integrated semiconductor integrated circuits (LSI).

従来の方法では集積度が高くなるとチップが大型化し、
それに伴い半導体集積回路装置を収納している容器も大
型化し、Ｔ、　Ｓ　Ｉ化の長所である小型化の効果が沖
少するという欠点、が生じる。また、従来の方法である
パッドをチップの周囲の配置する方式ではチップの大き
さでパッドの数が限定され外部リード数が制限されると
いう欠点が生じる。In conventional methods, the higher the degree of integration, the larger the chip.
As a result, the size of the container that houses the semiconductor integrated circuit device also increases, resulting in the disadvantage that the advantage of miniaturization, which is an advantage of T and SI, is diminished. Further, the conventional method of arranging pads around the chip has the disadvantage that the number of pads is limited depending on the size of the chip, and the number of external leads is limited.

本発明はチップをピラミッド形に積み重ねることにより
容易に集積度を上げることが可能になりまた、各層のチ
ップの周囲にパッドを形成することができるためチップ
サイズ、パッケージサイズを大きくするととソよく外部
リード数を堀加することを容易に可伴にする半導体集積
回路装置及びその容器を枡供するものである。In the present invention, it is possible to easily increase the degree of integration by stacking chips in a pyramid shape.In addition, since pads can be formed around the chips in each layer, when the chip size and package size are increased, external The present invention provides a semiconductor integrated circuit device and a container for the same, which makes it easy to increase the number of leads.

本発明の半導体集積回路装置及びその容器は半導体集積
回路装置を順次積み重ねピラミッド形にすることを特徴
とする。The semiconductor integrated circuit device and its container of the present invention are characterized in that the semiconductor integrated circuit devices are stacked one after another in a pyramid shape.

以下、本発明の詳細な説明する。The present invention will be explained in detail below.

第３図は従来のセラミ、クパッケージを使用した半導体
集積回路装置の例を示す。第４図は本発明実施例を説明
する為の図である。本発明はチップ１の上部にチップ２
を積み重ねその上にチップを順次積み重ね集輔度を上げ
必要に応じてチップ１゜チップ２．その他のチップ相互
を接続し各チップに形成したバンプ１１にて容器のリー
ドと接続するものである。積み重ねるチップ数はチップ
面積が許すかぎり可能であり集積度は数便、に上げるこ
とが可能である。また外部リードもチップから直接引き
出せるためチップが１個だけの場合よりリード数が数倍
かつ配線長も知くなるため＾Ｐ線抵抗も減少させること
か可能である。FIG. 3 shows an example of a semiconductor integrated circuit device using a conventional ceramic package. FIG. 4 is a diagram for explaining an embodiment of the present invention. In the present invention, the chip 2 is placed on top of the chip 1.
Stack the chips one after another on top of it to increase the density of chip 1, chip 2, etc. as necessary. The other chips are connected to each other and connected to the leads of the container using bumps 11 formed on each chip. The number of chips to be stacked can be determined as long as the chip area allows, and the degree of integration can be increased to several orders of magnitude. In addition, since the external leads can be drawn directly from the chip, the number of leads is several times that of a case where there is only one chip, and the wiring length is also known, so it is possible to reduce the P-line resistance.

本発明をセラミックケース、チップをマイクロコンピュ
ータ、メモリーに適用した実施ｆ１１を示す。Embodiment f11 is shown in which the present invention is applied to a ceramic case, a chip to a microcomputer, and a memory.

従来マイクロコンピュータ、メモリーは別々のケースに
収容され基板上で結線されていた（第５図）。Conventionally, microcomputers and memory were housed in separate cases and connected on the board (Figure 5).

この様な方法ではメモリーの数が多くなると基板が大型
化する欠点がある。本発明を適用すれば１つの容器内に
すべてのメモリーを収容できるため非常に小型化が可能
である。This method has the disadvantage that the larger the number of memories, the larger the board becomes. By applying the present invention, all memories can be accommodated in one container, making it possible to significantly reduce the size.

第６図は本発明の実施例である。マイクロコンピュータ
１上にメモリー２をバンプ１０にて結線する。同様にメ
モ！Ｊ−３，４をバンプ１０にて結線しチップをピラミ
ッド形に形成する。容器は第７図に示す様に第１層目セ
ラミック１６にチップ１と同じ大きさの穴を中心にあけ
る。同様に第２層目セラミック１５はチップ２．第３層
目セラミック１４はチップ３．第４層目セラミック１３
はチップ４と同じ大きさに穴をあける。第５層目セラミ
ックにはチップ４上のバンプと同位置に内部リードを形
成する。第２．３．４層目セラミックにはチップ１，２
．３のバンプと同位置に内部リードを形成する。各層を
積み重ね焼結する。外部リードの取り出し方式はＤＩＰ
、ＰＩＦ形式その他の方式で取り出し可能である。焼結
したセラミックケースにピラミッド形に積み重ねたチッ
プをバンプ１１にて圧着してシール１８をする（第８図
）。FIG. 6 shows an embodiment of the present invention. A memory 2 is connected to a microcomputer 1 using bumps 10. Note as well! J-3 and J-4 are connected with bumps 10 to form a chip into a pyramid shape. For the container, as shown in FIG. 7, a hole of the same size as the chip 1 is made in the center of the first layer ceramic 16. Similarly, the second layer ceramic 15 is chip 2. The third layer ceramic 14 is chip 3. 4th layer ceramic 13
Drill a hole the same size as chip 4. Internal leads are formed in the fifth layer of ceramic at the same positions as the bumps on the chip 4. Chips 1 and 2 for the 2nd, 3rd and 4th layer ceramics
．． Form an internal lead at the same position as bump 3. Each layer is stacked and sintered. External lead extraction method is DIP
, PIF format and other methods. Chips stacked in a pyramid shape are pressed into a sintered ceramic case using bumps 11 to form a seal 18 (FIG. 8).

以上のようにチップ、ケースを形成すれば１つの容器の
中に数種類のチップを混載することができ、かつＬＳＩ
の長所である小型化の効果を減することなく容易に集積
度を上げることが可能である。By forming chips and cases as described above, several types of chips can be mixed in one container, and LSI
It is possible to easily increase the degree of integration without reducing the advantage of miniaturization.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来のセラミック、プラスチック封止
の例である 第３図は従来のセラミックケース入すの半導体集積回路
装置の断面図である。第４図は本発明の断面図である。 第５図はマイクロコンピュータ、メモリーをプリント基
板上に実装した平面図である。第６図、第７図はセラミ
ックに適用した本発明である。第６図はチップ、第７図
はケースの断面図である。第８図は本発明のケースとチ
ップを実装した時の断面図である。 なお図において、１〜４・・・・・・半導体集積回路チ
、プ、５・・・・・・ボンディング線、６・・・・・・
ケース内部パターン、７・・・・・・マイクロコンピー
タ、８・・・・・・　５− メモリー、９・・・・・・プリント基板、１０・・・・
・・チャ１間接続用バンプ、１１・・・・・・ケース接
続用バンプ、１２・・・・・・第５層目セラミック、１
３・・・・・・第４層目セラミック、１４・・・・・・
第３層目セラミック、１５・・・・・・第２層目セラミ
ック、１６・・・・・・第１層目セラミック、１７・・
・・・・外部リード、１８・旧・・シール、である。 　６− 第１図 第７図 第　３　図 第　４図 第Ｓ　図 第　６　図 第　７図 乃　８図1 and 2 are examples of conventional ceramic and plastic sealing. FIG. 3 is a sectional view of a semiconductor integrated circuit device housed in a conventional ceramic case. FIG. 4 is a cross-sectional view of the present invention. FIG. 5 is a plan view of a microcomputer and memory mounted on a printed circuit board. Figures 6 and 7 show the present invention applied to ceramics. FIG. 6 is a sectional view of the chip, and FIG. 7 is a sectional view of the case. FIG. 8 is a sectional view when the case and chip of the present invention are mounted. In the figure, 1 to 4...semiconductor integrated circuit chips, 5...bonding lines, 6...
Case internal pattern, 7... Microcomputer, 8... 5- Memory, 9... Printed circuit board, 10...
... Bump for connection between chassis 1, 11 ... Bump for case connection, 12 ... Fifth layer ceramic, 1
3...4th layer ceramic, 14...
3rd layer ceramic, 15... 2nd layer ceramic, 16... 1st layer ceramic, 17...
... External lead, 18. Old... Seal. 6- Figure 1 Figure 7 Figure 3 Figure 4 Figure S Figure 6 Figure 7 to Figure 8

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路残置にお（・て、容器内に収められた半
導体集積回路チップ上にそれより小さく・半導体集積回
路チップが順次積み重ねられて（・ることを特徴とする
多層半導体チップを有する半導体集積回路残置。A semiconductor integrated circuit having a multilayer semiconductor chip, characterized in that smaller semiconductor integrated circuit chips are sequentially stacked on top of a semiconductor integrated circuit chip housed in a container. Circuit left behind.
JP58003092A 1983-01-12 1983-01-12 Semiconductor integrated circuit device with multiple layered semiconductor chip Pending JPS59127856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58003092A JPS59127856A (en) 1983-01-12 1983-01-12 Semiconductor integrated circuit device with multiple layered semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58003092A JPS59127856A (en) 1983-01-12 1983-01-12 Semiconductor integrated circuit device with multiple layered semiconductor chip

Publications (1)

Publication Number Publication Date
JPS59127856A true JPS59127856A (en) 1984-07-23

Family

ID=11547697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58003092A Pending JPS59127856A (en) 1983-01-12 1983-01-12 Semiconductor integrated circuit device with multiple layered semiconductor chip

Country Status (1)

Country Link
JP (1) JPS59127856A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
FR2701153A1 (en) * 1993-02-02 1994-08-05 Matra Marconi Space France Semiconductor memory component and module.
US6452279B2 (en) * 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US7279783B1 (en) * 2003-10-29 2007-10-09 Silicon Pipe, Inc. Partitioned integrated circuit package with central clock driver
US9657838B2 (en) 2012-05-28 2017-05-23 Kabushiki Kaisha Riken Combined oil control ring
KR20220131493A (en) * 2021-03-19 2022-09-28 난통 엑세스 세미컨덕터 컴퍼니 리미티드 Embedded packaging structure and manufacturing method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
FR2701153A1 (en) * 1993-02-02 1994-08-05 Matra Marconi Space France Semiconductor memory component and module.
EP0614190A1 (en) * 1993-02-02 1994-09-07 Matra Marconi Space France Semiconductor memory module and component
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US6452279B2 (en) * 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US7279783B1 (en) * 2003-10-29 2007-10-09 Silicon Pipe, Inc. Partitioned integrated circuit package with central clock driver
US9657838B2 (en) 2012-05-28 2017-05-23 Kabushiki Kaisha Riken Combined oil control ring
KR20220131493A (en) * 2021-03-19 2022-09-28 난통 엑세스 세미컨덕터 컴퍼니 리미티드 Embedded packaging structure and manufacturing method thereof
JP2022145598A (en) * 2021-03-19 2022-10-04 ナントン アクセス セミコンダクター シーオー．，エルティーディー Embedded packaging structure and manufacturing method thereof

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