JPS59127416A - Multistage voltage comparator - Google Patents

Abstract

PURPOSE:To simplify the constitution of a comparator which has plural decision ranges by ORing outputs of plural window comparators. CONSTITUTION:An analog signal VIN is supplied to N units of window comparators WC1-WCN in common and their outputs VW1 and VWN are ORed by an OR gate OR, which generates an output VOUT. When the analog signal VIN is within the window ranges of the window comparators WC1-WCN, the output VOUT goes up to a high level, and when not, the output goes down to a low level, obtaining N decision ranges. Therefore, a signal processing circuit is simplified even when the number of the required comparators is the same.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multistage voltage comparator that has a plurality of comparison standards for an analog comparison input and obtains an output for determining the level of the analog comparison input.

A conventional multi-stage voltage comparator supplies an analog signal as a common input to a plurality of comparators each having a different comparison standard, and separates the analog signal from the on/off output of each comparator. In this level discrimination, the output of each comparator only specifies one discrimination range corresponding to the analog signal, but in order to obtain signals that specify multiple discrimination ranges, the output of each comparator is processed by a complex signal processing circuit. I needed to.

An object of the present invention is to provide a multistage voltage comparator that has a plurality of discrimination ranges and does not have a complicated configuration by taking the logical sum of the outputs of a plurality of window comparators.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Comparison standard v1 (!: Vs + Vl (!:
N'4 + ''', v,, -8 and ■0..., v,
, , and vgN are given, and the comparison standard is VtK-i (V, , (v, to, (where =
1.2.・ , N), and the analog signal vIN is (11Vl)I > Vex or v, N <
The input/output characteristics are designed so that when 'II K-1, a low level output (2) vs &-1<V, and a high level output when <vsxo.

Each window comparator WC8~Wool O output Vv
t~■, N are input to the gate of the OR gate OR, and the logical sum is taken by the OR gate, and the output is output.

The window comparators WC1 to WO have the configuration shown in FIG. 2, for example. Analog signal v1. is made into a non-inverting input of comparator vC2, and comparator VC7
It becomes the inverted input of the comparator vC□, and becomes the inverted input of the comparator vC□■
, -0 is given, and a comparison reference of v9 is given to the non-inverting input of the comparator VC,. The outputs vvt+vvg of both comparators vc, , vc are ant gates consisting of diodes D1+DI and resistors R).
is input to obtain vWK as its output. With this configuration, the analog signal vIN is the comparison standard. −□ and ■. If it is within the range of , a high level output can be obtained at the output ■Wx.

A plurality of such window comparators are provided as shown in FIG. 1, and the analog signal V+x7 is used as a common input, and each output is the output V when the OR is performed. . 1 becomes the logic state shown in FIG. 3 depending on the level of the analog signal V, , . That is, the analog signal ■ is the comparison standard ■,
Below is the output■. . 7 is low level, and within the range of ■ and V, ■. , is at high level, and is at low level in the range of , and v, so that ii V and ua are at high level within the window width range of each window comparator, and are at low level elsewhere.#)1 This means that it has N discrimination ranges.

The multistage voltage comparator according to this embodiment can be applied to a circuit or device that requires a plurality of discrimination ranges to reduce the number of circuit components. For example, if the detection analog signal in a static protective relay is within the voltage range "'I+8" shown in Figure 4,
The protection output is obtained only when the input range is S4, and the protection output is not output in the input range under special conditions in the range S and S6.

Now, when setting the protection range in which no protection output is output within the normal input range, five discrimination ranges are required, and the conventional circuit requires four comparators and a signal processing circuit powered by four people. In this embodiment, only two window comparators and one OR gate are required, and the signal processing circuit is simplified even though the required number of comparators is the same.

Furthermore, this embodiment can be applied as a frequency multiplier, and as shown in FIG. When five window comparators are configured as shown in Figure 1 and the logical sum of their outputs is taken, the output ■. , JT has a pulse frequency (period T,, JT) that is 10 times the frequency (period ToW) of the triangular wave input V8, and can further convert this into a triangular wave to obtain a triangular wave signal 10 times as large. . On the other hand, conventional triangular wave multiplication requires a multi-stage cascade connection of full-wave rectifier circuits and amplifiers, resulting in a complicated configuration and making it difficult to obtain an odd multiplication frequency.

Furthermore, in this embodiment, the comparator WC□ or W is not made into a window comparator, but instead is made into a normal comparator having one comparison standard, so that every time an odd reference voltage is exceeded, an output ■ is generated. A circuit in which uT is inverted can also be constructed.

As described above, according to the present invention, a comparator having a relatively simple configuration and having a plurality of discrimination ranges can be obtained, and has the advantage that it can be applied to frequency multiplier circuits and the like.

[Brief explanation of drawings]

1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the window comparator in FIG. 1, and FIG. 8 is an input/output waveform diagram of FIG. 1. FIG. 4 is a determination range explanatory diagram showing an example of application of the present invention. FIG. 5 is an input/output waveform diagram showing another example of application of the present invention. WOl, WCg, WOK, WCll...
Window comparator. OR...or'f Yet I vc,・
··comparator. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] Multiple window comparators with an analog signal as a common comparison input and a pair of different comparison reference voltages set, and outputs with multiple discrimination ranges for the analog signal using the outputs of these window comparators as gate inputs. A multistage voltage comparator characterized by comprising an OR circuit that obtains the following.