JPS59126382A - Switching circuit - Google Patents

Switching circuit

Info

Publication number
JPS59126382A
JPS59126382A JP129183A JP129183A JPS59126382A JP S59126382 A JPS59126382 A JP S59126382A JP 129183 A JP129183 A JP 129183A JP 129183 A JP129183 A JP 129183A JP S59126382 A JPS59126382 A JP S59126382A
Authority
JP
Japan
Prior art keywords
capacitor
transistor
circuit
switching circuit
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP129183A
Other languages
Japanese (ja)
Inventor
Takashi Yonenaga
米永 隆志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP129183A priority Critical patent/JPS59126382A/en
Publication of JPS59126382A publication Critical patent/JPS59126382A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

Abstract

PURPOSE:To block discharge of a capacitor for a prescribed time when a power supply is interrupted by providing an impedance means between a capacitor of a switching circuit and ground and blocking a forward bias from being applied to a transistor(TR) when the power supply is turned off to prevent a remarkable voltage drop of a connecting point of the switching circuit when the TR is turned on. CONSTITUTION:Since a capacitor C1 is charged via a resistor R5 and a diode D1 even at the receiving of a PAL signal where a TRQ1 is turned off, even if the circuit is switched to the receiving of an SECAM signal from this state, the value of the voltage drop at a connecting point (a) is decreased when the TRQ1 is turned on. When the power supply is turned on at the SECAM receiving state where a capacitor C5 is charged where the TRQ1 is turned on, a base potential of the TRQ1 becomes -E1 and a collector potential V2 becomes -E2 by the discharge of capacitors C5, C1, where E1 is the switching voltage at an input terminal (b) and E2 is the voltage at the connecting point (a), and the potential V1 after (t) seconds, becomes V1=-E1exp(-t/(R1C5). When the potential V1 is lower than the V2, the base and collector of the TRQ1 is biased reversely, allowing to block the discharge of the capacitor C1.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は正変調テレビジョン信号(SECAM信号)も
負変調テレビジョン信号(PAL信号)も受信可能なテ
レビジョン受像機の自動利得制御回路(以下AGC回路
と略す)等に挿入されるコンデンサの切替え回路に関す
る、 (ロ)従来技術 第1図に従来の切替え回路を備える正変調SECAM信
号も負変調PAL信号も受信可能なテレビジョン受像機
のAGC回路の一実施例を示す。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to an automatic gain control circuit for a television receiver capable of receiving both positive modulation television signals (SECAM signals) and negative modulation television signals (PAL signals). (hereinafter abbreviated as AGC circuit), etc. (b) Prior art A television receiver capable of receiving both positive modulation SECAM signals and negative modulation PAL signals, which is equipped with a conventional switching circuit as shown in Figure 1. An example of an AGC circuit is shown below.

第1図に於いて、(1)は映像信号増幅回路(図示せず
)よりAGC信号を形成するAGC信号検出回路、(2
)は入力端子(blに印加される切替え電圧によりトラ
ンジスタ(Ql)のオン、オフを制御してコンデンサ(
C1)の作動状態と不作動状態を切替える切替え回路、
(3)は抵抗(R2) (R3’) %コンデンサ(C
2) (C5) (C4)、コイル(Ll)よりなりA
GC信号検出回路(1)の出力信号を平滑する平滑回路
、(4)はへ〇C信号を増幅して映像中間周波増幅回路
(図示せず)及び高周波増幅回路(図示せず)にAGC
信号を印加するAGC信号増幅回路、(5)はAGC信
号検出回路(1)平滑回路(31A G C信号増幅回
路(4)よりなる電圧発生回路であり、この場合電圧発
生回路(5)で発生される電圧はAGC電圧である。(
alは平滑回路(3)とコンデンサ(C1)の接続点を
示す。
In FIG. 1, (1) is an AGC signal detection circuit that forms an AGC signal from a video signal amplification circuit (not shown);
) is a capacitor (
C1) a switching circuit that switches between an active state and a non-active state;
(3) is resistance (R2) (R3') % capacitor (C
2) Consisting of (C5) (C4) and coil (Ll) A
A smoothing circuit smoothes the output signal of the GC signal detection circuit (1), and (4) amplifies the C signal and sends it to a video intermediate frequency amplification circuit (not shown) and a high frequency amplification circuit (not shown).
The AGC signal amplification circuit that applies the signal, (5) is a voltage generation circuit consisting of the AGC signal detection circuit (1) and the smoothing circuit (31A G C signal amplification circuit (4); in this case, the voltage generated by the voltage generation circuit (5) The voltage applied is the AGC voltage. (
al indicates a connection point between the smoothing circuit (3) and the capacitor (C1).

(ICI)は映像信号処理用の集積回路(例えば、三菱
電機株式会社製M51356 P )、■■は集積回路
(■C1)の端子ピン番号である。尚第一図に於いてコ
ンデンサ(C1)の値は100μFである。
(ICI) is an integrated circuit for video signal processing (for example, M51356P manufactured by Mitsubishi Electric Corporation), and ■■ is a terminal pin number of the integrated circuit (■C1). In FIG. 1, the value of the capacitor (C1) is 100 μF.

第1図のようなAGC回路に於いては、負変調FAI−
信号受信時にはトランジスタ(Ql)をオフにして映像
信号のピーク値(同期信号部分)を検出してAGC信号
を一定にするピーク値型AGC動作を行なっている。し
かし、正変調SECAM信号はピーク値か輝度信号部分
にあるためピーク値型AGC動作を行なうと画面の内容
により輝度ムラか発生する。このため正変調SECAM
信号受信信号受信人端子(blに切替え電圧を印加して
トランジスタ(Ql)をオンにして、コンデンサ(C1
)を平滑回路(3)に接続して平滑回路(3)の時定数
を増加させ平均値型AGC動作を行ない、正変調SEC
AM信号受信信号受信人ラが発生することを防いでいる
In the AGC circuit as shown in Fig. 1, negative modulation FAI-
When receiving a signal, a peak value type AGC operation is performed in which the transistor (Ql) is turned off, the peak value (synchronizing signal portion) of the video signal is detected, and the AGC signal is kept constant. However, since the positively modulated SECAM signal has a peak value or a luminance signal portion, when peak value type AGC operation is performed, luminance unevenness occurs depending on the content of the screen. Therefore, positive modulation SECAM
Signal reception Apply a switching voltage to the signal receiver terminal (bl) to turn on the transistor (Ql) and turn on the capacitor (C1
) is connected to the smoothing circuit (3) to increase the time constant of the smoothing circuit (3), perform average value type AGC operation, and perform positive modulation SEC.
This prevents AM signal reception signal failure from occurring.

しかし、この様な切替え回路(2)では、トランジスタ
(Ql)がオンになった時、接続点(alの電位は一度
O■まで降下しコンデンサ(C1)が充電されるにつれ
上昇し、もとの電位にもどる。この間AGC回路の出力
電圧が低くなるため高周波増幅回路(図示せず)及び映
像中間周波増幅回路(図示せず)の増幅度が増加し映像
信号が必要以上に増幅される。よって受像管は、まつ白
な状態となり、テレビジョン受像機の品位を損ねるとい
う欠点を有する。又この様な症状はトランジスタ(Ql
)がオンの時テレビジョン受像機の電源をオフにした後
、再び電源をオンにした時も表われる。これは電源かオ
フの間にコンデンサ(C1)の電荷か第4図に示すよう
にAGC信号増幅回路(4)及び切換え電圧源インピー
ダンス(R+)、抵抗(R1)、トランジスタ(Ql)
のベース・コレクタ間PN接合を介してすばやく放電さ
れるため、電源を再びオンにした時にコンデンサ(C1
)が再び循電されるためである。
However, in such a switching circuit (2), when the transistor (Ql) is turned on, the potential at the connection point (al) once drops to O■, rises as the capacitor (C1) is charged, and returns to its original state. During this time, the output voltage of the AGC circuit becomes low, so the amplification degree of the high frequency amplifier circuit (not shown) and the video intermediate frequency amplifier circuit (not shown) increases, and the video signal is amplified more than necessary. Therefore, the picture tube has the disadvantage that it becomes a blank state, which impairs the quality of the television receiver.Also, this symptom is caused by the transistor (Ql)
) is on, it also appears when the television receiver is turned off and then turned on again. This is due to the charge on the capacitor (C1) during the power off period.As shown in Figure 4, the AGC signal amplification circuit (4) and the switched voltage source impedance (R+), resistor (R1), transistor (Ql)
Because it is quickly discharged through the base-collector PN junction of the capacitor (C1
) is circulated again.

尚、テレビジョン受像機の電源をオフにしてからオンに
する間が長い場合には、電源をオフにした間に冷えた受
像管のヒーターか再び暖まり画像が映し出されるまでに
コンデンサ(C1)が充電されるため前述の様な症状は
表われない。
If the time between turning off and turning on the television receiver is long, the picture tube heater may have cooled down while the power was off, or the capacitor (C1) may have warmed up again before the image is displayed. Since the battery is being charged, the symptoms described above will not appear.

(ハ)発明の目的 本1/y+llは、上記の点に鑑みてなされたものであ
り、切替え回路のトランジスタかオフからオンになった
時に切替え回路と電圧発生回路との接続点の電位か大幅
に降下するのを防止し、且つ電源を切って前記トランジ
スタ及び前記電圧発生回路をオフにした時、前記コンデ
ンサの放電を一定時間阻止することが可能な切替え回路
を提供するものである。
(c) Purpose of the Invention Book 1/y+ll was made in view of the above points, and it shows that when the transistor of the switching circuit is turned on from off, the potential at the connection point between the switching circuit and the voltage generating circuit is significantly increased. To provide a switching circuit that can prevent the voltage from dropping and prevent the capacitor from discharging for a certain period of time when the power is turned off to turn off the transistor and the voltage generating circuit.

に)発明の構成 本発明は切替え回路のコンデンサとアース間に切替え回
路のトランジスタに並列に接続され前記トランジスタか
オフのとき前記コンデンサを充電するか、その際前記コ
ンデンサを切替え回路に接続された電圧発生回路に実質
的に影響を与えないようにするインピーダンス手段と、
電源をオフにして前記トランジスタ及び前記電圧発生回
路をオフにしたとき、前記トランジスタのベースとエミ
、ツタ間のPN接合を通して順バイアスがかかるのを阻
止する阻止手段を設けたことを特徴とする特替え回路、 幡)実施例 第2図に本発明の切替え回路を備えるテレビジョン受像
機のAGC回路の一実施例を示す。尚第1図と対応する
部分には同一符号を付し重複説明を省略する。第2図に
於いて、(R1) (Cs )はトランジスタ(Ql)
がオフになった時、トランジス9 (Ql)のベース・
コレクタ間に一定時間逆バイアスをかけコンデンサ(C
1)の放電を阻止する手段を構成する抵抗とコンデンサ
、(D2)はトランジスタ(Ql)のベース・エミ・ツ
タ間に逆耐定格電圧以上の電圧が印加されトランジスタ
(Ql)が破壊されるのを防ぐためのダイオード、(R
s)はトランジスタ(Ql)がオフの時でもコンデンサ
(C1)を充電さすための抵抗、(Dl)はコンデンサ
(C1)か抵抗(R5)を介して放電するのを阻止する
ためのダイオードである。このダイオード(Dl)と抵
抗(R5)はインピーダンス手段を構成する。尚、第2
図に於いて抵抗(ILl ) (、艮5)は夫々39に
Ω、5.6にΩコンデンサ(C5)は22μFである。
2) Arrangement of the Invention The present invention provides a method for connecting a switching circuit capacitor in parallel with a switching circuit transistor between a switching circuit capacitor and ground to charge the capacitor when the transistor is off, or to charge the capacitor at a voltage connected to the switching circuit. impedance means that substantially do not affect the generating circuit;
A special feature characterized in that a blocking means is provided for blocking forward bias from being applied through a PN junction between the base, emitter, and ivy of the transistor when the power source is turned off to turn off the transistor and the voltage generating circuit. Switching circuit (Hata) Embodiment FIG. 2 shows an embodiment of an AGC circuit for a television receiver equipped with the switching circuit of the present invention. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant explanation will be omitted. In Figure 2, (R1) (Cs) is a transistor (Ql)
is turned off, the base of transistor 9 (Ql)
A capacitor (C
The resistor and capacitor (D2) that constitute the means for preventing the discharge of 1) are used to prevent the transistor (Ql) from being destroyed if a voltage higher than the reverse withstanding voltage is applied between the base, emitter, and ivy of the transistor (Ql). A diode to prevent (R
s) is a resistor to charge the capacitor (C1) even when the transistor (Ql) is off, and (Dl) is a diode to prevent discharging through the capacitor (C1) or resistor (R5). . This diode (Dl) and resistor (R5) constitute impedance means. Furthermore, the second
In the figure, the resistance (ILl) (5) is 39Ω, and the capacitor (C5) is 5.6Ω and 22μF.

%2図の回路に於いて、トランジスタ(Ql)かオフの
PAL信号受信時でもコンデンサ(C1)は抵抗(R5
)及びダイオード(Dl)を介して充電されるため、こ
の状態からSECAM信号受信に切換えてトランジスタ
(Ql)かオンになった時に接続点(alの電圧降下の
幅を小さく出来る。このため受像管の画面か過渡的にま
つ白となる事を防げる。
%2 In the circuit shown in the figure, even when receiving a PAL signal with the transistor (Ql) off, the capacitor (C1) is connected to the resistor (R5).
) and the diode (Dl), so when switching from this state to SECAM signal reception and the transistor (Ql) turns on, the width of the voltage drop at the connection point (al) can be reduced. This prevents the screen from turning white temporarily.

又、入力端子(b)に印加される切換え電圧をEl(V
)接続点(alの電圧をR2(Vlとすると、トランジ
スタ(Ql)がオン状態でコンデンサ(C5)か充電さ
れているSECAM受信状態において、テレビジョン受
像機の電源をオフにすると、コンデンサ(Cs)(C1
)の放電によりトランジスタ(Ql)のベース電位v1
は−E1(V)、コレクタ電位V2は−E2(V)とな
る。その【秒後のベース電位v1はV1=−Elexp
(It、C4)  −−−−(11式で表わされる。こ
のベース電位v1かコレクタ電位■2よりも低い場合ト
ランジスタ(Ql)のベース・コレクタ間は逆バイアス
となり、コンデンサ(C1)の放電を阻止できる。つま
り、V1=−E+exp (−エ、c4) < −R2
−・−・−・−(21式となる間は、コンデンサ(C1
)の放電を阻止出来る。
Also, the switching voltage applied to the input terminal (b) is set to El(V
) If the voltage at the connection point (al is R2 (Vl), then in the SECAM receiving state where the transistor (Ql) is on and the capacitor (C5) is charged, when the power of the television receiver is turned off, the capacitor (Cs )(C1
), the base potential v1 of the transistor (Ql)
is -E1 (V), and the collector potential V2 is -E2 (V). The base potential v1 after [seconds is V1=-Eexp
(It, C4) ---- (Represented by equation 11. If the base potential v1 is lower than the collector potential ■2, the base and collector of the transistor (Ql) will be reverse biased, and the discharge of the capacitor (C1) will be inhibited. It can be prevented.In other words, V1=-E+exp (-E, c4) <-R2
−・−・−・−(While formula 21 is obtained, the capacitor (C1
) can be prevented from discharging.

しかし、第2図の様な回路では、入力端子(blに印加
される切替え電圧をテレビシコン受像機の他の回路の切
替えにも使用している場合、コンデンサ(C1)の放電
阻止の時間を長くするため、コンデンサ(C5)の値を
大きくすると、コンデンサ(Cs)が充電されるまでの
間が長くなり、入力端子(blに印加される切替え電圧
の立ち上がりが遅くなり、他の回路の切替えが遅れてし
まう。又、放電阻止の時間を長くするため、抵抗(R1
)の値を太きすると、トランジスタ(Ql)のベースに
印加される電圧か低くなりトランジスタ(ql)か完全
なオン状態となりにくくなる。
However, in a circuit like the one shown in Figure 2, if the switching voltage applied to the input terminal (bl) is also used to switch other circuits of the television receiver, the time required to prevent the discharge of the capacitor (C1) is If you increase the value of the capacitor (C5) to increase the length of time, the time it takes for the capacitor (Cs) to be charged will become longer, the rise of the switching voltage applied to the input terminal (bl) will be delayed, and the switching of other circuits will be delayed. In addition, in order to prolong the discharge blocking time, the resistor (R1
) increases the voltage applied to the base of the transistor (Ql), which makes it difficult for the transistor (ql) to be completely turned on.

第6図に上記の事を鑑みてなされた本発明の他の実施例
を示す。尚第1図及び第2図と対応する部分には同一符
号を付して重複説明を省略する。
FIG. 6 shows another embodiment of the present invention made in view of the above. Note that parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and redundant explanation will be omitted.

第3図に於いて、(R1’)(Cs’)はコンデンサ(
C1)の放電を阻止する抵抗とコンデンサ、(Q2)は
トランジスタ(Ql)にダーリントン接続されたトラン
ジスタである。尚、第3図に於いて、コンデンサ(C5
)は10μFであり、抵抗(R1)(It6)は夫々2
20にΩ、4.7にΩである。
In Figure 3, (R1') (Cs') is a capacitor (
A resistor and a capacitor are used to prevent the discharge of C1), and (Q2) is a Darlington-connected transistor to the transistor (Ql). In addition, in Fig. 3, the capacitor (C5
) is 10 μF, and the resistors (R1) (It6) are each 2
20Ω and 4.7Ω.

第3図に示す様にトランジスタ(Ql)とダーリントン
接続したトランジスタ(Q2)によって抵抗(R1)の
値を非常に大きくしてもトランジスタ(Ql)を完全に
オン状態に出来る。又、抵抗(R1)の値を大きくとれ
るため、コンデンサ(C5)の値を小さく押さえる事が
出来る。このため、切替え電圧の立ち上がりが速(なり
、他の切替え回路への影響を小さくする事か出来る。又
、入力端子(b)に印加される切替え電圧を適当に選ぶ
ことにより第2図のトランジスタ(Ql)のベースの逆
耐保護用のダイオード(1) 2 )が省略出来る。
As shown in FIG. 3, the transistor (Q1) can be completely turned on even if the value of the resistor (R1) is made very large by connecting the transistor (Q2) with the transistor (Q1) in Darlington connection. Furthermore, since the value of the resistor (R1) can be made large, the value of the capacitor (C5) can be kept small. Therefore, the switching voltage rises quickly (and the influence on other switching circuits can be reduced).Also, by appropriately selecting the switching voltage applied to the input terminal (b), the transistor shown in Fig. 2 The reverse protection diode (1) 2 ) at the base of (Ql) can be omitted.

(へ)発明の効果 本発明によれば、切替え回路の電圧供給端子の電位か、
切替え回路のトランジスタかオンになった時、大きく降
下することを防ぐ事か出来、又、切替え回路及び電圧発
生回路の電源をオフにした時、前記コンデンサの放電を
一定時間阻止することかできる。又、本発明を上記実施
例の如(PAL信号とSECAM信号の双方を受信でき
るテレビジョン受像機のAGC回路の切替え回路に実施
すれば、前記トランジスタをオンにした時に受像管がま
つ白な状態になることを防げ、又、テレビジョン受像機
の電源をオフにして再びオンにした時に於いても受像管
がまつ白な状態になることを防ぐことが出来、有用であ
る。
(F) Effects of the Invention According to the present invention, the potential of the voltage supply terminal of the switching circuit is
When the transistor of the switching circuit is turned on, a large voltage drop can be prevented, and when the switching circuit and the voltage generating circuit are turned off, the discharge of the capacitor can be prevented for a certain period of time. Furthermore, if the present invention is implemented in the switching circuit of the AGC circuit of a television receiver as in the above embodiment (which can receive both PAL signals and SECAM signals), the picture tube will be in a bright white state when the transistor is turned on. It is also useful because it can prevent the picture tube from becoming blank even when the power of the television receiver is turned off and then turned on again.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の切替え回路を備えるAGC回路の一実施
例、第2図及び第3図は本発明の切替え回路を備えるA
GC回路の一実施例を示す。第4図は第1図を説明する
ための図面である。 (2)・・・切替え回路、(5)・・・電圧発生回路、
(C1) (Cs)(C5)・・・コンデンサ、(Dl
)・・・ダイオード、(R1)(R1) (1’−5)
・・・抵抗、(Ql )(Q2 )・・・トランジスタ
FIG. 1 shows an embodiment of an AGC circuit including a conventional switching circuit, and FIGS. 2 and 3 show an embodiment of an AGC circuit including a switching circuit according to the present invention.
An example of a GC circuit is shown. FIG. 4 is a drawing for explaining FIG. 1. (2)...Switching circuit, (5)...Voltage generation circuit,
(C1) (Cs) (C5)... Capacitor, (Dl
)...Diode, (R1) (R1) (1'-5)
...Resistor, (Ql) (Q2)...Transistor.

Claims (1)

【特許請求の範囲】 (1)電圧を生じる電圧発生回路をコンデンサとトラン
ジスタの第2、第3電極間の直列接続を通して基準電位
点に接続し、前記トランジスタの第一電極に切替え電圧
を与えて前記トランジスタをオンとオフの2つの状態の
一方を択一選択的に設定するよう1こした切替え回路に
於いて、前記コンデンサと基準電位点間に前記トランジ
スタに並列に接続され前記トランジスタかオフのとき前
記コンデンサを充電するか前記コンデンサを前記電圧発
生回路に実質的に影響を与えないようにするインピーダ
ンス手段と、電源をオフにして前記トランジスタ及び電
圧発生回路をオフにしたとき前記第1電極と第2電極間
のPN接合を通して順バイアスがかかるのを阻止する阻
止手段を設けたことを特徴とする切替え回路。 (2)  前記インピーダンス手段は抵抗とダイオード
とからなることを特徴とする特許請求の範囲第1項記載
の切替え回路。 (31U記阻止手段は切替え電圧供給点と前記第一電極
間に挿入された抵抗とコンデンサの並列接続よりなるこ
とを特徴とする特許請求の範囲第1項記載の切替え回路
。 (4)@記阻止手段は前記並列接続と前記第一電極間に
挿入され前記トランジスタにダーリントン接続された第
2トランジスタを含むことを特徴とする特許請求第3項
記載の切替え回路。 (5)前記電圧発生回路かAGC信号検出回路、及び平
滑回路、及びAGC信号増幅回路であることを特徴とす
る特許請求の範囲第1項記載の切替え回路。
[Claims] (1) A voltage generating circuit that generates a voltage is connected to a reference potential point through a series connection between a capacitor and the second and third electrodes of the transistor, and a switching voltage is applied to the first electrode of the transistor. In a switching circuit configured to selectively set the transistor to one of two states, ie, on and off, the switching circuit is connected in parallel to the transistor between the capacitor and a reference potential point, and is connected between the capacitor and a reference potential point to indicate whether the transistor is in the off state or not. an impedance means for charging the capacitor or causing the capacitor to have no substantial effect on the voltage generation circuit; A switching circuit comprising a blocking means for blocking forward bias from being applied through the PN junction between the second electrodes. (2) The switching circuit according to claim 1, wherein the impedance means comprises a resistor and a diode. (31U) The switching circuit according to claim 1, characterized in that the blocking means comprises a parallel connection of a resistor and a capacitor inserted between the switching voltage supply point and the first electrode. (4) @ The switching circuit according to claim 3, wherein the blocking means includes a second transistor inserted between the parallel connection and the first electrode and Darlington connected to the transistor. 2. The switching circuit according to claim 1, which is an AGC signal detection circuit, a smoothing circuit, and an AGC signal amplification circuit.
JP129183A 1983-01-07 1983-01-07 Switching circuit Pending JPS59126382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP129183A JPS59126382A (en) 1983-01-07 1983-01-07 Switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP129183A JPS59126382A (en) 1983-01-07 1983-01-07 Switching circuit

Publications (1)

Publication Number Publication Date
JPS59126382A true JPS59126382A (en) 1984-07-20

Family

ID=11497354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP129183A Pending JPS59126382A (en) 1983-01-07 1983-01-07 Switching circuit

Country Status (1)

Country Link
JP (1) JPS59126382A (en)

Similar Documents

Publication Publication Date Title
JP3563088B2 (en) Video signal processing device
JP2876093B2 (en) Grid bias control circuit for picture tube
JP2721880B2 (en) Video signal processing / display device
US4577234A (en) Driver amplifier for an image display device
KR100233945B1 (en) Video display apparatus with kinescope spot burn protection circuit
DK144550B (en) BLACK LEVEL FIXING CIRCUIT FOR A TELEVISION SIGNAL PROCESSING DEVICE
JPS59126382A (en) Switching circuit
JPS6112429B2 (en)
US3595993A (en) Noise-cancelling circuits
KR910006855B1 (en) Signal sampling circuit
KR910006459B1 (en) Signal sampling apparatus
KR100465919B1 (en) Display driver apparatus
JP2931701B2 (en) Clamp circuit
KR950013443B1 (en) Peak holding circuit for a color tv receiver
US6285143B1 (en) Video display protection circuit
JPH0537579Y2 (en)
JPH03231567A (en) Spot killer circuit
JPS5941666Y2 (en) blanking circuit
KR100244775B1 (en) A circuit for compensating rgb signals in case of abl in a monitor
JPH0419903Y2 (en)
KR810001367B1 (en) Automatic beam current limiter
KR0134616Y1 (en) Crt spot killer circuit
SU1755391A1 (en) Picture tube protection device
JPH0155635B2 (en)
JPS6113429B2 (en)