JPS59125648A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS59125648A JPS59125648A JP49983A JP49983A JPS59125648A JP S59125648 A JPS59125648 A JP S59125648A JP 49983 A JP49983 A JP 49983A JP 49983 A JP49983 A JP 49983A JP S59125648 A JPS59125648 A JP S59125648A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- gas atmosphere
- resistance value
- hydrogen atoms
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000012298 atmosphere Substances 0.000 claims abstract description 17
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims abstract description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 5
- 230000008018 melting Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims 1
- 239000002023 wood Substances 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 2
- 230000007423 decrease Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101100008048 Caenorhabditis elegans cut-4 gene Proteins 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は多結晶シリコンの抵抗を有する半導体集積回
路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit having a polycrystalline silicon resistor.
（従来技術）
薄膜多結晶シリコンはバイポーラおよびＭＯ８集槓回路
において抵抗として使用されている。その場合使用目的
に応じてその抵抗値の範囲を制御しなけれはならない。PRIOR ART Thin film polycrystalline silicon is used as resistors in bipolar and MO8 collector circuits. In that case, the range of the resistance value must be controlled depending on the purpose of use.
たとえば切４．交換回路のラダー抵抗のとき、シート抵
抗値で約ｘｏ３Ｑ７ｓ低消費電力パイボーラ回路の負荷
抵抗のとき、約１０４〜１０５≦侘、スタチックＲＡＭ
のメモリセルの負荷抵抗のとき約１０８〜１０耳化など
である。For example, cut 4. When using the ladder resistance of the exchange circuit, the sheet resistance value is approximately xo3Q7s When the load resistance of the low power consumption pibora circuit is approximately 104~105≦Wabi, static RAM
When the load resistance of a memory cell is approximately 108 to 10 times, etc.
しかしながら、多結晶シリコンの抵抗は色々な要因によ
シ変化し、精密な制御には注意が必要である。However, the resistance of polycrystalline silicon changes depending on various factors, and careful control is required for precise control.
たとえば、不純物導入量を一定としてもその多結晶シリ
コン膜厚、多結晶シリコン膜のＣＶＤ成長時の雰囲気、
成長温度、成長法などの成長条件および多結晶シリコン
膜成長後の熱処理条件などによって影響を受け、特に、
高抵抗、たとえば。For example, even if the amount of impurity introduced is constant, the thickness of the polycrystalline silicon film, the atmosphere during CVD growth of the polycrystalline silicon film,
It is affected by growth conditions such as growth temperature and growth method, and heat treatment conditions after polycrystalline silicon film growth.
High resistance, e.g.
シート抵抗で１０６〜１０１１（％ぐらいの抵抗値の再
現性のよい制御が難しい。It is difficult to control the resistance value with good reproducibility, which is about 106 to 1011% (sheet resistance).
また、多結晶シリコンの抵抗を低下させる方法は色々検
討されているが、一旦低下したものを再び上昇させる簡
単な方法は、なかった。Furthermore, although various methods have been studied to lower the resistance of polycrystalline silicon, there has been no easy method to raise it again once it has been lowered.
（発明の目的）
この発明は、この色々な要因によシ、変化しやすい多結
晶シリコン膜の抵抗値を最終工程後でもＴ１１〕小に？
ｌｉ！制御できる半導体集積回路の製造方法を提供する
ことを目的とする。(Purpose of the Invention) The present invention can reduce the resistance value of a polycrystalline silicon film, which is easy to change, to T11 even after the final process due to these various factors.
li! An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can be controlled.
（発明の構成）
この発明の半導体集積回路の製造方法は、半導体集積回
路における金属配線材料としてのＡｌの融点以下の比較
的低温のアニールを水素がス雰囲気中で行なうことによ
シ、多結晶シリコン中に水素原子を導入、あるいは窒素
ガス雰囲気中でアニールを行なうことにより、上記多結
晶中の水素原子を放出させるようにしたものである。(Structure of the Invention) A method for manufacturing a semiconductor integrated circuit according to the present invention is characterized in that polycrystalline The hydrogen atoms in the polycrystal are released by introducing hydrogen atoms into silicon or by performing annealing in a nitrogen gas atmosphere.
（実施例）
以下、この発明の半導体集積回路の製造方法の実施例に
ついて説明する。(Example) Hereinafter, an example of the method for manufacturing a semiconductor integrated circuit of the present invention will be described.
多結晶シリコン中に水素原子を導入し不対電子と結合さ
せることにより、多結晶粒界のエネルギ障壁が小さくな
り、実質的に山田キャリア濃度が」二昇するため多結晶
シリコンの抵抗値は低下し、逆に一旦尋人した水素原子
は外部からエネルギを与え、Ｗ（離させ放出させると抵
抗値は再び上昇し回復すること、およびこの水素原子の
導入、あるいは放出が一般的配線材別であるＡＡの融点
以下の比較的低温（たとえば５００℃）の各々水素ガス
Ｈ２雰囲気のアニールあるいはＩ’Ｊ２ ”Ｊ）囲気中
のアニールという簡単な方法で容易に実現できることが
わかった。By introducing hydrogen atoms into polycrystalline silicon and combining them with unpaired electrons, the energy barrier at polycrystalline grain boundaries becomes smaller, and the Yamada carrier concentration essentially increases by 2,000,000, which lowers the resistance value of polycrystalline silicon. However, once the hydrogen atoms have been exposed, they are given energy from the outside, and when they are released and released, the resistance value increases again and recovers. It has been found that this can be easily achieved by a simple method of annealing in a hydrogen gas H2 atmosphere or annealing in an ambient atmosphere at a relatively low temperature below the melting point of a certain AA (for example, 500 DEG C.).
これの概念図を第１図に示ゴ。ここで横軸は低温アニー
ル時間、縦軸は多結晶シリコンの抵抗仙点線から左側が
Ｈ７雰囲気、右側がＮ２雰囲気、ま／ここの曲線は、多
結晶シリコンへの不純物の導入量を変化させれば、自然
、抵抗値が変化するので上下へ移動する。A conceptual diagram of this is shown in Figure 1. Here, the horizontal axis is the low-temperature annealing time, and the vertical axis is the H7 atmosphere on the left and the N2 atmosphere on the right from the polycrystalline silicon resistance line. For example, the resistance value changes naturally, so it moves up and down.
半導体集積回路の多結晶シリコン抵抗は、その製造工程
において完成１でに実効的に）］２雰囲気のアニールに
和尚する工程を１ｍｋるＣとが多い。Polycrystalline silicon resistors for semiconductor integrated circuits often require a process of 1 mK for annealing in an atmosphere during the manufacturing process.
たとえば、絶縁膜としてＳ ｉ ｋ（、ガスと０２ガス
の反応によるＣＶＤ酸化膜を使用すると、その反応によ
り削生成物としてＨ２が発生し、Ｈ２アニールと類似の
効果を受ける。For example, if a CVD oxide film produced by a reaction between S i k and 02 gas is used as an insulating film, H2 is generated as a cutting product due to the reaction, resulting in an effect similar to that of H2 annealing.
したがって、集積回路完）戊後の多結晶シリコン抵抗は
それ自身に着目すれば、若干のＨ２雰囲気のアニールを
受けた第２図のＡ点のような状態にあることが多い。Therefore, if we pay attention to the polycrystalline silicon resistor itself after the completion of the integrated circuit, it is often in a state like point A in FIG. 2, which has undergone some annealing in an H2 atmosphere.
この第２図において、縦軸は第１図と同じであり、横軸
は実効的なアニール時間である。In FIG. 2, the vertical axis is the same as in FIG. 1, and the horizontal axis is the effective annealing time.
一方、多結晶シリコン抵抗は不純物の導入量を制御し′
て、その抵抗値を制御するのが基本であるが、これはた
とえ同一の不純物導入量であっても、前記したような他
の色々な条件によ）変化し、集積回路完成時にある目的
とする一定の抵抗範囲内に制御するのは、それがたとえ
ば１０６〜１０１１％のような高抵抗であるほど難しい
。On the other hand, polycrystalline silicon resistors control the amount of impurities introduced.
The basic idea is to control the resistance value, but even if the amount of impurities introduced is the same, this value may change depending on various other conditions as mentioned above, and it may be necessary to control the resistance value when the integrated circuit is completed. The higher the resistance, for example 106-1011%, the more difficult it is to control it within a certain resistance range.
この状況の概念図を第３図に示す。この第３図において
、横軸は多結晶シリコン抵抗に対する実効的なアニール
時間、縦軸は多結晶シリコンの抵抗値であり、３本の曲
線は同一不純物量であっても、他の条件によシ変動し、
半導体集積回路完成時にａ、ｂ、ｃの抵抗値をとること
を示している。A conceptual diagram of this situation is shown in Figure 3. In this Figure 3, the horizontal axis is the effective annealing time for polycrystalline silicon resistance, the vertical axis is the resistance value of polycrystalline silicon, and the three curves show that even if the amount of impurity is the same, it depends on other conditions. shi fluctuates,
It shows that the resistance values of a, b, and c will be taken when the semiconductor integrated circuit is completed.
この場合、点線の範囲内が目標とする所望の抵抗値の範
囲とすると、抵抗値ａは高すぎ、抵抗値Ｃは低すぎるこ
とになる。このときたとえ抵抗値Ｃのように低すぎても
上記方法にょシ簡単に抵抗値ａ、ｃとも所定の範囲内に
制御することができる。In this case, if the desired target resistance range is within the range of the dotted line, the resistance value a will be too high and the resistance value C will be too low. At this time, even if the resistance value C is too low, both the resistance values a and c can be easily controlled within a predetermined range using the above method.
したがってこの発明の半導体集積回路の製造方法は多結
晶シリコンの抵抗値を製造工程の最終段階である金属配
線形成後でも多結晶シリコンへ尋人された不純物量で基
本的に決まるある範ν１］内で容易に上下させ制御する
ことができるので、多結晶シリコン抵抗を有するすべて
の半導体集積回路に利用することができる。Therefore, the method for manufacturing a semiconductor integrated circuit of the present invention allows the resistance value of polycrystalline silicon to be kept within a certain range ν1, which is basically determined by the amount of impurities added to the polycrystalline silicon, even after metal wiring is formed at the final stage of the manufacturing process. Since it can be easily controlled by raising and lowering the resistor, it can be used in all semiconductor integrated circuits having polycrystalline silicon resistors.
（発明の効果）
以上のようにこの発明の半導体集積回路の製造方法によ
れば、半導体集積回路における金属配線材料としてのＡ
ｌ融点以下の比較的低温のアニールを水素ガス雰囲気中
で行なうことにょ多条結晶シリコン中に水素原子を導入
あるいは窒素ガス雰囲気中゛でアニールを行なうことに
ょυ多結晶中の水素原子を放出させるようにしたので、
多ＸＴＪ晶シリコンの抵抗値を容易に、最終工程後でも
簡単に割御できるものである。(Effects of the Invention) As described above, according to the method for manufacturing a semiconductor integrated circuit of the present invention, A can be used as a metal wiring material in a semiconductor integrated circuit.
By performing annealing at a relatively low temperature below the melting point in a hydrogen gas atmosphere, hydrogen atoms are introduced into polycrystalline silicon, or by performing annealing in a nitrogen gas atmosphere, hydrogen atoms in polycrystals are released. I did it like this,
The resistance value of multi-XTJ crystal silicon can be easily controlled even after the final process.
第１図はこの発明の半導体集積回路の製造方誌の一実施
例を説明するための水素ガス雰囲気中および窒素ガス雰
囲気中における多結晶シリコンに対する低温アニール時
間対多結晶シリコン抵抗値の関係を示す図、第２図およ
び第３図は、それぞれ同上、半導体集積回路の製造方法
における多結晶シリコンに対する実効的アニール時間対
多結晶シリコン抵抗値の関係を示す図である。
特許出願人 沖電気工業株式会社
第 １ 図
五
珍ｆ、吉晶シリコン１（クトするイＣ晶アニールａ今Ｉ
Ｖｉ第２図
第３ 図FIG. 1 shows the relationship between low-temperature annealing time and polycrystalline silicon resistance value for polycrystalline silicon in a hydrogen gas atmosphere and a nitrogen gas atmosphere to explain an embodiment of the manufacturing method of a semiconductor integrated circuit according to the present invention. 2 and 3 are diagrams showing the relationship between the effective annealing time for polycrystalline silicon and the resistance value of polycrystalline silicon, respectively, in the method for manufacturing a semiconductor integrated circuit. Patent applicant Oki Electric Industry Co., Ltd. Figure 1
ViFigure 2Figure 3
Claims (1)
材料としてのＡ／の融点以下の比較的低温のアニールを
水素ガス雰囲気中で行なうことによシ、多結晶シリコン
中に水素原子を導入したり、あるいは定木ガス雰囲気中
でアニールを行なうことによシ多結晶シリコンから水素
原子を放出させることを特徴とする半導体集積回路の製
造方法。Hydrogen atoms can be introduced into polycrystalline silicon by performing annealing in a hydrogen gas atmosphere at a relatively low temperature below the melting point of A/, which is a metal wiring material commonly used in semiconductor integrated circuits, or A method for manufacturing a semiconductor integrated circuit, characterized in that hydrogen atoms are released from polycrystalline silicon by performing annealing in a solid wood gas atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49983A JPS59125648A (en) | 1983-01-07 | 1983-01-07 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49983A JPS59125648A (en) | 1983-01-07 | 1983-01-07 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59125648A true JPS59125648A (en) | 1984-07-20 |
Family
ID=11475446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49983A Pending JPS59125648A (en) | 1983-01-07 | 1983-01-07 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59125648A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01231362A (en) * | 1988-03-11 | 1989-09-14 | Sony Corp | Manufacture of polycrystal silicon resistance |
| EP0801427A2 (en) * | 1996-04-11 | 1997-10-15 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor, semiconductor storage device, method of manufacturing the same and method of driving semiconductor storage device |
-
1983
- 1983-01-07 JP JP49983A patent/JPS59125648A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01231362A (en) * | 1988-03-11 | 1989-09-14 | Sony Corp | Manufacture of polycrystal silicon resistance |
| EP0801427A2 (en) * | 1996-04-11 | 1997-10-15 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor, semiconductor storage device, method of manufacturing the same and method of driving semiconductor storage device |
| EP0801427A3 (en) * | 1996-04-11 | 1999-05-06 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor, semiconductor storage device, method of manufacturing the same and method of driving semiconductor storage device |
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