JPS59124731A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59124731A JPS59124731A JP23377082A JP23377082A JPS59124731A JP S59124731 A JPS59124731 A JP S59124731A JP 23377082 A JP23377082 A JP 23377082A JP 23377082 A JP23377082 A JP 23377082A JP S59124731 A JPS59124731 A JP S59124731A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- pattern
- nichrome
- annealing
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 53
- 229910001120 nichrome Inorganic materials 0.000 abstract description 24
- 238000000137 annealing Methods 0.000 abstract description 21
- 230000005611 electricity Effects 0.000 abstract 2
- 238000005259 measurement Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 18
- 239000010410 layer Substances 0.000 description 5
- 229910052736 halogen Inorganic materials 0.000 description 4
- 150000002367 halogens Chemical class 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- SEPPVOUBHWNCAW-FNORWQNLSA-N (E)-4-oxonon-2-enal Chemical compound CCCCCC(=O)\C=C\C=O SEPPVOUBHWNCAW-FNORWQNLSA-N 0.000 description 1
- LLBZPESJRQGYMB-UHFFFAOYSA-N 4-one Natural products O1C(C(=O)CC)CC(C)C11C2(C)CCC(C3(C)C(C(C)(CO)C(OC4C(C(O)C(O)C(COC5C(C(O)C(O)CO5)OC5C(C(OC6C(C(O)C(O)C(CO)O6)O)C(O)C(CO)O5)OC5C(C(O)C(O)C(C)O5)O)O4)O)CC3)CC3)=C3C2(C)CC1 LLBZPESJRQGYMB-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Surface Heating Bodies (AREA)
Abstract
Description
【発明の詳細な説明】
＋１１発明の技術分野
本発明は半導体装置の製造方法、詳しくはうエバのアニ
ール方法に関する。DETAILED DESCRIPTION OF THE INVENTION +11 Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for annealing a flying evaporator.
（２）技術の背景
半導体素子製作のためにはウェハに各押の工程が加えら
れる。その１つに、ウェハに素子が形成された後にウェ
ハ全面上に例えば燐・シリケート５・ガラス（ＰＳＧ
）膜を化学気相成長法（ＣＶｒｌ法）で成長して、眉間
絶縁膜を作り、このＰＳＧ膜にスルーホール（コンタク
トホール）を開孔し、例えばアルミニウム（１／）層を
形成してこのスルー（１）
ホールを埋めて層間接続をとることが行われる。(2) Background of the technology In order to manufacture semiconductor devices, a wafer is subjected to various pressing steps. For example, phosphorus-silicate-5 glass (PSG) is applied over the entire surface of the wafer after devices are formed on the wafer.
) film by chemical vapor deposition method (CVrl method) to create a glabella insulating film, then open a through hole (contact hole) in this PSG film, form an aluminum (1/) layer for example, and then Through (1) Holes are filled to establish interlayer connections.
かかるスルーホールは一般にドライエツチングで形成さ
れ、段差が急峻であるためそこに６１１層を形成すると
、段差のところでｉ層が断線するおそれがある。かかる
Ａｊ２１ｉＪの切断を克服する目的でウェハを１１００
℃程度の高温で熱処理し、ＰＳＧ膜を溶融（フロー、ｆ
ｌｏｗ）Ｌ、ＰＳＧ膜の段差をなだらかにし、その上に
へｌ配線層を設けることが行われる。上記はウェハに加
えられるアニール（熱処理）の１例であるが、素子製作
工程においてはウェハに上記以外の目的でアニールがな
されることもある。Such a through hole is generally formed by dry etching, and since the step is steep, if the 611 layer is formed there, there is a risk that the i layer will be disconnected at the step. In order to overcome such Aj21iJ cutting, the wafer was
The PSG film is melted (flow, f
(low) L, the steps of the PSG film are made smooth and a low wiring layer is provided thereon. Although the above is an example of annealing (heat treatment) applied to a wafer, wafers may also be annealed for purposes other than the above in the device manufacturing process.
（３）従来技術と問題点
従来ウェハのアニールにおいては、複数枚のウェハを１
バツチとし、それらを炉に入れてアニールするパンチ処
理が行われた。しかし、最近ウェハは例えば直径が１２
．７ｃｍ （５インチ）というように大口径化し、炉を
用いるバッチ処理に代えて１枚取り処理が行われるよう
になってきた。そのときに、従来の炉を用いるアニール
の場合の如く、（２）
ゆっくり時間をかけてアニールし、次に同様に時間をか
げて冷却するのであれば問題はないが、作業性向上のた
めウェハ処理工程（ウェハプロセス）の高速化が要求さ
れ、また、大口径化するうエバは従来の炉で処押しゲ狂
い事情がある。(3) Conventional technology and problems In conventional wafer annealing, multiple wafers are
A punching process was performed in which they were grouped together and placed in a furnace for annealing. However, recently, wafers have a diameter of, for example, 12
．． The diameter has become larger, such as 7 cm (5 inches), and single-sheet processing has begun to be performed instead of batch processing using a furnace. At that time, as in the case of annealing using a conventional furnace, there is no problem if (2) the wafer is annealed slowly over a long period of time and then cooled over a similar period of time, but in order to improve workability, the wafer The processing process (wafer process) is required to be faster, and evaporators with larger diameters are being processed at a disadvantage in conventional furnaces.
更には半導体集積回路の高隼積化のため不純物拡散領域
等は浅く形成されるようになり、ウェハのアニールにお
ける不純物の再分布を防１１−する目的で、レーザを用
いきわめて短い時間内（殆ど瞬間的）にアニールするこ
とが行われるようになった。Furthermore, impurity diffusion regions, etc., are being formed shallowly due to the high integration density of semiconductor integrated circuits, and in order to prevent impurity redistribution during wafer annealing, lasers are used to form Annealing (instantaneous) is now performed.
しかし、レーザアニールにおいては、ウェハ表面がｔＲ
傷される（１’ｒｌれる）問題がある。そこで、例えば
ハロゲンランプを用い光エネルギーによりアニールする
ようになっζきたが、光エネルギーによるアニールにお
いては、アニールするに足る光強度をウェハ全面にわた
って得るについて問題がある。その問題を解決すべく複
数のハロゲンランプを用いることも試みられるが、その
ときウェハ全面が均一に加タハされるようにするためハ
ロゲ（３）
ンランプの配置にり１１シい問題がある。However, in laser annealing, the wafer surface is
There is a problem of being damaged (1'rl). Therefore, for example, annealing using light energy using a halogen lamp has come to be performed, but in annealing using light energy, there is a problem in obtaining light intensity sufficient for annealing over the entire wafer surface. Attempts have been made to use a plurality of halogen lamps to solve this problem, but there is a problem in arranging the halogen lamps in order to uniformly coat the entire surface of the wafer.
ウェハは単結晶体であってそれに素子が形成されるので
あるが、光エネルギーがウェハ全面に均一に加えられな
いと、熱ストレスによって反ることがあり、またはスリ
ップラインが発生する等の問題がある。そうなると、反
った部分でウェハの単結晶性が乱され、そこに素子が形
成されると、リーク電流や接合（ジャンクション）リー
クの発生があり、形成される素子の特性に悪影口を及ぼ
す。以上を要約すると、大口径化するウェハを、短時間
内に均一の温度で熱処理することが要求されているもの
の、ウェハプロセスの高速化、浅い拡散層が形成された
素子における不純物再分布の防止等の諸問題を解決する
ウェハのアニール方法は未だ確立されていない。Wafers are single crystals on which devices are formed, but if light energy is not applied uniformly over the entire surface of the wafer, problems such as warping or slip lines may occur due to thermal stress. be. In this case, the single crystallinity of the wafer is disturbed at the warped portion, and when devices are formed there, leakage current and junction leakage occur, which adversely affects the characteristics of the formed devices. To summarize the above, although it is required to heat-treat wafers with increasingly large diameters at a uniform temperature within a short time, it is necessary to speed up wafer processing and prevent impurity redistribution in devices with shallow diffusion layers. A wafer annealing method that solves these problems has not yet been established.
（４）発明の目的
本発明は上記従来の問題に鑑み、ウェハを短時間内に均
一の温度でアニールする方法を提供することを目的とす
る。(4) Purpose of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a method for annealing a wafer at a uniform temperature within a short time.
（５）発明の構成
（４）
そしてこの目的は本発明によれば、熱処理されるべきウ
ェハの背面のほぼ全体にわたり高融点金属でパターンを
形成し、前記パターンに１ｆｆｉ電してウェハ全体を均
一に加熱することを特徴とする半導体装置の！！Ｉ＋！
造方法を捉方法ることによって達成されろ。(5) Structure of the Invention (4) According to the present invention, this object is to form a pattern with a high melting point metal over almost the entire back surface of a wafer to be heat treated, and apply 1ffi electric current to the pattern to uniformly coat the entire wafer. A semiconductor device characterized by being heated to! ! I+!
This can be achieved by understanding how to create and how to capture.
（６）発明の実施例 ツ下本発明実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail with reference to the drawings.
図には本発明の方法によって作られたウェハ１の背面が
平面図で示され、同図において２はニクロムのパターン
である。図示のニクロムパターン２は、ニクロムをウェ
ハｌの背面」二に全面付着し、パターンが微細なもので
あればエツチングによって図示のパターンに形成し、パ
ターンが微細なものでないと１きは図示のパターンのメ
タルマスクを用いて直接形成する。いずれの方法を用い
ても、パターンがウェハの背面のほぼ全面にわたるよう
配置する。The figure shows a plan view of the back side of a wafer 1 produced by the method of the invention, in which numeral 2 is a nichrome pattern. The illustrated nichrome pattern 2 is obtained by depositing nichrome on the entire back surface of the wafer 1, and if the pattern is fine, it is formed into the illustrated pattern by etching.If the pattern is not fine, it is formed into the illustrated pattern. directly formed using a metal mask. Whichever method is used, the pattern is arranged so as to cover almost the entire back surface of the wafer.
ウェハ１のアニールにおいては、電極３と４とを電源線
にそれぞれ接続し、両電極間に通電す（５）
ルト、ニクロムパターン２はニクロムの抵抗によって加
熱され、その結果ウェハ１は均一の温度に加ｐ４＞され
アニールされる。ニクロムパターン２と電源の電力とを
適宜選定することにより、ニクロムパターン２を１２０
０℃程度に加熱すると、ウェハ１は短時間内に全面が均
一に１１００℃程度に熱せられ、所望のアニールがなさ
れうる。ニクロムパターン２が所定の温度に達するまで
の時間は、ニクロムパターンの抵抗値、ウェハ１の寸法
等に対応し、前以って実験によって一定値になるよう設
定しておく。In annealing the wafer 1, electrodes 3 and 4 are connected to the power supply line, and current is passed between the two electrodes (5).The nichrome pattern 2 is heated by the nichrome resistance, and as a result, the wafer 1 is heated to a uniform temperature. p4> and annealed. By appropriately selecting the nichrome pattern 2 and the power of the power supply, the nichrome pattern 2 can be
When the wafer 1 is heated to about 0° C., the entire surface of the wafer 1 is uniformly heated to about 1100° C. within a short period of time, and desired annealing can be performed. The time required for the nichrome pattern 2 to reach a predetermined temperature corresponds to the resistance value of the nichrome pattern, the dimensions of the wafer 1, etc., and is set in advance to a constant value through experiments.
ニクロムパターン２は図示の形状に代えて、ウェハ１の
裏面の全面上に平板状に形成してもよく、そのときは、
ニクロムパターンの全体の温度が均一に上昇しうるよう
、電極３，４の位置を前以って選定しておく。なお、ニ
クロムパターンの形状は上記に説明したものに限定され
るものでなく、ウェハの背面全体にわたり、ウェハの温
度を均一に上昇せしめるものであればその他のパターン
でもよい。The nichrome pattern 2 may be formed in a flat plate shape on the entire back surface of the wafer 1 instead of the shape shown in the figure.
The positions of the electrodes 3 and 4 are selected in advance so that the temperature of the entire nichrome pattern can be raised uniformly. Note that the shape of the nichrome pattern is not limited to that described above, and may be any other pattern as long as it uniformly increases the temperature of the wafer over the entire back surface of the wafer.
（６）
ニクロムパターン２は蒸着またはスパッターによってニ
クロムをウェハの背面に付着し、しかる後に前記した如
くにパターンを形成する。なお、ウェハ加熱用の材料は
−１−記したニクロムに限定されるものでなく、その他
の高融点金属も用いうる。(6) Nichrome pattern 2 is formed by depositing nichrome on the back side of the wafer by vapor deposition or sputtering, and then forming the pattern as described above. Note that the material for heating the wafer is not limited to the nichrome described in -1-, and other high melting point metals may also be used.
ウェハプロセスにおいてウェハに前ツって金属が付着さ
れるとプロセスが金属を嫌うこともある点に着目して、
図示のニクロムパターン２はウェハのアニールがなされ
る直前に形成する。もっとも、ウェハのアニールはウェ
ハプロセスの後２１′の段階でなされることが多い。ま
た、所定のアニールがすべて終了したときには、エソヂ
ングまたは研磨によってニクロムパターンを除去する。Focusing on the fact that in the wafer process, if metal is attached to the wafer beforehand, the process may dislike the metal.
The illustrated nichrome pattern 2 is formed just before the wafer is annealed. However, wafer annealing is often performed at step 21' after wafer processing. Further, when all predetermined annealing is completed, the nichrome pattern is removed by etching or polishing.
いずれの方法を用いても、ニクロムパターンの４ＣＩ’
１は回収と再使用が可能である。No matter which method is used, the 4CI' of the nichrome pattern
1 can be collected and reused.
（７）発明の効果
以上詳細に説明した如く、本発明の方法によるときは、
短時間内に均一の温度でウェハのアニールをなすことが
可能となり、ウェハが大口径のものであっても反りが発
４Ｌすることがなく、製作（７）
される半導体素子の特性が損なわれることが防止され、
ウェハプロセスの高速化が実現される。また、本発明の
方法によって作られたウエノへのアニールにおいては、
１！＋、に電流を通電するだけであるので、レーザビー
ム発生装置を用い、または複数のハロゲンランプを配置
する場合に比べ、容易にかつコスト安にアニールがなさ
れうる利点がある。(7) Effects of the invention As explained in detail above, when using the method of the present invention,
It becomes possible to anneal the wafer at a uniform temperature within a short time, and even if the wafer has a large diameter, there will be no warping, which would impair the characteristics of the semiconductor devices being manufactured (7). It is prevented that
Wafer process speed is realized. In addition, in annealing Ueno made by the method of the present invention,
1! Since it is only necessary to supply current to + and +, there is an advantage that annealing can be performed more easily and at a lower cost than in the case of using a laser beam generator or arranging a plurality of halogen lamps.
添付した図は本発明の方法によって作られたウェハの背
面を示す平面図である。
１−ウェハ、２−ニクロムパターン、
３．４−−一電極
（８）The attached figure is a plan view showing the back side of a wafer made by the method of the invention. 1-wafer, 2-nichrome pattern, 3.4--one electrode (8)
Claims (1)
点金属でパターンを形成し、前記パターンに通電してウ
ェハ全体を均一に加熱することを特徴とする半導体装置
の！！！造方法。A semiconductor device characterized in that a pattern is formed using a high melting point metal over almost the entire back surface of a wafer to be heat treated, and the pattern is energized to uniformly heat the entire wafer! ! ! Construction method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23377082A JPS59124731A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23377082A JPS59124731A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59124731A true JPS59124731A (en) | 1984-07-18 |
Family
ID=16960298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23377082A Pending JPS59124731A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59124731A (en) |
-
1982
- 1982-12-29 JP JP23377082A patent/JPS59124731A/en active Pending
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