JPS59124667A - Controller for group of elevator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to group management control of elevators in which a plurality of elevators are put into service for a plurality of floors, and these plurality of elevators are centrally controlled and operated efficiently. In particular, the present invention relates to a highly reliable elevator group management/control device that can prevent a significant functional deterioration of the group management control due to breakdowns or the like.

[Technical background of the invention]

Elevator group management control is performed to efficiently operate multiple elevators installed in parallel9, and the status of hall calls is continuously scanned and monitored to ensure that hall calls occur If there is a call, the most suitable elevator to respond to the hall call is selected from among the plurality of ELMS and BETAs to serve the hall call.

In such an elevator group management control system, the control of registering and deleting hall calls has conventionally been configured by a relay sequence or a Dounia logic such as a frig 70 tube. In the system configuration shown in Figure 1, the hall caller installed in the hall detects the input front line (rising bt or falling si, ji) of the button (push? button switch), and receives the input using a flip-flop, etc. The hall call is latched, and a response signal from each machine clears the latch and erases the hall call.

FIG. 1 shows an example of the system configuration of Mukuro's group management control device.

The example shown in FIG. 1 is an example of a conventional system in which hall call registration and deletion are performed using hardware logic. The button HB input is latched by a 7-lip frog, etc., and the hall call registration rung HL is lit, and the main controllers (A) to (6) 6A, which correspond to each machine of A to H,
Hall call response signal from 6H), 'latte' is canceled and the registration lamp HL is turned off. P
IA (peripheral interface adapter) 2, R
OM (read only memory) 3, RAM (random access memory) 4. A computer comprising a CPU (central processing unit) 5, a failure detection logic 7, etc. determines the optimum machine among each machine number A to H based on the hall call information from the hall call registration deletion logic circuit 1. Controls allocation. IO is an input/output bus.

Recently, in systems using small computers such as microcomputers, functions similar to those described above are controlled by shiftware based on hall call input from the hall call button and response signals from each car, and group management control. It constitutes one functional module in the computer.

In conventional systems such as these, when using hardware logic, the hardware must be changed each time due to building configurations, differences in specifications depending on customer needs, etc. If a failure occurs in the hardware, even if the group management control function is normal, the group management control will be lost and all units will have to be stopped on each floor or skip operation will be required, resulting in a major system down. Put it away.

In addition, even in systems that use computers, if the computer malfunctions, boarding call registration becomes impossible, and as in the case of the above-mentioned no-dounia logic, if only one malfunction occurs, the reliability will drop significantly, resulting in a large The system will go down.

Furthermore, as a computer-based system, two computers with the same functions are installed, and a fully duplex system consisting of an operating system and a standby (backup) system is used to prevent functional degradation in the event of a failure. There is a system that prevents this problem, but even in such a system, the registration and deletion of hall calls and the allocation of the optimal car for each hall call based on the information of each car are controlled by one computer. Number of hall calls,
Increasing the number of group control bases or performing more detailed processing for determining the optimum number of machines increases the load on the computer, resulting in an increase in cycle time, especially in systems with warning light displays. This is not desirable.Also, considering that even when one computer has a load, the standby computer is not operating, the system configuration is very inefficient.

[Purpose of the invention]

The present invention is a highly reliable elevator group management control system that realizes an efficient dual system configuration using two computers and that does not cause a significant functional decline in group management control even if one of the computers breaks down. Our goal is to provide the following.

[Summary of the invention]

The present invention divides the function of group management control of the elevator between two computers, and in the event that one of the two computers fails, the other computer, that is, the remaining computer, can take over the function of the failed computer. It is a feature.

[Embodiments of the invention]

FIG. 2 shows the configuration of an embodiment of the group management control function device according to the present invention.

In FIG. 2, 11.15 is the 1st. second calculator c
pty (central processing unit), 1st. .

The second computer is equipped with a read-only ROM 9.13, which is made up of each CPU 11, 15, RAM 10, 14, which is a rewritable memory section corresponding to each CPU, a program implementation section, and a data section. It is configured. The PIA8°12 are programmable general purpose Ilo (input/output) interface elements, and these PIA8°12 are the first . C of each second computer
PU11.

The input/output buses IO1 to 04 are managed by
is under control. Reference numeral 16 denotes a failure detection logic circuit, which is connected to the above-mentioned No. 1. Second calculator (units [8-11], [
12 to 15] for monitoring the operating status of
Detects watchdog operation, power supply status, etc., and detects normal and abnormal states of the two-hand counter. 17 is an input/output bus rQl-
It is an input/output bus automatic switching device that consists of a changeover switch of IO4 and operates based on the detection output of the above-mentioned failure detection opening knock circuit 16. The input/output bus IO3* is connected to the hall call registration device 19 consisting of Nzo HL.
IO4 is connected to the main control devices 188 to 18H of each machine A to H. When both the first and second computers are normal, the input/output bus automatic device 17 uses the input/output bus IO! for hall call control. r IO2, main controller 181', ~1
The input/output bus IO3 of the BH hall call response signal S is PI
A 8 is connected to the CPU 11, and the first
is under the control of a computer. Also, at this time, the input/output bus I04 for communication with the main controllers 18A to 18H is connected to the CPU 15 via the PIA 12.
It is placed under the control of the second computer. If the first computer is normal and the second computer is in a troubled state,
Main controller 718A-18. The input/output bus I04 for communication with H is completely switched, switched to be under the control of the first computer (CPU 11 ) via the PIA 48, and disconnected from the second computer CPU 25 which is in a failure state. Also the second
When the first computer is normal and the first computer is in a faulty state, conversely, all input/output buses 10° to IO4 are connected to the second computer (CPU 15) and the first computer is in a faulty state.
computer (CPU 11).

Next, the operation of such a configuration will be explained with reference to the flowcharts shown in FIGS. 3 to 6. FIGS. 3 and 4 show the overall operation by the CPU 11 and CPU 15 of the first and second computers, respectively. 5 and 6 show partial details of the processing in FIGS. 3 and 4, respectively - hall call (registration, deletion) control and hall call allocation control; FIG. This is a flowchart.

In the system shown in Figure 2, CPUI 1, CPU
I and 5 respectively. When both second computers are normal, is the hall call of the hall call registration circuit 19?
The tongue HB input, hall call ramp 'HL output, and hall call response signal S from the main controller J8A-18H are connected to PIA& by an input/output automatic switching device 17 and are under the control of CPU J1. ◎ First, the processing of the system centered on the first computer, that is, the CPU 11 will be explained.

In FIG. 3, when the program starts and the presetting of the memory, timer, etc. is completed by the initialization routine P1-1, the hall call control routine P3 is executed via the repeat start point P1-2.

As shown in detail in FIG. 5, this routine P3 inputs the state of the hall call registration button HB of the hall call registration device 19 (p, y-1) Ig, when the hall call button is pressed. When (PJ-,?)
Depending on whether the corresponding hall call registration lamp HL lighting output has been output (p3-3), if it has not been output, the registration lamp HL is turned on and the registration of the hall call is memorized (
PJ-4). Then, inputs the hall call response signal S from the main controllers 18A to 18H (PJ-5), and checks whether the registered hall call has been answered or not (PJ-5).
Based on the information in J-6), if the hall call has already been answered, an output is generated that erases the registration lamp HL and erases the hall call registration. show. When this routine is completed in all halls, the hall call control routine P3 is completed.

Next (returning to FIG. 3), the failure detection logic circuit 16 detects whether the second computer centered on the CPU 15 is normal (pl-3) t, and if it is normal, the repeat start point (pl- Return to 2). In the unlikely event that the second computer (CPU 15) becomes in a failure state, the failure detection logic circuit 16 operates to cause the input/output bus automatic switching device 1 to
7, the input/output bus IO4 for communication signals from the main controllers 18A to 18H is connected from the PLA 12 to the PIA 8.
The CPU 11 has each main controller 181 to
1BH information is input, and if there is a hall call based on that information, the optimum car number is determined and output to the main controller, and hall call allocation is performed in control P4.

Next, the processing of the system centered on the second computer, that is, the CPU 15 will be explained.

In Fig. 4, Grodarum starts at the start point, and when the initialization routine (P2-1) is completed, the repeat start point (p
In the fault detection logic circuit 16, C
Detection (pz-, y) is performed to determine whether the first computer centered around pUll is normal. If normal, hall call allocation executes control routine P4.

As shown in detail in FIG. 6, this routine P4 connects the input/output bus IO4 for communication between the main controllers 188 to 1BH.
When a hall call (Pl-2) is generated based on the information of each car (Pl-1) L and A-H via IA 12, (
pl-3), determine whether the allocation has been completed (pl-4),
If the status is unassigned, perform evaluation conversion calculation (Pl-5) based on the information of each A-H machine mentioned above and determine the responding machine (
pl-6) and gives the assigned output to the assigned machine via the PIA 12 (Pl-7). When all the holes are completed, this routine is completed and the process returns to FIG. 4.) Return to the repeat start point (pz-z.).

Here, when the first computer centered on the CPU 11 is in a failure state and is detected by the failure detection door knocking circuit 16, the input/output bus IO1r IO for hall call control is activated.
2 and the input/output bus 03 of the hall call response signal S from the main control unit WtxsA to 18H are connected to the pLA 12 side in the input/output bus automatic switching device 17, so that the hall call control P3 is performed by the CPU 15. become.

Furthermore, in this case, the hall call control system and the hall call assignment are controlled by the first control system of the control system. Second computer (CPU 11.

If both CPUs 15) go down, this is detected by the failure detection logic circuit 16,
The information is input to the main controllers 18A to 1BH, and backup operations such as stopping at each floor and skip operation are performed on service floors, thereby maintaining the minimum level of functionality.

Note that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various modifications without changing the gist thereof.

For example, the first. As buffer lag processing when an abnormality is detected in both the second computers, processing other than stopping each floor or skipping operation described above may be performed, and if this backup is not taken into consideration, the first. As a means for detecting an abnormality in the second computer, the failure detection logic circuit 16 using hardware logic is replaced by the first computer. Software-based detection means may be used, such as inserting a routine for detecting an abnormality in the other computer into the processing routines of both second computers.

[Effects of the Invention] According to the present invention, in an elevator group management control device that operates a plurality of elevators for a plurality of floors, functions are divided such that hall call control and hall call assignment are controlled. By adopting a dual-system configuration of computers, each function can perform more detailed and precise processing by dividing the load among the computers.
It becomes possible to reduce the load by shortening the cycle time, greatly improving the efficiency of the computer drive system, and making it easier to respond flexibly to building configurations and customer needs. Furthermore, even if one of the computers fails, the other computer backs up the functions of both computers, making it possible to prevent a significant decline in functionality in terms of group management control.
Reliability is significantly improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the system configuration of an example of a conventional elevator group management control device, Fig. 2 is a block diagram showing the system configuration of an embodiment of the present invention, and Figs. 3 to 6 are the same. 3 and 4 are general flowcharts showing the overall operation of the first and second computers, respectively, and FIGS. 5 and 6 are flowcharts showing the operation of the system according to the embodiment. Hall call control routine and hall call allocation are flowcharts showing details of the control routine. 8.12... Veri 7 error interface adapter, 9.13... ROM, 10, 14... RA
M. 11.15...CPU, 18A~18H...A
~H Main control device of each unit, 16... Failure detection port knocking circuit, 17... Input/output bus automatic switching device, 19...
Landing - call registration device. Applicant's representative Patent attorney Takehiko Suzue Figure 4 Figure 5

Claims (1)

[Claims] A plurality of elevators are put into service for a plurality of floors,
In an elevator group management control system that selects and determines the optimal machine for common hall calls and allocates hall calls, the first system monitors the status of the hall for each floor and controls the registration and deletion of hall calls. Abnormalities in the computer, the second computer that monitors the status of each car and the condition of the hosel call, and selects and assigns the most suitable car from among multiple elevators to respond to the hall call, and these first and second computers. and an abnormality detection means for detecting an abnormality, and when an abnormality in either one of the first and second computers is detected by the abnormality detection means, the other computer is caused to perform the functions of both computers. An elevator group management control device characterized by: