JPS59122218A - Hysteresis circuit - Google Patents

Abstract

PURPOSE:To obtain stable and highly accurate hysteresis characteristics by using voltage dividing constitution and a normally on type FET, feeding back an output from a comparator comparing input voltage with reference voltage and changing resistance between the source and drain of the FET. CONSTITUTION:When both input voltage VIN and output voltage VOUT are on low levels, the reference voltage VREF is determined as voltage VREF1 by composition of resistance at ON of normally ON depression type IGFETs Q11, Q12 and low-biased IGFET Q13. When the comparator 1 detects VIN>VREF1, the output of the comparator 1 is turned from low to high level and the voltage VREF is made close to earth voltage. Consequently, the output voltage is stably kept at the high level. At that time, the voltage VREF becomes voltage VREF2 determined by the composition of resistance generated when the IGFETs Q11, Q12 and the high-biased IGFET Q13 are on, and I/O characteristics having hysteresis is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit having hysteresis characteristics, and more particularly to a circuit having stable hysteresis in input/output characteristics.

'In electronic circuits, circuits with hysteresis in input/output characteristics, such as Schmidt-Riggut, are widely used. In a circuit that changes the output state in response to changes in input voltage, by setting a trip point voltage at which the output state transitions depending on the output state, advantages such as widening the noise dead zone can be obtained. can.

The advantage of a hysteresis circuit is realized when the hysteresis characteristic changes between components or due to conditions such as temperature. Therefore, a hysteresis circuit with a highly accurate and stable hysteresis circuit is desired.) The accuracy and stability of currently available hysteresis circuits do not necessarily meet this requirement.Figure 1 shows a Schmitt trigger circuit according to the prior art. An example of this is shown below. FIG. 2 shows an example of the input/output characteristics of a Schmitt trigger circuit. P3 edge date field effect transistor (GFET) Q1! Q2 + Q3
is connected in series between the power supply voltage (VDD) line and the ground (ss) line, and the GFET Q4 is connected between the vDD line and the connection point of GFET Q2 + Q3.

Input (vI, N) Terminal yb"G""' Q2
r Q3 is connected to r-to, and GFET 'Q
The connection point of l + Q2 is the GFET. Output via the date of Q1 + Q4 and the inverting buffer circuit 11 (■OUT)
connected to the terminal. Engineering GFET Q.

is a normally-on type depletion mode transistor, and Q4 is a normally-off type enhancement mode transistor. , Q4 conduct, and Q3+Q4 form a voltage divider circuit. This voltage divider VRmF and the input terminal
Voltage V, and voltage GFffT, Q, and 20 are the source voltage and date voltage, respectively. As shown in Figure 2, when the input voltage becomes VT
BT Q, □.

The %old at the connection point of Q2 drops from high (H) to low (L). This L voltage is turned off, and becomes an H voltage via the inverting buffer 11 and is supplied to the output terminal voUT. Note that the inversion buffer 1 may be omitted to output an inversion output.

Next, a case where the input voltage decreases will be explained. When the input terminal is high, the input terminal is high, and the input terminal is off.
Q2 and Q3 are connected in series between the DD line and 788247 to form a voltage dividing circuit. Engineering GFET Q
21 The voltage division at the connection point of Q3 and the input voltage V are ■uv
When the input terminal voltage vIN is less than V and the voltage between p1 and gate becomes less than a threshold value, GFET Q2 is turned off.

That is, Q3. The circuit threshold ■T, vI2, and the differential pressure △VT of the circuit as seen from the input terminal are created by the partial pressure of Q, the partial pressure of Ql-Q2+Q3, and the differential pressure thereof.

Only L, depression mode, GFFJT Q□ and enhancement mode, GFFJT Q2. Q3+ Q
4'kA, the components of the voltage divider circuit and their components change greatly when the input terminal rises and falls, so parameter fluctuations in the manufacturing process can result in large fluctuations in the threshold value and its difference. Furthermore, there are also drawbacks that can be seen as large fluctuations in the threshold values and their differences due to differences in the dependence of the valley transistors on power supply voltage fluctuations and temperature changes.

An object of the present invention is to provide a hysteresis circuit having highly accurate hysteresis characteristics determined by r/'i. A reference voltage circuit that generates a variable reference voltage is constructed using a normally-on field effect transistor connected to the field effect transistor. A stable and highly accurate hysteresis characteristic is created by changing the total source-drain resistance of the device.

Voltage divider configurations can be created with fixed resistors or fixed bias field effect transistors. Precision and stability can be further improved by configuring the voltage division configuration using a normally-on field-effect transistor of the same polarity as the feedback normally-on-field-effect transistor.

FIG. 6 shows an embodiment of the invention. In the same figure, a comparison circuit 1 using, for example, a turtle current switching type differential amplifier has 40 input terminals, a force voltage vIN, and a variable reference voltage VftE.
F is input, the buffer circuit 2 is blown, and the output terminal 5 is
■ Output voltage. UT k supply. The output voltage ■oUT is also supplied to the reference voltage circuit 3.

Reference voltage circuit 3 is connected to t source DD and ground line VSS
and three normally-on-depleted mode type insulated date field effect transistors (GF).
) Qllll Ql21 Ql3 included. These transistors Q11 Q12+Q13 vi are fabricated in the same process and arranged in the same direction within the IC board.

GFKT Q and Q are connected in series between VDD and SS, and their dates are short-circuited to their respective sources and given a fixed bias. Another IGF
, h; T Q, is in series with GIT Q, and also 'ET Q, on the eye.

is connected in parallel with , and its date is connected to the output '1 voltage terminal 5 and output voltage ■. We are receiving the return of UT. Engineering G
A reference voltage VRFiF is supplied from the connection point between FET Q and IGFET Q12+Q13.

Normally-on IG, FET Q, 13 is its F”-)
The on-resistance is changed by bias. That is, a predetermined on-resistance is provided depending on whether the applied voltage VoUT is low (L) or high (H). First, it is assumed that the input voltage N is low (L) and the output voltage OUT is also low (L).

At this time, reference voltage ■Ryuhako GFET Qko□ and Q□2
and L-biased GFET Q130 on-resistance. VHHy this! The comparator circuit 1 compares the input terminal VN with the reference voltage VRFiF, and sets its output to low (L) when VXY>vREF.
) to high (H). Therefore, the input voltage (trip point voltage) VT when the output transitions from low (L) to high (uniform) when the input voltage increases is ■T#■
It becomes R□.

1 1 1 V engineering N〉■
The output voltage becomes T□. When U is in the H state, GFET Q13 is biased high (H) and
Tortoise pressure■ Bring REF close to ground voltage. Therefore, the input voltage V
Even if TN crosses VT due to noise, etc., chattering no longer occurs and the output voltage is stably maintained at a high H state. Reference 1tEE VREF u in output H state
IeFET Qll ToQ12 &Hihi(H)Ha(
VRK is determined by combining the on-resistance of Q13 that is
VREF becomes F < VftEF. Output from H to L2 1 2
The input voltage (trip point voltage) when returning to
vTL; VREF. In this way,
An input/output characteristic with 2 2 steresis △moss = ■T-VT is obtained.

In the unreal current example, the transistors 1, Q, Q12, and Q12+ that constitute the reference voltage circuit 3 are all depletion mode type, and the impurity-doped v! Variations in process parameters such as J, depth, depth, date insulating film thickness, and mask process errors can be commonly accounted for in each element. Therefore, these influences cancel each other out, and the partial pressure ratio can be maintained at a desired value. Furthermore, since the valley elements are transistors of the same type, the voltage division ratio is the valley element Q11 + Q]
, L+Q13 channel size ratio C, W/L), and can be made unaffected by power supply voltage fluctuations and temperature changes. Also, set voltage (VR
It is also possible to completely improve the accuracy of F and vRwp), and for example, by increasing the pattern width 'kl in steps of 0.5 μm, it becomes possible to set a minute voltage on the order of 1 mV.

FIG. 4 shows a complete alternative embodiment. In Figure 6, IGFET
The configuration is the same as that shown in FIG. 6, except that the voltage dividing configuration composed of Q1□ and Q is composed of resistors R11 and R12. The resistors R11 and R12 are made in the same process and are arranged in the same direction within the C board. For example, it can be made from a polysilicon resistor. R11 and R12 as in the embodiment of FIG.
The partial pressure ratio can be made insensitive to the 7°0 process parameter, etc., and can be set accurately and stably.

Depending on the application, it may be desired to change the trip point and the difference Δ■T when the input voltage rises and falls. Even in such cases, prepare only the necessary types of values.・Q
11'+ Q42i Q13 or RIll R121Q
If the dimensions of 13 can be made optional on a certain mask (for example, a gut mask in the case of a metal dating process) for selective convenience, it will be possible to meet the requirements easily, quickly, economically, and accurately. I can do it.

It will be obvious to those skilled in the art that the present invention is not limited to the above-mentioned embodiments, and that various modifications and combinations are possible.

According to the present invention, a daytime-accurate hysteresis circuit that is stable against changes in power supply voltage and temperature as well as parameter fluctuations in the manufacturing process is provided using the same process as the conventional one and with a simple circuit configuration. be done.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a conventional Schmitt circuit, Fig. 2 is a graph showing an example of input/output characteristics of a Schmitt circuit, and Figs. 3 and 4 are circuit diagrams showing an embodiment of the present invention. . Explanation of symbols 1... Comparison circuit, 3... Reference voltage circuit, 4... Input terminal, 5... Output terminal. Representatives: Asamura and 4 people

Claims (1)

[Claims] (1) A reference voltage circuit including a normally-on field effect transistor and having all voltage dividing terminals that generate a reference voltage by dividing the power supply voltage, an input terminal to which the input voltage is applied, and a comparison input terminal, respectively. a comparator circuit connected to the voltage dividing terminal and the input terminal and generating an output voltage based on a comparison of comparison input voltages at the output terminal; and a comparator circuit connected between the output terminal and the field effect transistor, the output and a feedback path for controlling the reference voltage based on the voltage. (2. The hysteresis circuit described in Claim 1 JJi is formed in an integrated circuit, and the reference voltage circuit is connected in parallel to a voltage dividing configuration composed of the same type of transponder and a part thereof. 0(3)%ifF hysteresis circuit including the normally-on type electric field effect element 2 and the Lanzoster having the same type of element 2 as described in claim 2. A hysteresis circuit in which all field effect transistors are degustation mode insulation case field effect transistors.