JPS59122215A - Automatic waveform equalizer - Google Patents

Abstract

PURPOSE:To remove DC offsets with a simple constitution by inserting a passive filter cutting off DC between a correlator and an error signal generating circuit or between the input terminal of a transversal filter and the correlator. CONSTITUTION:An input x(t) is inputted to the transversal filter 1 and the correlator 4. An output y(t) from the transversal filter is outputted from an output terminal and also inputted to the error signal generator 3, which compares the input with a signal (r) from a reference signal source 2 to generate an error signal e(t). Then, the passive filter 50 consisting of a capacitor 5a and a resistor 52 removes a DC offset from the signal e(t) and outputs a signal e0(t) and the correlator 4 finds out the correlation between the signal e0(t) and another signal x(t). On the basis of the correlated result, a tap gain memory 6 is compensated and the transversal filter 1 is automatically controlled. The passive filter can remove an offset also from the signal x(t) in stead of the signal e(t).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic waveform equalizer that eliminates code amount interference caused by linear distortion of a transmission path in digital signal transmission.

[Technical background and problems of the invention]

In the transmission of digital signals, the transmitted signal may be subject to isometric interference (due to linear distortion of the transmission path). A signal subjected to code amount interference has a reduced margin against noise and an increased error rate during reception. A waveform equalizer is used to remove this code amount interference. As a waveform equalizer, an automatic waveform equalizer that performs an equalization operation corresponding to an arbitrary transmission path is widely known.

FIG. 1 shows an example of an automatic waveform equalizer. Transpersal filter 10 inputs X
-41) (where τ is the transpersal filter 1
delay time of the delay unit). This output y(t) and the output r of the reference signal generator 7
(t) is calculated by the adder 3, and its output, the miscalculation signal e(t), is "(t)""(υ-r(t) "°"
``''''' (2) is given.

The square integral of the error signal e(1) is evaluated as the evaluation criterion E as shown in the following equation.
shall be.

E-fe(t)dt Tap dyne is controlled to minimize this E.

If we use the maximum slope algorithm for minimization, −
What is necessary is to modify the tap gain along the direction of E. Considering each cod fC1, the correction direction is expressed by the following equation.

Equation (3) shows the cross-correlation between the input X(t) and the error signal e(t). If the newly corrected tap f/j''in is C, (nrw), and the uncorrected tap dyne read from the tag dyne memory 6 is CI(old), then ?

(α: proportionality constant, positive number) (nevr) C1 is stored again in the tag-dyne memory 6. In FIG. 1, the correlator 4 calculates the equation (3), and the adder 5 corrects the tap dyne shown in the equation (4).

By repeating this correction operation, the optimal tap dyne is converged. This correction operation of f'f-in is called a learning identification method. In this way, the multiple inputs ``(t)'' to the transpersal filter 1 having the automatically determined tap-dyne Ci are automatically equalized.

However, when such an equalizer is constructed from an analog circuit, a DC offset occurs due to variations in each circuit element, temperature changes, and the like. Let's consider the effect of this DC offset. For simplicity, it is assumed that the transpersal filter 11 is composed of one delay device 12, one multiplier 13, and one adder 14, as shown in FIG.

As shown in the following equation, the input signal X A C (t) has a value σ□ with an average of zero and a root mean square of a fixed period Tsec like pseudo-random noise with a period T. Assume that the signal is completely free of distortion.

-7 The effect of DC offset is expressed as XDC# eDC for each input signal and error signal. Input signal XAc(
j) is input to the delay device 12, and from the delay device 12, the input signal C is input. (1) Signal C delayed by a certain amount of time τ. (tor) is output. The output XAc(t-T) of the delay device 12 is input to the multiplier 13, while the adder 15 adds the DC component XDC generated by the DC component generator 16. Here X
DC represents the DC component added from the DC component generator 16 until it is input to the correlator 17. If the signal input to the correlator 17 is X(t-4), then X(t-r)
= XAC(t-r) 1xDc ---°
°(7). The output XAc(j-T) of the delay device 12 is multiplied by 0 in the multiplier 13, where C is the tap gain value read out from the tap-dyne memory 18.

The output of the multiplier 13 is converted to the input signal XAC(
t) (!: output of transversal filter 1)'(t).

y(t)” XAc(t)+ Cx person C(t-τ)
=゛''-(8) This y<t) is output as an equalized output. This )'(t) is also input to the adder 19 for calculating the error. ) is undistorted, and the output r(
t).

r(t)”XAC(t) −=
°=゛=°(9) In the adder 19, the transparsal
The difference between the output y(t) of the filter 11 and the reference signal r(t) is taken. From equations (8) and (9), this difference is y(
t) −r(t)=XAc(t)+”Ac(t-7)
”Ac(t)2CXAc(t-r)
---(10). This value is input to an adder 21 and a DC component generator 22 representing the DC offset.
The direct current component eDC generated by is added. Adder 2
If the output of 1 is e(t), Equation (9),' (10
), e(t)=y(t)-r(t)+eDC=C
XAC(-r) + eoc −-°゛-(
11). The correlation value between the output X(t) of the adder 15 and the output e(t) of the adder 21, which is calculated by the correlator 17, is calculated by the equation (7), since XDC# eDC is a DC component.
.

(11) Become Yoshifu. The average of XAC(j) is σ according to equation (5), and the root mean square is σXc according to equation (6). Therefore, the second and third terms of equation (12) are zero. The output of the correlator 17 expressed by equation (13) is
The constant multiplier circuit 23 multiplies the signal by a positive constant 2α and sends it to the adder 24 as a tap gain correction amount. The adder 24 calculates the difference between the uncorrected tap gain C(old) read from the tap dyne memory 18 and the output of the correlator 17 multiplied by a constant 2α as + (new), and calculates the difference between the tap dyne memory 18 and the output of the correlator 17 multiplied by a constant 2α. = (1-2ασA2ε) c(Old) 2αxDCe
DC...(14) is calculated.

Next, let us consider how the tap gain is corrected in the configuration shown in FIG. 2 and assuming that the DC error is added at the stage before the correlator 17, as described above. Since tag dyne is repeatedly modified,
The subscript indicates the number of revisions. For example, C(
0n is the tap dyne when no correction is made, and C(6) is the tap gain when the correction is made n times. Also, subscripts are added to the output cuff (t) of the transpersal filter 11 and the error e(t), and 7(t) calculated using the tap dyne C(n) that has been corrected n times is y(ro). )(1), let e be expressed as "(n)(t) (0). As the initial value of tag dyne, C(0)20...
...Assume (15).

Consider the nth revision. At this time, the tag-dyne memory 18 stores C(nl) which has been corrected (ni) times. Therefore, in equation (14), C(new) becomes C(n), p c(o
ld) is C(n-1)tealnote, C'=(1-2αc
rX C)C(n') -2α"DCeDC"""
(16). Here, 1-2ασ:c ”P...
...(17) x Dceoc = Q
−−・・(1f3), equation (16) becomes C■=pC(nl) 2αq −・”−−
(19) Similarly, c(n-1): PC(n-2)-2αQ, , , (2
o) Substituting equation (20) into equation (19), C(n)=P(PC''-2)-2aQ)-2αQ=P2
C” '-2αQ(1+P) −・−−−・・(2
1). Tag dyne c(n 2) appearing on the right side
Similarly, we can express it in terms of tag dyne with fewer modifications. C(0) is assumed to be a gap as shown in equation (15). Therefore, by substituting equations (17) and (18) for P and Q, C(b) becomes 0<'''<'r**b.In this way, due to the influence of the DC component, The tag dyne does not diverge, but converges to the value shown in equation (25).Thus, even though there is no distortion in the input signal, the tag dyne takes the value shown in equation (25).For this reason, ,
The response of the transversal filter to the impulse is the addition of an unnecessary signal 32 to the main signal 3, as shown in FIG. 3(a). If there are a plurality of tags, the response of the fixture, such as an automatic waveform, to the impulse will be the same as the number of taps added to the main signal 31, as shown in FIG. 2(b). Furthermore, when a step waveform is input to such a circuit, the output is as shown in the figure (
As shown in C), a step-like sag occurs. Thus, it is clear that the DC component must be removed because it prevents proper equalization.

As shown in equation (25), the DC component X included in the input
The product of DC and the DC component epc included in the error generates a tag 0 signal that requires cine, and to make it zero, remove at least one of the input DC component XDC or the error DC component eDC. Just do it.

“A one-ChtpAuto
matic Equalizer For Echo
Reduction InTe1etext 'IE
EE Tr, on C, E, Vol, CE-2
7 No., IP512-529, 1981J is known.

As shown in FIG. 4, this is a format in which the error signal e(t), which is the output of the adder 3 in FIG. By adding a DC offset removal circuit 40, the error signal e
(t) K is applied to remove the DC component.

The transfer characteristics of this DC offset removal circuit 40 are as follows. Integrator 4 is assumed to be a CR integration circuit, its transfer characteristic is F(8), the gain of DC amplifier 42 is A1, the output of adder 43 is J, the Lanolas transform of eo is El(s),
When Eo(s), the following equation holds true.

El(g)-E. (s)E(s)A=Eo(s)
・=−=−・−・−(26). When the step function u (t) is input, that is, e(t) 20(t) - 9 peaks - (30), the frequency ω is -3 dB down in the time domain. is the formula (29)%
Equation % As described above, this DC component removal circuit 4o requires a high gain, low drift DC amplifier 4I as a component, which has the drawback of increasing cost.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic waveform equalizer that eliminates the influence of DC offset using a simple circuit and achieves good equalization operation.

[Summary of the invention]

The present invention is characterized in that a passive filter for removing DC offset is inserted on the input side of one or both of the correlators that perform a correlation calculation between the input signal of the trans-purple filter and the error signal.

〔Effect of the invention〕

According to the present invention, with a simple configuration that does not use a DC amplifier, it is possible to remove the influence of DC offset, prevent unnecessary tap-dyne caused by DC offset, and obtain good equalization operation. .

[Embodiments of the invention]

FIG. 5 shows an embodiment of the present invention, in which a capacitor 51 is connected between an adder (error signal generator) 3 and a correlator 4.
A CR-pass filter 50 composed of a resistor 52 and a resistor 52 is inserted as a passive filter for removing DC offset.

Now, the Laplace ei(t) transformation of the input signal of the filter 51 is Ei(11), and the output signal e. Let Eo(s) be the Laplace transform of <1). When a step function is applied as input, the transfer characteristic becomes
37), in the time domain - and CR eo(t) ”...
......(39) -3dB down frequency is ω. That's good ω. = Kawara......Song (4o). The only difference is that the constant A is now 1 compared to the conventional equations (32) and (34).

Therefore, by appropriately selecting the constant CR, it is possible to achieve the same recurrent offset removal effect as in the conventional example without requiring a high-gain optical amplifier.

FIG. 6 shows another embodiment of the invention, in which a similar passive filter 50 is inserted between the input terminal of the transversal filter l and the correlator 4, and the direct current of the input signal X(t) is This is an example of a configuration in which the offset is removed and then input to the correlator 4.

As can be seen from equation (25), it is sufficient to remove the DC offset of at least one of the input signal and the error signal, so the configuration of FIG. 6 can also achieve the same effect as the previous embodiment.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the basic configuration of an automatic waveform equalizer, Figure 2 is a diagram to explain the influence of the DC component, and Figure 3 (,)
(b) Figure 4 shows the configuration of a conventional automatic waveform equalizer with a DC offset removal circuit added; FIG. 6 is a diagram showing the configuration of an automatic waveform equalizer according to an embodiment of the present invention. 1... Transparsal filter, 3° error signal generator, 4... Correlator, 6 ...Tap-dyne memory, 50--DC blocking passive filter, 51...Capacitor forming the DC blocking passive filter, 52...Resistor forming the DC blocking passive filter.Applicant's agent Patent attorney Suzue Takehiko Fang 2 Figure 12 Figure 3 (a) (C) Fang 4 Figure Sai 5

Claims (1)

[Claims] a transpersal filter, an error signal generator that obtains an error signal of the output signal of the transpersal filter relative to a reference signal, and a correlation that performs a correlation operation between the error signal and the input signal of the transparsal filter. In the automatic waveform equalizer, a passive filter for DC offset removal is inserted on one side of the error signal generation side in the automatic waveform equalizer, which comprises: An automatic waveform equalizer characterized by: