JPS59122137A - Digital signal regenerating circuit - Google Patents

Abstract

PURPOSE:To regenerate accurately a digital signal by eliminating the effect of a low frequency noise component, preventing an envelope from being zero-crossed and performing accurate envelope detection to regenerate a DC component. CONSTITUTION:An input signal is divided into three. A DC voltage of +E is added at an adder 12 and the result passes through a time constant circuit comprising a rectifier 16, capacitor C1 and a resistor R1. A DC voltage of -E is added at an adder 13 and the result passes through a time constant circuit comprising a rectifier 17, the capacitor C1 and the resistor R1. After these two outputs are added, the result is attenuated into 1/2 by a subtractor 23, and the attenuated result is subtracted from the input signal to have an envelope made nearly flat. The output of the subtractor 24 is divided further into four, the discharge of a capacitor C2 is controlled by the output of a differentiating device 37 to detect the positive and negative envelopes, allowing to regenerate the DC component with suppressed low frequency noise by adding the envelopes.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to the recording and reproduction of digital signals subjected to code modulation, communication, etc., which are subject to frequency band limitations and which have passed through systems with significant noise contamination. It relates to waveform equalization, and is particularly the waveform distortion that occurs when a digital signal whose frequency spectrum has expanded to the low frequency band passes through a system that limits the low frequency band, and at this time, it is contaminated with significant low-frequency noise. The present invention relates to a digital signal reproducing circuit that can correct for.

Conventional configuration and its problems As is well known, most digital signals handle binary values of 0 and 1 or -1 and 1. For simplicity's sake, let's consider a binary NRZ modulated digital signal.
There are countless possible combinations of 0, 1 or -1, 1 signals. -As an example, if we consider three specific types of arrangement, Figure 1 (a) (b) (c)
A Tsuma turn like this can be considered.

In FIG. 1, the average value of the signal in pattern (a), that is, the DC component, is zero, the DC component in pattern (b) is +0.5, and the DC component in pattern (C) is -0.5. Therefore, if these /NO turners ≦ cascaded signals pass through a system that can pass flatly up to DC, the waveform will be reproduced correctly as shown in Figure 2 (a), but the DC component will be ( As shown in the broken line in a), when passing through a system in which the low frequency band is restricted, the DC component cannot pass through, and the fluctuation in the envelope as shown in Figure 2 (b) It occurs in response to the ingredients. At this time, if the high frequency band is not limited), the rising and falling slopes of the signal will be extremely rapid, so the position information of the zero crossing point will be retained, and there will be no error in the reproduction of the digital signal. Does not occur. However, in reality, the high frequency band is also limited, so even with optimal high M equalization, the signal rises slowly and the correct zero-crossing position shifts as shown in Figure 2 (C). Sisters,
It was causing an error.

Conventionally, the following two methods have been used to deal with the occurrence of such errors.

The first method is to perform modulation that produces a pattern in which no direct current component of the signal occurs or in which the low-frequency spectrum is suppressed as much as possible. The second method is to reproduce the DC component from the signal envelope. The present invention relates to the latter method, and has been previously published in the literature (Chuyo et al. "Study of integral detection method in NRZ recording, Institute of Electronics and Communication Engineers Magnetic Recording Study Group MR77-4619
78-3), it had a configuration as shown in Figure 8. In Figure 3, (1) and (2) are diodes, (3r-(
4 is a capacitor, (5) C6) is a resistor, (7) is an adder, and (8) is a subtracter. In this configuration, the part consisting of the diode (1), capacitor (3), and resistor (5) performs envelope detection on the negative voltage side of the input.
The output waveforms at points A, B, 0, and D in FIG. 3 are the curve p in FIG. 4(a). * q o , r o+ 8 (As in 1, the output waveforms of the 3rd and 18th points are as shown in FIG. 4 (bl), and the DC component is regenerated.

However, such conventional methods often suffer from the following two drawbacks. The first drawback is that when the amplitude of the noise component is the same as or even larger than the signal level, the envelope q divides the zero level as shown in Figure 5, and in the conventional configuration as shown in Figure 3, this zero level It was no longer possible to detect the envelope in the area where the value was divided, resulting in errors in theta reproduction. In particular, when the low frequency is limited by a relatively high frequency, the period of change of the signal envelope approaches the period of change of 0.1 or 1°-1 of the signal, as shown in Fig. 6 ( a) curve q′, r
In order to prevent this, we compensate for the low frequency to some extent and use the method shown in Figure 6 (
Generally, the configuration is such that the period of the envelope and the period of the signal are Nf, as shown by the curve q''I of bl.For this reason, in a system that handles minute signals, the low In other words, the curve p in Figure 6 (b)
Low-frequency noise is added to “, and the envelope is qM in Fig. 8, ,
sr, and the positive envelope output in the section X, that is, the output at point B in Figure 3, was zero, and a correct envelope could not be obtained. Next, the second drawback is that even in cases like the one shown in Figure 6, where there is relatively little noise in the low range, as seen in lights, E, and F,
Figure 3 Discharge resistor (5) (6) and capacitor (3) (
If the slope of the line (envelope) connecting the signal peaks is greater than the time constant determined by 4) (which determines the downward slope of the curves q' and r''), an accurate envelope could not be obtained. 1,
To deal with this, a possible method is to reduce the discharge resistances (5) and (6) in Figure 8, that is, to decrease the time constant, and to make the downward slope steeper, as shown by the broken line in Figure 6(b). However, for example, the intersection point with the rising edge of the signal, such as point G, is too low,
An error occurred in envelope detection.

Purpose of the Invention The present invention has been made in view of the two drawbacks of the conventional method. First, the influence of low-frequency noise components is removed, and the envelope line is prevented from zero-crossing, and then an accurate envelope is obtained. By detecting the connection and regenerating the DC component, it is possible to accurately reproduce the digital signal, and it is also useful when transmitting the digital signal through a system that has a limited low frequency band and contains a lot of low frequency noise. The purpose of this invention is to provide a circuit that reproduces the original signal with sufficient accuracy.

Structure of the Invention In order to achieve the above object, the present invention consists of the following two parts. One part is a part that mainly removes low-frequency noise and prevents the signal envelope from crossing zero. The other part is to detect the accurate envelope of the output and remove envelope fluctuations.If the DC component fluctuations and low-frequency noise are large enough to cause the envelope to cross zero, the above-mentioned However, in the present invention, in the first step where the positive envelope is detected, the envelope of the signal to which a positive DC voltage is applied is detected, and the negative envelope is In the detection part, the envelope of each signal is obtained by applying a negative DC voltage, and the signal obtained by adding these positive and negative envelopes is subtracted from the input signal, thereby detecting the envelope heartbeat of the input signal. The line is suppressed to such an extent that it does not cross zero, and as a second step, the output signal is further subjected to similar envelope detection to obtain an accurate DC component in order to sufficiently suppress envelope fluctuations. In this case, @2-stage DC component detection is performed as shown in Figure 8 (3) at the rising edge of the signal pulse.
By discharging the charge in the capacitor (4) in a short time and charging it again to the peak value of the pulse, it is configured to remove the influence of the peak voltage of the previous pulse, allowing more accurate envelope detection. It is possible.

Description of examples Embodiments of the present invention will be described below based on the drawings.

FIG. 9 shows a specific embodiment of the present invention. In Figure 7, 0υ
is an input terminal, 0z03 is an adder, (Jtl QS is a DC voltage source, OGα is a rectifier (diode), 0119
(11 is a capacitor, (a) Q◇ is a resistor, (a) is an adder, (c) is a 1/2 attenuator, (24I is a subtractor, is a rectifier (diode), @ (a) is a Capacitor, G!
1111 is a resistor, @110η is a switching element, (3
31 (341 is a diode, 3FA is an adder, (G) is a waveform shaper, (3η is a differentiator, (3 barrel is a 1/2 attenuator, (39) is a subtracter, and (3) is an output terminal.

If a digital signal including an envelope fluctuation as shown in FIG. 10 is input to the input terminal Oη, the signal is divided into three parts and input to the adder Q and the subtracter uZ'l.

First, the signal input to the adder (6) is added with the voltage generated by the DC voltage source 04 (+Eff), and the adder (2) outputs the voltage waveform of curve a in Figure 10, and the rectifier The capacitor is charged to O fat through αQ.

When the input waveform of the rectifier θQ passes the peak, the capacitor (
The input voltage of the rectifier aQ is lower than the voltage of the rectifier 06 (g), and the rectifier 06 is prevented from flowing backwards from the output to the input, and the peak value is maintained. ), the battery is discharged with a discharge time constant CR.

Therefore, the voltage waveform across the capacitor 0 becomes like the curve d1 in FIG. Next, the signals distributed to the adders (to) undergo the same operation, so that the output of adder 0 becomes curve C in Fig. 10, the curve of the output of capacitor Cll becomes el, and the curve dl+eH becomes the adder (to), respectively. b), and the first
The curve of Figure 0 is output. Since the DC component and low-frequency f/s of the input signal at the input terminal (b) are the average value of the positive envelope line and the negative envelope line, the output of the adder is further reduced to 1/1 by the attenuator (to). 2, resulting in curve b1' in Figure 10, which is subtracted from the input signal by the subtractor (support), and the first
As shown in Figure 1, the envelope is approximately flattened.

However, at this point, as described above, an accurate envelope is not necessarily extracted, and the envelope is further flattened through the system from (c) to h+i. The output from the subtracter is distributed to four parts: the rectifier (to the rectifier), the waveform shaper, and the subtractor (A).
Consider the case where the output of the fathom is curved as shown in FIG. 12(a). The signal input to the rectifier (A) charges the capacitor with a positive rectified voltage until it reaches the first peak (in Figure 12), point A), and after passing the peak, this peak voltage vP is held. . On the other hand, the output signal of the subtractor 4) is waveform-shaped into a rectangular wave as shown in FIG. 12(b) by a waveform shaper f-fuchi with a sufficiently large degree of amplification. Differentiate this with the differentiator mouth η, and the first
This differential pulse is separated into positive and negative pulses by a diode 131, which outputs the waveform shown in FIG. 2 (C). The positive differential pulse output from the diode closes the switching element and discharges the charge stored in the capacitor through the resistor R2 to point B in FIG. 12(a). When the capacitor is discharged to point B, the input to the rectifier (curve h in FIG. 12(a)) exceeds the voltage of the capacitor (a), and charging starts again. By repeating the above process, a positive envelope line is detected as shown by curve j in FIG. 12(a). Similarly, rectifier, capacitor (to)
, the resistor and the switching element (c) in Figure 12 (
A negative envelope like the curve f in a) is detected, and the addition device CM
, is added. The signals added together are attenuated (c)
This means that the DC component (curve g in FIG. 12(a)) of the output signal of the subtracter h< is detected.

This DC component is subtracted from the output signal of the subtractor C24) by the gW unit (
) to suppress low-frequency noise,
Further, a digital signal whose DC component has been regenerated is outputted to an output terminal [a].

More than the effects of the invention, according to the present invention, the low frequency band is limited,
In addition, it is possible to reproduce the original signal with sufficient accuracy even for a digital signal that has passed through a system containing low-frequency noise having an amplitude equal to or higher than that of the signal, which is extremely useful industrially.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the generation of a DC component, Fig. 2 is an explanatory diagram of the shift of the zero cross position due to the DC component, Fig. 8 is a conventional circuit configuration diagram, and Fig. 4 is an explanatory diagram of the effect of the conventional circuit. Fig. 5 is an explanatory diagram of a case where the pulse width changes greatly, Fig. 6 is an explanatory diagram of an example of mismatching of the discharge time constant, and Fig. 7 is an explanatory diagram of an example of mismatching of the discharge time constant.
Fig. 8 is an explanatory diagram of the cause of the increase in discharge area noise, Fig. 8 is an explanatory diagram of the drawbacks of the conventional circuit, Fig. 9 is a circuit configuration diagram of the present invention, and Fig. 10 is an explanatory diagram of the cause of the increase in discharge area noise.
Figure, Figure ii, and Figure 12 are detailed explanatory diagrams of the present invention. 4 (c)... Adder, 04 Q5... DC power supply, O
Qaη... Rectifier, (G) (11... Capacitor,
) Qυ...resistance, (a)...adder, (to)...
・1/2 attenuator, (241...subtractor,) suggestion...
Rectifier, @)... Capacitor, 4-... Resistor, C
l1lle12...Switching element, 03) (Foundation)
...Diode, f3[1...Adder, Trowel...Waveform shaper, Fighter...Differentiator, (I)...-1/2 subtractor, (A)...-Subtractor substitute People Yoshihiro Morimoto Figure 1 ootooot θ0 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 I7 Lower Figure β Figure 1 O Figure 1/Figure 1? figure

Claims (1)

[Claims] 1. Means for adding a positive DC voltage to an input signal, means for adding a negative DC voltage to an input signal, means for rectifying the outputs of the means for adding positive and negative DC voltages, and the rectification. a capacity for charging each of the outputs of the means for
A first signal obtained by rectifying the output of the means for slowly discharging the positive and negative charges of this capacitor and the means for adding the positive DC voltage, and a negative DC voltage obtained as a voltage charged in the capacitor. a means for adding a second signal obtained as a voltage charged in a capacitor by rectifying the output of the adding means; and attenuating the output of the means for adding the first and second signals; the first subtracted from the input signal
a means for rectifying the positive voltage output from the first subtracting means; a means for rectifying the negative voltage output from the first subtracting means; and a means for rectifying the negative voltage output from the first subtracting means; and a capacitor for holding a negative voltage, a means for quickly discharging the charge charged in each of the capacitors, a means for adding the voltages of the respective capacitors, and the first subtracting means. a second subtracting means for subtracting the output of the means for adding the voltages of the respective capacitors; a means for shaping the output of the first subtracting means into a rectangular wave; and a means for differentiating the output of the shaping means. 1. A digital signal reproducing circuit comprising: a digital signal reproducing circuit, wherein the means for releasing the charge in a short time is controlled by the output of the differentiating means.