JPS59122138A - Digital signal regenerating circuit - Google Patents

Abstract

PURPOSE:To attain correct DC regeneration while suppressing low frequency noise by adding positive and negative DC voltages to an input signal and passing the added signal through a time constant circuit. CONSTITUTION:The input signal is divided into three; one is added with a DC voltage of +E at an adder 11 and the remaining two signals are added with a DC voltage of -E at an adder 12. Each output of the adders 11, 12 is applied respectively to the time constant circuits consisting respectively of a capacitor 17 and a resistor 19, and a capacitor 18 and a resistor 20. The time constant circuits supply an output to the adder as positive and negative envelope signals. The output of the adder 21 is attenuated to 1/2 and the result is subtracted from the input signal. Then, even if the amplitude of low frequency noise is larger than that of the input signal, the signal regeneration is performed accurately by the correct DC regeneration.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to waveform equalization of digital signals that have passed through a system with a limited frequency band, such as recording/reproducing or communication of code-modulated digital signals. In particular, a digital signal whose frequency spectrum has expanded to a low frequency band is often contaminated with low frequency noise, and the present invention relates to a digital signal reproducing circuit that can correct waveform distortion caused by passing through a system that limits the low frequency band.

Conventional configuration and its problems As is well known, most digital signals handle binary values of 0 and 1 or -1 and 1. For simplicity's sake, let's consider a binary NRZ modulated digital signal.
There are countless possible combinations of how the 0's and 1's of the signal are arranged. - As an example, if we consider three specific types of arrangement, patterns such as those shown in Fig. 1 (a), (b), and (c) can be considered. In Figure 1, the average value of the pattern (a), that is, the DC component is zero, and (b) the DC component of the tube turn is +0.
．． 5, the DC component of the pattern (c) is -0.5.

Therefore, if a signal in which these patterns are connected in cascade passes through a system that can pass flatly up to DC, it will become as shown in (a) in Figure 2.
The waveform is correctly expressed as 1q, but its DC component is (a
), so when the low frequency band passes through a limited system, the envelope changes as shown in FIG. 2(b), corresponding to the DC component. At this time, if the high frequency band is not limited, the rising and falling slopes of the signal will be extremely steep, so the position information of the zero crossing point will be maintained and no error will occur in the reproduction of the digital signal. However, in reality, since the high frequency band is also limited, the rise of the signal becomes gradual, and the correct zero-crossing position shifts as shown in FIG. 2(c), causing an error.

Conventionally, such errors have been dealt with roughly in the following two ways. The first method is to perform modulation that creates a pattern in which the DC component or low-frequency spectrum of the signal is suppressed as much as possible. The second method is to regenerate direct current from the signal envelope.

The present invention relates to the latter method, and as can be seen in the literature (Chuuyo et al.' Study of Integral Detection Method in NRZ Recording, Institute of Electronics and Communication Engineers Magnetic Recording Study Group MR77-46, 1978a), there has been a method as shown in Fig. 3. It was structured.

In Figure 3, (1) (2) are diodes, (3) (4)
is a capacitor, (5) and (6) are resistors, (7) is an adder, and (8) is a subtracter. In this configuration, the part consisting of the diode (1), capacitor (3), and resistor (5) performs envelope detection on the negative voltage side of the input;
Points A, B, and C in the diagram.

The output waveforms at each point of D are curves p, q, and r in FIG. 4(a).

S, and the output waveform at point E in FIG. 3 becomes as shown in FIG. 4(b), and the DC component is regenerated. But with this method,
Under low S/fV where the S//N is less than 2 times, the envelope exceeds the zero level as shown in FIG. 5(a), making accurate envelope detection impossible. That is, the output waveforms at points A, B, C, and D in FIG. 3 are the curve T'' in FIG. 5(a).
+ q' + r'+ S', and the output waveform at point E in FIG. 3 became as shown in FIG. 5(b), with errors occurring at points X and Y.

In this way, the cause of signal detection errors is that in addition to the fluctuation of the signal envelope due to the low-frequency limit, low-frequency noise is added, and the fluctuation of the envelope is less than zero, causing the envelope to change. This is because line detection will no longer work.

OBJECT OF THE INVENTION The present invention has been made in view of the above drawbacks of the conventional technology.The purpose of the present invention is to improve the method of envelope detection to improve systems in which the low frequency band is restricted and direct current cannot pass through. To provide a digital signal reproducing circuit that can sufficiently suppress this noise and obtain a correct signal even if the low-frequency noise in the system is significantly large and the amplitude is larger than the signal when transmitting a digital signal through a digital signal. be.

Structure of the Invention In order to achieve the above object, the present invention provides a means for adding a positive DC voltage to an input signal, a means for adding a negative DC voltage to the input signal, and a means for adding the positive and negative DC voltages. A means for rectifying the output of the means for rectifying, a capacitor for charging the output of the means for rectifying, a means for slowly discharging the positive and negative charges of this capacitor, and adding the above positive DC voltage. means for rectifying the output of the means and adding a first signal obtained as a voltage charged in the capacitor and a second signal obtained as a voltage charged in the capacitor rectifying the output of the means for adding a negative DC voltage; , means for attenuating the output of the means for adding the first and second signals, and means for subtracting the output of the attenuating means from the input signal. By superimposing a positive DC voltage to detect a positive envelope, and by superimposing a negative DC voltage to detect a negative envelope, it is possible to expand the operating range of envelope detection. There is.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. @7
The figure shows one specific embodiment of the invention. In Fig. 7, ◇1 is an input terminal, Ql) (6) is an adder, (13o→ is a DC voltage source, and the voltages are +E and -E, respectively. (J.

qQ is a rectifier, α7) (to) is a charging capacitor, θsu (a) is a discharging resistor, ■υ is an adder, (2) is a 1/2 attenuator, ni) is a subtractor, and (c) is a It is an output terminal. Now, when a digital signal including envelope fluctuations is input to the input terminal (Irl+) as shown in Fig. 5(a), the adder 0υ(
The outputs of 6) are the curves w and (b) in Fig. 6(a), respectively.
) will look like the curve j. That is, the input signals are level-shifted by 10E and -E, respectively. level shifted (
No. n is connected to a capacitor (1
7) Charged to ae.

IK style N4θ! 01 (9 is capacitor α″7108)
This prevents the charge from flowing back to the adder αU'4.

By appropriately selecting the discharge resistance (InK), positive and negative envelopes of the signal can be obtained approximately as shown by the curve u in FIG. 6(a) and the curve U' in FIG. 6(b). Therefore, these positive and negative envelope outputs are f(t), respectively, where f (t) and g (t) are the positive and negative envelopes of the input signal.
)+E, expressed as -E of g.

The positive and negative envelope signals are added by an adder 01), and f (t
) +g([) is obtained. Furthermore, the added output is attenuated to 17'2 by the attenuator (A), and (f (t) 10 g
(t)/2, and the average value of the input signal, that is, the DC component, is reproduced as shown by curve X in FIG. 8(a). This DC component is subtracted from the input signal by a subtracter (/I), and a signal with no envelope fluctuation is sent to the output terminal (c) as shown in Figure 8 (c).
It is obtained as in b).

As described above, according to the present invention, even when the low frequency band is limited and the low frequency noise component has a level higher than the signal amplitude, it is possible to sufficiently reproduce the original signal. Further, the present invention has an extremely simple structure and can be realized at low cost, so that the industrial benefits are extremely large.

[Brief explanation of the drawing]

Figure 1 is an illustration of the generation of a DC component in a digital signal, Figure 2 is an illustration of the occurrence of an error in the zero cross position when the low frequency band passes through a limited system, and Figure 3 is an illustration of the conventional 4 is an explanatory diagram of the effect of the DC component regeneration circuit, FIG. 5 is an explanatory diagram of the drawbacks of the conventional method, FIG. 6 is an explanatory diagram of the gist of the present invention, and FIG. 7 is a diagram of the circuit of the present invention. The configuration diagram and FIG. 8 are detailed explanatory diagrams of the present invention. αυ(6)...Adder, θ side α→...DC voltage source, a
aa*... Rectifier, α7) 0119... Charging capacitor, 01(a)... Discharging resistor. ■υ...adder, ni)...1/2 attenuator, (goods)・
...Subtractor agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. Means for adding a positive DC voltage to an input signal, means for adding a negative DC voltage to an input signal, means for rectifying the outputs of the means for adding positive and negative DC voltages, and the rectification. A capacitor for charging the output of the means for charging, a means for slowly discharging the positive and negative charges of this capacitor, and a means for adding the positive DC voltage are rectified to obtain the voltage charged in the capacitor. means for rectifying the output of the means for adding the first signal and the negative DC voltage and adding a second signal obtained as a voltage charged in the capacitor;
A digital (i5'F' knee reproducing circuit) comprising means for attenuating the output of the means for adding the first and second signals, and means for subtracting the output of the attenuating means from the input signal.