JPS59121825A - Fabrication of semiconductor thin film - Google Patents
Fabrication of semiconductor thin filmInfo
- Publication number
- JPS59121825A JPS59121825A JP22759182A JP22759182A JPS59121825A JP S59121825 A JPS59121825 A JP S59121825A JP 22759182 A JP22759182 A JP 22759182A JP 22759182 A JP22759182 A JP 22759182A JP S59121825 A JPS59121825 A JP S59121825A
- Authority
- JP
- Japan
- Prior art keywords
- axis direction
- scanning
- film
- velocity
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体薄膜の製造方法に係り、特に基板上に堆
積した多結晶または非晶質半導体薄膜の高エネルギビー
ムの照射による結晶化処理工程の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor thin film, and particularly to a method for crystallizing a polycrystalline or amorphous semiconductor thin film deposited on a substrate by irradiating it with a high-energy beam. Regarding improvements.
従来の二次元半導体装置の素子を微細化して、これを高
集積化高速化するには限界があ弘これを越える手段とし
て多層に素子を集積する、いわゆる三次元半導体装置が
提案された。三次元半導体装置を実現する上で最も重要
な問題は、絶縁膜上に如伺にして良質の半導体膜を形成
するかということである。この問題に対して、基体上の
多結晶または非晶質半導体薄膜に高エネルギビームを照
射しながら走査して粗大粒の多結晶または単結晶の半導
体薄膜を得るビームアニール方法が提案されている。There is a limit to miniaturizing the elements of conventional two-dimensional semiconductor devices to increase their integration and speed.As a means to overcome this limit, so-called three-dimensional semiconductor devices have been proposed in which elements are integrated in multiple layers. The most important issue in realizing a three-dimensional semiconductor device is how to form a high-quality semiconductor film on an insulating film. To solve this problem, a beam annealing method has been proposed in which a polycrystalline or amorphous semiconductor thin film on a substrate is scanned while irradiated with a high-energy beam to obtain a coarse-grained polycrystalline or single-crystalline semiconductor thin film.
従来のビームアニール法は、基本的には第1図に示すよ
うに、一方向(X軸方向)に一定の速度でエネルギビー
ムを走査しながら、これと直角方向(Y軸方向)に、一
定の間隔ステップを一定の速度で行送シしながら照射す
る方法である。しかし、このビームアニール方法では、
iI]デー光を用いた場ムでは 直径20m以上子線を
用いた場合では長さ100μm1幅1o一 以上の単結
晶シリコン薄膜を形成するのがむずかしい。また実現さ
れた単結晶薄膜には多くの転位や双晶などの欠陥が含ま
れ、さらに走査したビームの軌跡が結晶表面の凹凸とし
て残る等、十分に良質の単結晶を得ることは困難であっ
た。これは、従来のビームアニール法では、ビーム走査
のX軸方向の速度とY軸方向の行送シの速度が共に一定
であるので、熱放散のよいウエハ周辺部が中央部よシ温
度が低くなるという、ビーム照射領域内での温度の不均
一性が生じること、また、X軸方向の走査速度が遅いた
めビーム照射地点の近傍でX軸方向に大きな温度勾配が
存在していること等が大きな理由と思われる。As shown in Figure 1, the conventional beam annealing method basically involves scanning an energy beam at a constant speed in one direction (the In this method, the irradiation is performed while moving the irradiation step at a constant speed. However, with this beam annealing method,
iI] When using laser beams with a diameter of 20 m or more, it is difficult to form a single-crystal silicon thin film with a length of 100 μm and a width of 10 mm or more. Furthermore, the single crystal thin film that has been realized contains many defects such as dislocations and twins, and the locus of the scanned beam remains as unevenness on the crystal surface, making it difficult to obtain a single crystal of sufficiently high quality. Ta. This is because in the conventional beam annealing method, the beam scanning speed in the X-axis direction and the beam speed in the Y-axis direction are both constant, so the temperature at the periphery of the wafer, where heat dissipation is good, is lower than at the center. This is because temperature non-uniformity occurs within the beam irradiation area, and because the scanning speed in the X-axis direction is slow, there is a large temperature gradient in the X-axis direction near the beam irradiation point. This seems to be a big reason.
また、第2図のように、線状電子ビーム101を用い、
これをX@方向七平行に保ったまま矢印で示すY軸方向
に走香して半導体薄膜をア二一ルする方法も提案されて
いる。しかし、この方法でもビーム照射地点のX軸方向
の温度を均一にした−!:ま走査するのがむずかしく、
結晶成長界面が102のように弧を描く場合が多いので
、単結晶の成長方向が一方向に揃わない。こtため05
×5一以上のPr粒を成長させるのは難であった。Further, as shown in FIG. 2, using a linear electron beam 101,
A method has also been proposed in which the semiconductor thin film is annealed by running it in the Y-axis direction shown by the arrow while keeping it seven parallel to the X direction. However, even with this method, the temperature in the X-axis direction at the beam irradiation point was made uniform! : It's difficult to scan,
Since the crystal growth interface often draws an arc like 102, the growth direction of the single crystal is not aligned in one direction. Kotame 05
It was difficult to grow more than one ×5 Pr grain.
寮I発明の目的〕
本発明はこのような点に鑑みてなされたものNf’,r
jAア=−7.7いよ9−Cヵつよいあゆ。Dormitory I Purpose of Invention] The present invention has been made in view of the above points.
jA = -7.7 Now 9-C is a sweet sweetfish.
多結晶または単結晶を形成する方法を提供することを目
的とする。The object is to provide a method of forming polycrystals or single crystals.
本発明は高エネルギビームを連続的に照射しながら走食
してアニールする方法を改良したものであり、エネルギ
ビームの走査速度を、X軸方向、Y軸方向共に走葺範凹
の中央部で端部よシ速くなるように制御する。これによ
り、基板上の多結晶または非品質半導体薄膜のビーム照
射領域でのX軸方向の温度を均一にして単結晶の成長界
面を直線状にし、また成長界面のY軸方向の移動速度も
一定にすることが可能となる。The present invention is an improved method of scanning and annealing while continuously irradiating a high-energy beam. Control the parts so that they are faster. This makes the temperature in the X-axis direction uniform in the beam irradiation area of the polycrystalline or non-quality semiconductor thin film on the substrate, makes the growth interface of the single crystal linear, and also keeps the moving speed of the growth interface constant in the Y-axis direction. It becomes possible to
本発明によれば、良質の半導体薄膜を得ることができ、
三次元半導体装置の素子形成基板として実用上十分な特
性をもたせることが可能となる。According to the present invention, a semiconductor thin film of good quality can be obtained,
It becomes possible to provide practically sufficient characteristics as an element formation substrate of a three-dimensional semiconductor device.
以下、本発明の一実施例を図面を用いて詳しく説明する
。第3図(a)〜(e)は一実施例の製造工程を示す断
面図である。Hereinafter, one embodiment of the present invention will be described in detail using the drawings. FIGS. 3(a) to 3(e) are cross-sectional views showing the manufacturing process of one embodiment.
イ4Lまず第3図0で示すように 例えばP型(100
)方位の単結晶シリコン基板201の表面に絶,j一
膜として約1μmのS IO 2膜202を形成し、そ
の上にSiN膜203を形成する。このSiN膜一二二
=,
!+H’jW o sは後のビームアニール工程でシリ
コン膜一4
′丁で 単結晶化させやすくするために形成するもの’
,0+:’.“七ある。また、シリ・ン基板201は既
に所望の素子が周知の工程を経て形成されているとする
。次に第3図(b)で示すようにSIN膜203の表面
にたとえば5000Xの多結晶シリコン膜204を堆積
する。次に第3図(C)で示すようにエネルギビームを
上部から照射走査して上記シリコン膜204をアニール
する。このビームアニール工程を詳しく説明すると、あ
らかじめ熱の拡散を防ぐためにシリコン基板を500
′cまで昇温しておき、連続電子ビームをビーム源とし
て用い、電子線の加速電圧を1 0 kV ,シリコン
基板に到達するビーム電流を5mAとし、ビームスポッ
ト径は300μmφとした。また、第4図(a)に示す
ように、X軸方向の往復運動のビーム走査は、X軸方向
の走査範囲(O≦X≦XQ)内において、x=XO//
2でv = vmax ( fcとえば20m/see
とした)とし、x = O、XoでV = Vminと
やや小さくして、かつアニールされた部分が1T″′′
“゜−”″゜゜”was−ii、ビーム照射領域でのX
軸方向の温度k均保つことにより、第4図(b)のよう
に単結晶f0嶋一一が
の成長界面30ノが直線状になるようにした。A4L First, as shown in Figure 30, for example, P type (100
) direction on the surface of the single crystal silicon substrate 201,
An S IO 2 film 202 with a thickness of about 1 μm is formed as a film, and a SiN film 203 is formed thereon. This SiN film 122=, ! +H'jW o s is formed to facilitate single crystallization of the silicon film in the later beam annealing process.
,0+:'. Furthermore, it is assumed that the desired elements have already been formed on the silicon substrate 201 through a well-known process.Next, as shown in FIG. 3(b), the surface of the SIN film 203 is A polycrystalline silicon film 204 is deposited. Next, as shown in FIG. 3(C), the silicon film 204 is annealed by scanning an energy beam from above. 500mm silicon substrate to prevent diffusion.
The temperature was raised to 'c', a continuous electron beam was used as a beam source, the acceleration voltage of the electron beam was 10 kV, the beam current reaching the silicon substrate was 5 mA, and the beam spot diameter was 300 μmφ. In addition, as shown in FIG. 4(a), the beam scanning of the reciprocating motion in the X-axis direction is performed within the scanning range (O≦X≦XQ) in the X-axis direction, where x=XO//
2 and v = vmax (fc for example 20m/see
), x = O, Xo and V = Vmin, which is slightly small, and the annealed part is 1T''''
"゜-""゜゜" was-ii, X in the beam irradiation area
By keeping the temperature k uniform in the axial direction, the growth interface 30 of the single crystal f0 was made to form a straight line as shown in FIG. 4(b).
:刀)らにビーム照射のy軸方向の位置によっても1・
1′・4
i14’jj軸方向の速度分布を適当に設定して、X軸
方i:ク′!1
jj7,像の温度の均一性を保った。またy軸方向の走
査速度はX軸方向のそれに比べて十分遅くし、かつy軸
方向走査範囲の中央部でその走査速度が速くなるように
これを制御することによ9、単結晶の成長界面30ノの
Y軸方向の移動速度を一定に保った。なおビーム走査の
軌跡は第4図(c)のようになった。: sword) and the beam irradiation position in the y-axis direction.
1'・4 i14'jj Set the velocity distribution in the j-axis direction appropriately, and the X-axis direction i:ku'! 1 jj7, the temperature uniformity of the image was maintained. In addition, the scanning speed in the y-axis direction is made sufficiently slower than that in the The moving speed of the interface 30 in the Y-axis direction was kept constant. The locus of the beam scan was as shown in FIG. 4(c).
本実施例では、以上の走査速度の制御を赤外線検出器に
よる温度センサーを用いてビーム照射地点の温度を検出
しながら電子計算機でビーム走査の最適速度を算出して
電子ビーム照射装置にフィードバックをかけるという方
法によシ行った。こうして、単結晶の成長方向を完全に
揃えることができ、壕だ単結晶の成長界面の速度も一定
にすることができ、この結果従来よりもさらに結晶粒径
の大きい多結晶や単結晶が実現された。In this example, the above scanning speed is controlled using a temperature sensor with an infrared detector to detect the temperature of the beam irradiation point, and an electronic computer calculates the optimum speed of beam scanning and provides feedback to the electron beam irradiation device. I went to that method. In this way, the growth direction of single crystals can be perfectly aligned, and the growth interface speed of trenched single crystals can be kept constant, resulting in polycrystals and single crystals with larger grain sizes than before. It was done.
以上の第3図(c)工程に次いで第3図(d)に示す1
A゜“一”一“゜“″“゜
たシリコン[ 2 0 4’ヲ/−eターニングしてフ
ィN,“′゛酸化膜′゜゛で分離された素子形成領域を
形成し、この素子領域にr−ト酸化膜206−・・を介
して例えば多結晶シリコンからなるダート・,:、
−1j′電゛1極207を形成し、ソース、ドレイン領
域1・L
Yr′o 8. ,? o9ヲ形成LテMOS } ラ
ン−)スタトI1 ・
t′=ylだ。次に第3図(.)で示すように全面を絶
縁膜210でおおった後、Atによる電極211〜21
3を形成して三次元に集積した半導体装置を完成した。1 shown in Fig. 3(d) following the above Fig. 3(c) step.
A゜"1"1"゜"""゜゜゜゜゜ヲゲ/-e turn to form an element forming region separated by a ``''゛oxide film''゛゛, and this element region A dirt electrode 207 made of, for example, polycrystalline silicon is formed through the r-to oxide film 206-..., and the source and drain regions 1 and L Yr'o 8., ? o9 Formation Lte MOS } run) stat I1 t'=yl.Next, as shown in FIG.
3 and completed a three-dimensionally integrated semiconductor device.
上記実施例では再結晶化したシリコン膜にMOS }ラ
ンジスタを形成したがC − MOS }ランジスタ、
パイポーラトランジスタ、ダイオードなどあらゆる素子
を形成できることはいうまでもなく、本発明を用いてこ
れらの素子を三次元的に配列することによシ、従来より
高集積、高性能、多機能な三次元集積回路を実現するこ
とが可能になった。なお、上記実施例では、ビーム走査
を第4図(C)に示すように往復ともアニールに利用し
たが、第1図のようなブランキング走査方式に本発明を
適用することもできる。また本発明の効果はシリコン以
外の半導体においても期待でき、これを組合せることに
より、−] ゾに従来の己憶口路 論理口路と共に表示
1・
j・ 路や感知回路などを同時に備えた多機能素子2
作りあげることができる。また、上記実施例起は電子ビ
ームを用いたが、他のエネルギビ−ムとして、レーザー
ビーム、赤外線および太陽光などの可視光なども考えら
れる。また、第2図(e)工程におけるAtによる電極
は他の金属でもかまわない。また、ビームの走査速度は
上記実施例においては最高20m/secの速さであっ
が、これ以上の速度でもかまわない。In the above embodiment, a MOS} transistor was formed in a recrystallized silicon film, but a C-MOS} transistor,
Needless to say, it is possible to form all kinds of elements such as bipolar transistors and diodes, and by arranging these elements three-dimensionally using the present invention, three-dimensional devices with higher integration, higher performance, and more functionality than ever before can be formed. It became possible to realize integrated circuits. In the above embodiment, beam scanning is used for annealing in both directions as shown in FIG. 4(C), but the present invention can also be applied to a blanking scanning method as shown in FIG. Furthermore, the effects of the present invention can be expected in semiconductors other than silicon, and by combining these, it is possible to simultaneously provide display circuits, sensing circuits, etc. in addition to conventional self-memory circuits and logic circuits. Multifunctional element 2
You can make it up. Further, although the above embodiments used an electron beam, other energy beams such as a laser beam, infrared rays, and visible light such as sunlight may also be used. Further, the At electrode in the step (e) in FIG. 2 may be made of other metals. Further, although the scanning speed of the beam is a maximum of 20 m/sec in the above embodiment, it may be faster than this.
その他この発明はその趣旨を逸脱しない範囲で種々変形
実施できる。In addition, the present invention can be modified in various ways without departing from its spirit.
第1図および第2図は従来のエネルギビーム走査方法を
説明するだめの図、第3図(a)〜(e)はこの発明の
一実施例の製造工程を示す断面図、第4図(a)〜(c
)は同実施例のエネルギビーム走査方法を説明するため
の図である。
201・・・単結晶シリコン板、2o2・・・5lo2
膜、2θ3・・・SiN膜、2o4・・・多結晶シリコ
ン膜、204′・・・単結晶シリコン膜、2o5・・・
フィールド酸化膜、206・・・ダート酸化膜、207
・・・ダート電極、208,209・・・ソース・ドレ
イン領域、210・・・絶縁膜、211〜213・・・
At電極、3θ1・・・単結晶の成長界面。
出願人 工業技術院長 石 坂 誠 〜第1図
第3図
s3図1 and 2 are diagrams for explaining the conventional energy beam scanning method, FIGS. 3(a) to 3(e) are sectional views showing the manufacturing process of an embodiment of the present invention, and FIG. a) ~ (c
) is a diagram for explaining the energy beam scanning method of the same embodiment. 201... Single crystal silicon plate, 2o2...5lo2
film, 2θ3...SiN film, 2o4...polycrystalline silicon film, 204'...single crystal silicon film, 2o5...
Field oxide film, 206... Dirt oxide film, 207
... Dirt electrode, 208, 209... Source/drain region, 210... Insulating film, 211-213...
At electrode, 3θ1... single crystal growth interface. Applicant: Makoto Ishizaka, Director of the Agency of Industrial Science and Technology ~Figure 1, Figure 3, Figure s3
Claims (1)
ギビームを連続的に照射しながら走査してその結晶粒径
を拡大させる方法において、前記エネルギビームの走査
速度を、走査範囲の中央部で端部より速くなるように制
御することを特徴とする半導体薄膜の製造方法。In a method in which a semiconductor thin film is deposited on a substrate and the semiconductor thin film is continuously irradiated with an energy beam while being scanned to enlarge the crystal grain size, the scanning speed of the energy beam is set to an end point at the center of the scanning range. 1. A method for manufacturing a semiconductor thin film, characterized by controlling the manufacturing speed to be faster than the current speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22759182A JPS59121825A (en) | 1982-12-28 | 1982-12-28 | Fabrication of semiconductor thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22759182A JPS59121825A (en) | 1982-12-28 | 1982-12-28 | Fabrication of semiconductor thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59121825A true JPS59121825A (en) | 1984-07-14 |
Family
ID=16863314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22759182A Pending JPS59121825A (en) | 1982-12-28 | 1982-12-28 | Fabrication of semiconductor thin film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59121825A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5745920A (en) * | 1980-09-02 | 1982-03-16 | Fujitsu Ltd | Forming method for semiconductor single crystal by energy beam emission |
-
1982
- 1982-12-28 JP JP22759182A patent/JPS59121825A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5745920A (en) * | 1980-09-02 | 1982-03-16 | Fujitsu Ltd | Forming method for semiconductor single crystal by energy beam emission |
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