JPS59117795A - Discriminating circuit in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To discriminate easily and surely a failed part after the package assembling of a memory provided with a redundancy circuit by connecting a fuse of a programmable element and a transistor (TR) of diode operation and impressing a reverse potential to the connection. CONSTITUTION:No current is conducted to the FETQ3, Q4 of diode connection connected to the fuse 4 of a discriminating circuit 3 at the normal operation when voltages at terminals VCC, VSS are at power supply voltage and ground voltage respectively, and no effect on an output buffer circuit is given because of the connection of the circuit 3. In impressing the reverse potential to the terminals VCC and VSS, when the fuse 4 is not blown, a node N1' reaches a prescribed voltage dividing potential by the FETQ3, Q4, and when the fuse is blown, the potential reaches a high potential depending on the FETQ4. When the potential depending on the discrimination of the presence of a failure via the bonding and section 2 is observed, the discrimination of a failed part is attained easily and surely even after the package assembling.

Description

[Detailed Description of the Invention] The present invention relates to a discrimination circuit in a semi-urban integrated circuit,
%, relates to an identification circuit having a redundant circuit and suitable for non-semiconductor memories.

Furthermore, in semiconductor IC memories, defective bits that do not function as intended may occur during the manufacturing process. Therefore, recently, spare memory cells or memory columns are provided, and when an address signal is input that causes the memory column containing the defective bit to be selected,
The spare memory cell 1 girl is the youngest girl and a hole redundant circuit is provided to switch the memory column. Therefore,
A memory provided with a redundant circuit is made to appear as a defect-free product from the outside.

However, general users are concerned about the reliability of defect-free products, so they are discriminating between non-defective products and defective products.
It is required that the product be easily identified from the outside after assembly is completed.

In such cases, conventionally, defect-free products and salvageable products are distinguished before being incorporated into the package, and salvageable products are subjected to salvage treatment before being incorporated into the package. We print and provide identification cards to users. however,
Such a sifting method using marks cannot be a fundamental solution to users' concerns about reliability.
Furthermore, in the current manufacturing process that involves forming a large number of ICs on a wafer at the same time, salvageable items are salvaged at the wafer stage. Therefore, at the stage of cutting out the wafer, we distinguish between defect-free products and repaired products.
It was necessary to incorporate it into the pan cage separately, and there was a disadvantage that it could not be identified in the f17 (state) when it was assembled in the pan cage.

This invention makes it possible to electrically distinguish whether a memory with a redundant circuit is a non-defective product or a salvageable product while it is embedded in a package. As the need for such identification increases, the purpose is to improve the reliability of products by making it easier for general users to identify them.

This invention will be explained below using the drawings.

FIG. 1 shows an embodiment of an identification circuit according to the present invention. In the figure, the output vanofer (b) is an output vanofa circuit commonly used in 1-half-body integrated circuits.
Line 1 is the supply voltage V, such as +5V. 0 and the tm frost pressure vS8 such as ground level.
O9FKTQ, consists of +, Q, and t. This VO day'
FET Q, 0. Data signals φd and φd of opposite phases are supplied to the gate terminal of Q2, and when they are turned on and off in a complementary manner, the output signal ut is output from the output node N1. In addition, when the chip is not selected, it is controlled by an appropriate control signal.
Both M08FETQg and Q2 are turned off, and the output is placed in a floating state, that is, in an impedance state.

2 is the output node N of the output vanofer circuit l.

This bonding panode 2 is connected to an output bin (not shown) by a bonding wire.

3 is an identification circuit which is added to the output vanofer circuit IVc. This identification circuit 3 is ``gold pressure ■''. It consists of an MO8FKTQ3 and a fuse element 4 connected in series between the output nodes N1 and L of the output sofa circuit 1, and an MO8FETQ4 connected between the output nodes N1 and L and the power supply voltage vss.

The gate terminal of MO8FKTQ, , is connected to the connection node N2 with the fuse element 4, and MO8FK
TQ, 4 is driven with its gate terminal connected to the power supply voltage ``ss.'' This allows MO8FETQ, 3 and Q, a, to be connected in the forward direction from the hot cloth 7 voltage vss to the vcc side. Let's use this as a female diode.

It works. The fuse element 4 is made of polysilicon or the like, and can be cut by flowing a relatively large amount of tj H between both terminals.

The output circuit configured as above is
When a voltage such as +5V is applied to the V88
In a normal case where the terminal is connected to the ground level, the identification circuit 3 is SRBk, MO8FETQ3
, Q, 4 are also in the off state when the fuse element 4 is not blown. MOB FET that acts as a diode Q3. Since the reverse voltage is applied to Q4, MOSF
ET Q3, Q, 4 K current will not flow. Therefore, in this case, a new r(discrimination circuit 3 added to the output circuit) not only does not function at all, but also has no effect on the output 7177 circuit 1.Therefore, in normal use, the output circuit 1 It operates exactly the same as before.

Next, a method of performing identification using the fctl separate circuit 3 added to the output circuit will be described.

In this case, connect the ■oo terminal to ground, and
By applying a positive voltage to the terminal, you can detect lightning, which is the opposite of that in normal use.
I'll make it into a rank relationship. In such a potential relationship, if fuse element 4 is not blown, MO8F'ETQ
4, Q, and 4 are both rendered conductive. Therefore, M
08FB T Q, 3. Fuse element 4. MO8FE
Current flows through TQ, 4, and the output nodes N, L are
MOS FET Q, 3. A split potential is generated so as to be determined by the ratio of the on-resistance of Q, 4 and the resistance of fuse element 4. In this case, ■The voltage applied to the SS terminal is ■ during normal use. . The voltage can be lower than the voltage (+5V) applied to the terminal.

On the other hand, the fuse element 4 in the identification circuit 3 is cut in advance,
, current is prevented from flowing through MOEIFETQ, 3. Therefore, in this case, the output node N
, l Suwachi Pad 2, MOB FETQ, 4
A potential determined only by 1C appears.

For example, if a resistor is externally connected to bat 2 and the output node 1' is pulled to the ground through this external resistor, the voltage applied to bat 2 is approximately 68.
It is brought to a potential close to the countervoltage.

Therefore, by observing the female output bin connected to this pad 2 from the outside using a tenuter or the like, it is possible to know whether the fuse element 4 is disconnected or not.

Generally, in a memory device equipped with a redundant circuit, for example, a voltage (voltage) is connected to ground, and a fuse element is connected between the terminal and the set point of the circuit. n-7 to be able to program the address of the defect hint by
An address storage circuit is provided.

If the memory has a defective pit, in order to repair it, it is necessary to appropriately cut the fuse element in the address storage circuit. Therefore, when performing relief processing by cutting off the fuse element, by cutting off the fuse element 4 in the identification circuit 3 at the same time, it is possible to set the identification circuit 3 without adding a completely new process. can.

Note that the IC memory to which the identification circuit of the above embodiment is applied is provided with a substrate potential generation circuit, and during normal use, the semiconductor substrate constituting the chip is raised to a negative voltage lower than, for example, ground level. It is ranked in the top spot in the weight class (■BB). This substrate potential generation circuit has a reverse potential between the Go terminal and the vss terminal.
In case c, the substrate is fixed, for example, at the ground level.

Therefore, as mentioned above, when ■CC is disproved, ■o. Terminal - ■
Even if the potential between the 8S terminals is reversed, MOS FETQ, 3.
PM between the source and drain regions of Q4 and the substrate
A forward voltage is applied to the parasitic diode due to the junction, and a current flows, so that a predetermined level is not generated at the node NI'.

Next, Figure Maki 2 shows another embodiment of the present invention. In this embodiment, the output nodes N and l are pulled to the ground level through the resistor R, which is externally connected to the pad 2. By adopting the configuration, MO8FE in the above embodiment
TQ, , is omitted. In this case, fuse element 4
) 4 o s F'ET is connected between T04 and the vS6 terminal.

In addition to the drilling and insertion positions of the fuse element 4, the life positions shown by broken lines A, B, and 0 in FIG. 2 can be considered.

Even if such an identification circuit is used, similarly to the first embodiment, by setting the potential between the voo terminal and the vss terminal opposite to that during normal use and detecting the level of the output bin, the heating element 4 can be detected. It is possible to determine whether there is a cut or not, that is, to distinguish between non-defective products and repaired products.

In addition, a proposal has also been made in which a high resistance element that can be laser annealed is used instead of a fuse element as the address storage circuit in the redundant circuit, and by lowering the resistance, the address of the defective bit can be set. It is. In this case, the whip separate circuit 3V in FIGS. 1 and 2]
It is preferable to use a high resistance element that can be annealed in place of the fuse element 4.

Since this invention is constructed as described above,
Without impairing the original functions of the IC, even those who have been forced into a package can easily electrically distinguish between non-defective products and repaired products.

That woman doesn't have the heart to identify the product in stages by cutting it out from Ueno. This has the effect of improving reliability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the identification circuit according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the present invention. l... Output Hanofa circuit, 2... Hong Taing Bano agent Patent attorney Bo 1) Li 9;: ,,,,, +(:
,,;,゛・,. 4-1.・＋Mu′

Claims (1)

[Claims] 1. At least a diode-connected transistor so that a reverse voltage is applied between the output canode of the output bag 77 circuit and the power supply voltage of one side of the circuit during normal use;
A programmable setting element is provided in the middle of the kth wiring that connects the transistor to the circuit, and by applying a potential opposite to that in normal use to the chemical pin,
An identification circuit in a semiconductor integrated circuit, characterized in that the output bin is divided so that different potentials are expressed depending on the state of the setting element.