JPS60113399A - Semicondutor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to inspect the presence or absence of the defect or the fusing of a fuse means by installing a electrode supplying the ground electric potential for the fusing to a source of MOSFET, by installing a switch MOSFET between an electrode and an electrode supplying the ground electric potential of a circuit and by measuring the resistance value of the fuse means through the MOSFET for the fusing, setting the switch MOSFET to ''off''. CONSTITUTION:The source of MOSFET 3 for the fusing is made common to the source of other same MOSFET for the fusing and is connected to an electrode P4 of supply the ground electric potential Vss' for the fusing. Namely, when a fuse means F0, etc., are fused, the electric potential is supplied to the electrode P4 by means of probing. Switch MOSFET Q15 and Q16 are in a serial shape installed between the electrode P4 and the electrode P5 supplying the ground electric potential Vss of the circuit. To the gate of these MOSFET Q15 and Q16, control signals phipow0 and phipowl are respectively impressed. Thus, the presence or absence of the defect or fusing of fuse means F0, etc., can be identified from the outside.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to semiconductor integrated circuit device technology.
For example, the present invention relates to a technique effective for a dynamic RAM (random access memory) provided with a defective address storage circuit for relieving defective bits.

[Background technology]

For example, in semiconductor memory devices such as dynamic RAMs, it has been considered to use a defective bit relief method in order to improve the product yield.

In order to adopt the defect bin tl & completed method, the semiconductor memory device is equipped with an address comparison circuit that compares an address (hereinafter referred to as a defective address) that indicates defect focus in the memory array with an address supplied to the semiconductor memory device. An address conveyor consisting of an address conveyor and a redundant memory array (spare memory array) are provided.

As a storage means for storing the defective address, a storage circuit as shown in FIG. 1 can be considered. This memory circuit stores the address of a defective memory cell, and fuse means F is used as the storage means. In order to blow out this fuse means F according to the above address, the following circuit is provided.

A logic circuit receiving the defective address signal aO is operated by the timing signal φp from the electrode P1. That is, the logic circuit is constituted by an inverter circuit that receives the load MO3FETQI and the defective address signal 10.

Furthermore, a fuse means F and a MOSFETQ3 are connected in series between the electrode P2 and the ground potential of the circuit, and the drain output of the MOSFETQ2 constituting the inverter circuit is applied to the gate of the MO3FETQ3. .

Further, in order to identify whether or not the fuse means F is blown, and to form complementary address signals aO, aO,
A launch circuit is provided. That is, a launch circuit is constituted by an MO3FET Q4 whose drain is connected to the fuse means F, and an MO3FET Q5 whose gate and drain are cross-connected to each other.

Note that current limiting means consisting of a resistor R2 is provided between the electrode P3 for supplying the power supply voltage of the circuit and the electrode P2 for blowing the fuse. Fuse means F (when programming whether to fuse or not, use the probe to
A voltage vCCr for fusing is directly supplied to the voltage vCCr.

The inventor's research has revealed that the following problems occur in such a memory circuit. That is, for example, when a polysilicon layer is used as the fuse means F, irregularities in shape or structure may occur due to manufacturing variations. What is the above shape abnormality?
The above-mentioned structural abnormality is caused by the occurrence of a chip in the middle of the polysilicon layer that constitutes the fuse means F, and this causes the resistance value to increase by more than 10 times the normal value. The layers are formed in the form of scales, and minute gaps are formed between the respective connection parts, which increases the resistance value as in the case where the above-mentioned shape abnormality occurs.

In the fuse means F having such a shape abnormality or structural abnormality, the blowing current flowing through the ON state of the MO3FET Q3 becomes small, so that complete blowing is not performed. Further, even if the fuse means F has no abnormality in shape or structure, a fusing failure may occur due to insufficient fusing current flowing due to defective characteristics of the MO3FETQ3, etc. As a result, if both ends are connected under a relatively large resistance value, the force,! (incomplete fusion).

In this way, when a writing failure occurs in the fuse means F, the defective bit 7 remains unswitched. Furthermore, in an incompletely fused state, the device may operate normally or malfunction, making it extremely difficult to detect this in a functional test. therefore,
Defective products end up on the market, are used in products, and may cause serious defects in actual operating conditions.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a memory circuit using highly reliable fuse means.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, the source of the MO3F'ET that blows the fuse means serves as an electrode that supplies a ground potential for blowing, and a switch MO3FET is provided between this electrode and an electrode that supplies the ground potential of the circuit.
By turning off the ET and measuring the resistance value of the fuse means via the blowing MO3FET, it is possible to inspect the fuse means for defects or blowouts.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment in which the present invention is applied to an address conveyor provided for repairing defective bits in a dynamic RAM. The address conveyor (redundant circuit) is composed of a plurality of unit address conveyors (unit redundant circuits) ACO to ACn. In the figure, only the unit address conveyor ACO is described in detail, but the remaining unit address conveyors have the same configuration as the unit address conveyor ACO.

Although not particularly limited, the MOSFE described in the examples below
T is N-channel enhancement type MOS F E
It is T.

The memory circuit that stores defective addresses is composed of the following circuit elements. Between the electrode P2 that supplies the voltage Vccr for blowing and the electrode P4 that supplies the ground potential Vss' for blowing, there is a fuse means FO and a MO3FE for blowing.
TQ3 is connected in series.

A load MO3FET is connected to the gate of this MO3FETQ3.
Q1 and drive MO3FET Q2. The output of the logic circuit composed of Q2' is applied. Above negative 1M03FETQ
1 is an electrode P to which a programming pulse φpO is supplied.
It is activated by the voltage supplied from 1. At the gate of the drive MO3FETQ2 of the above logic circuit,
A defective address signal aO is applied. In addition, drive MO5
A control signal φpoivo is applied to the gate of FETQ2°. Although not particularly limited, programming pulses φpo, φp1 and control signals dl powO+ e
In combination with powl, four types of defective address signals supplied from the same address terminal can be written to four sets of address conveyors, respectively.

That is, two sets of spare memory arrays can be provided for each of the defective addresses in the X system and the Y system, and switching between them can be performed. In the figure, only one set of address conveyors is shown as a representative.

A resistor R1 is provided between the electrode P2 and the power supply electrode P3 for supplying the power supply voltage Vcc of the circuit as current limiting means during reading of the fuse means FO or the like. Further, a high resistance resistor R3 is provided between the electrode P1 and the ground potential point of the circuit in order to prevent the electrode P1 from being in a floating state.

In order to identify whether or not the fuse means F is blown and to form complementary defective address signals aO and ao, the following circuit elements are provided.

MO3 whose gate and drain are cross-connected to each other
FETQ4. Q5 is configured in lunch form. Above M
The drain of OS F ETQ 4 is the fuse means FO
connected to. Although not particularly limited, this fuse means FO is formed by a polysilicon layer.

The drain of the MO3FET Q5 is provided with the following pull amplifier circuit, although not particularly limited, in order to pull up its high level output to the level of the power supply voltage Vcc.

Between the drain of MO3FETQ5 and the power supply voltage Vcc (the above-mentioned electrode P3), there is a Prechizi MO3FETQ7,
MO3FETQ8 is connected in parallel. The above MO
The conductance characteristics of 3FF and TQ4 are set to be relatively small in order to reduce power consumption. MO3FE above
'l'QB gate voltage is stored information according to whether or not the fuse hand vJtFO is blown, in other words MO3FE
According to the drain signal level of TQ5, MO3FET is set to low level or high level higher than power supply voltage Vcc.
The gate electrode side of MO8 with a capacitance of 0 is connected to the gate of Q8. Further, a timing signal φ is applied to the electrode side above this MO3O3 capacitor. It should be understood that this is a variable capacitance element in which when a high level higher than the threshold voltage on the M'O8 capacitor C capacitor is applied, an MO3 capacitor is formed, and when a low level lower than the threshold voltage is applied, an MO39i1 is not formed. 1 MO3O3 capacity above MO5FETQ50
MO3FETQ9 is provided to convey the drain signal. The gate of this MO3FETQ9 is connected to the electrode P
A power supply voltage Vcc supplied from No. 3 is constantly applied.

Although not particularly limited, the timing signal φ is the row address strobe signal R in the dynamic RAM.
An internal timing signal formed based on the AS is used.

Above MO3FETQ4. The storage information aQ, τ0 obtained from the drain of Q5 is the MO that constitutes the address comparison circuit.
Applied to the gate of 8FET QI O, Ql 1. These MO3FETQIO and Qll are connected in series, and the address signal aO° is supplied from the MO3FETQIO side and the address signal aO'' from the MOSFETQIO side in a complementary manner, and from their common connection point. This is to obtain a comparative output.

If the above stored information matches the address signal, the MOS FETQI that is in the on state due to the stored information
A low level match signal of address signal aO' or aOo is output through O or Qll.

On the other hand, if there is a mismatch between the stored information and the address signal, a high-level mismatch signal of the address signal aO' or aOo will be output through MO3FET QIO or Qll, which is turned on depending on the stored information.

Unit address conveyors ACn and the like provided for other address signals an are also constituted by similar storage circuits and comparison circuits.

The comparison output is input to a NOR gate circuit composed of MO3FETQI 2 to Ql3 and precharge MO3FET QI 4, and an address switching control signal ar is formed through this NOR gate circuit. In other words, when all stored information and address signals match, the low level output causes MO3FETQ12 to Ql
3 is turned off, and a high-level address switching control signal ar is generated.

In this embodiment, in order to be able to identify from the outside whether or not the fuse means FO is defective or fused,
The source of the MO3FET Q3 for blowing is shared with the source of another similar MOSFET for blowing (not shown), and is connected to an electrode P4 for supplying ground potential Vss' for blowing.

That is, when blowing out the fuse means FO, etc., the ground potential is supplied to this electrode P4 by probe ping. A switch MO3FETQI5 is connected between this electrode P4 and an electrode P5 that supplies the ground potential Vss of the circuit.
．． Ql 6 is provided in series configuration. And these MO3FETQ15. The control signal φpow (L φpowl) is applied to the gate of Ql6.

Note that the resistance R2 provided between the MO3FF, TQl 6 and the electrode P5 indicates the equivalent resistance of the wiring connecting the MO3FET Q16 and the electrode P5. This is because, for example, by providing the address conveyor close to the electrode P3 side that supplies the power supply voltage Vcc, the distance between the address conveyor and the electrode (ponding pad) that supplies the circuit ground potential Vss becomes longer. This is caused by

Next, the operation of this embodiment circuit will be explained.

When writing a defective address signal; 0 to the illustrated unit address conveyor ACO, the presence or absence of a defect in the fuse means FO, etc. is determined by the following procedure.

That is, the control signal φpow1 is set to a high level while the control signal φpowQ is set to a high level. This control signal φpo
Since MO3FET QI 5 receiving the low level of wo is turned off, terminals P4 and P5 can be electrically isolated. Furthermore, the MO5FETQ of the unit address conveyor ACO shown in the figure is
2'' is turned off, MO3FETQ3 etc. can be controlled according to the address signal 10 etc. Therefore, only the pulse φpO supplied to the electrode P1 is set to high level, and a voltage for resistance measurement is supplied from the electrode P3. For example, by setting only the address signal aO to a low level, only the MO3FET Q3 is turned on.As a result, only the fuse means FO is connected between the electrodes P2 and P4. The series combined resistance of FO and MO5FETQ3 can be known.

In this case, the reason why the electrodes P4 and P5 are electrically separated is as follows. That is, electrode P2
An equivalent combined resistance having a relatively small resistance value when viewed from the power source side of the entire circuit is connected between the electrode P5 and the electrode P5.

Therefore, when the electrodes P4 and P5 are connected, the fuse means FO, etc. and the equivalent combined resistance are in a parallel configuration, making it impossible to accurately measure the resistance value of the fuse means FO, etc.

If the fuse means formed of the polysilicon layer has no abnormality in shape or structure, it will have a relatively small resistance value of about 200Ω to 500Ω, but if it has an abnormality in shape or structure, the resistance will increase Since the resistance value is as large as the above, it can be identified. Hereafter, the address signal D1 to the address signal an are set to low level in order,
After detecting that there are no defects in the corresponding fuse means F1 to Fn, the electrode P
By supplying the fusing voltage Vccr to 2 and the defective address signal a (1-an), the fuse means FO to Fn are supplied according to the bit pattern.
It melts.

After that, in the same manner as above, each fuse means FO~
The resistance value of Fn is measured again to identify and confirm whether or not the predetermined fuse means is completely blown. What is the resistance value for the blown fuse means? (2) Therefore, it is easy to determine whether the fuse means is completely blown.

Hereinafter, when using the remaining three sets of address conveyors, they are selected by the combination of the two sets of pulses φp and the control signal φpo-, and the same operation is performed.

Note that when such a write operation has been completed, the control signals φpowO+φpoivl are both supplied with the power supply voltage Vcc of the circuit via the pull-up resistor, so the M
O3FETQ2° etc. and MO3FETQ15. Q16 is constantly on. Therefore, even if the parasitic capacitance formed by the electrode P4 is charged up due to undesired electrostatic coupling or ions, these MO3FETs Q15. It is pulled out to the ground potential point of the circuit via Q16. As a result, the electrode P
4 is placed in a floating state to prevent electrostatic damage due to charge-up to the parasitic capacitance.

〔effect〕

+11 For blowing fuse f4 (7) By separating the electrode that supplies the source potential of the MOSFET and the ground potential of the circuit, the resistance value before and after blowing the fuse means can be measured, so the shape of the fuse means Or structural defects can be easily identified. Therefore, since it is possible to reliably write and read defective addresses,
The effect is that highly reliable defective bit relief can be realized.

(2) Determining a defect in the fuse means can be configured with an extremely simple circuit, since it is only necessary to provide a switch MO3FE'l'' between the electrode that supplies the ground potential for blowing the fuse and the ground potential point of the circuit. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the electrode P4
may be completely electrically separated from the ground/earth potential point of the circuit. However, in this case, since there is a risk of electrostatic damage as described above, a high resistance that does not affect the resistance measurement of the fuse means, in other words, a sufficiently large resistance value compared to the resistance value of the fuse means. It may be connected to the ground potential point (P5) of the circuit by a resistor of a certain value.

Furthermore, in the circuit shown in FIG. 2, the dynamic '7 pull-up circuit can be modified in various ways.

Further, the circuit for determining whether or not the fuse means is blown and forming a complementary pair of defective address signals may utilize a flip-flop circuit or the like.

Furthermore, the number of address conveyors can be increased or decreased as needed. In the embodiment, one switch MO3FET is provided between the electrodes P4 and P5, and the control signal φpow(Lφpoy1 is combined with AND(A
ND) It may be controlled by a signal passed through a logic circuit. In addition to the polysilicon layer, the fuse means used may be of any type as long as it can be blown by a current generated by a MOSFET.

Furthermore, although the circuit of this embodiment was constructed with an N-channel enhancement type MO3FET, it may be constructed with a P-channel enhancement 9M03FET or a CMO3 (complementary type MO8) circuit.

[Application field]

The above explanation mainly focuses on the dynamic type RA, which is a technical field based on the invention made by the inventor of the present application.
Address conveyor for defective bit relief in M (
Although the present invention has been described with reference to a case where it is applicable to a redundant circuit, it is not limited thereto, and the present invention can be widely used in semiconductor integrated circuit devices that utilize fuse means as storage means.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a defective address storage circuit considered prior to the present invention, and FIG. 2 is a circuit diagram showing an embodiment in which the present invention is applied to an address conveyor.

Claims (1)

[Claims] 1. Fuse means having one end connected to a voltage supply electrode;
A fuse blowing MOS FET with a drain connected to the other end of the fuse means, and a fuse blowing MOSFET having a drain connected to the other end of the fuse means.
The logic circuit that forms the control signal to be supplied to the gate of the S FET and the source of the fuse blowing MOS FET are provided in common to supply the ground potential for fuse blowing, and the ground potential point of the circuit is electrically connected to the ground potential point for the fuse blowing. 1. A semiconductor integrated circuit device comprising: electrodes that can be separated from each other. 2. Electrical separation between the electrode that supplies the ground potential for fuse blowing and the ground potential of the circuit is achieved using a switch MOS F.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device uses ET. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the fuse means is formed of a polysilicon layer. 4. The above semiconductor integrated circuit device is a dynamic RAM.
4. A semiconductor integrated circuit device according to claim 1, wherein said fuse means has an address of a defective memory cell written therein.