JPS59114949A - Digital multi-frequency receiving system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a digital signal multi-frequency receiver and to shorten the discriminating time of the frequency component, by providing a means which measures the intervals between adjacent coding changing time points of the digital signal and the changing points of the digital signal at the optimum value time point of an envelope curve. CONSTITUTION:The coding changing point of a digital signal is detected by the 1st means containing a multiplier 12 connected to an input terminal 1 and a delay circuit 13. Then the interval between the detected adjacent coding changing points is measured by the 2nd means containing a counter circuit 15. The 3rd means is provided with the circuit 13, a subtractor 14, a comparator 17, a threshold value circuit 18, a holding circuit 19, a subtractor 20, a delay circuit 21, a comparator 22 and a threshold value circuit 23 respectively. This 3rd means detects the optimum value time point of an envelope curve of the digital signal. Then the 4th means containing a calculating circuit 24 measures the adjacent extreme value time points. The double frequency of the digital signal component is discriminated from the measured values of the 2nd and 4th means. Thus the discriminating time can be shortened with a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a digital multi-frequency receiver, and more particularly to a digital multi-frequency reception method that can shorten the time required to identify three frequencies included in a received digital signal.

(b) Background of the Technology A multi-frequency signal system that uses a combination of three frequencies within a plurality of predetermined frequencies is widely used as an interoffice signaling system for automatic exchanges. In digital exchanges, this type of multi-frequency signal is also sampled at a predetermined period (for example, 125 microseconds), further quantized, and converted into a digital signal such as a PCM code before being transmitted. A digital multi-frequency receiver is required.

(C) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional digital multi-frequency reception system in this type of digital multi-frequency receiver. In FIG. 1, the digital signal arriving at the input terminal l is generated by a sine kernel function 5in(
2πfnT) (where f is the frequency to be identified) is determined by the multiplier 3, and the product by the cosine kernel function cos(2πfnT) generated by the kernel function generation circuit 4 is determined by the multiplier 5. The signal is transmitted to calculation circuits 6 and 7. Accumulating circuits 6 and 7 accumulate the transmitted multiplication results, and transmit the accumulated results for each calculation interval NT determined by the frequency characteristics required of the digital multi-frequency receiver to multipliers 8 and 9. . Multipliers 8 and 9 square the accumulated results transmitted for each calculation interval NT, and then transmit the result to adder 10. Adder 10 adds the squared results transmitted from multipliers 8 and 9, and outputs the result from output terminal 11 as a discrete Fourier transform output.

By comparing the discrete Fourier transform output with a predetermined reference value, the presence or absence of the frequency f is identified from the digital signal.

As is clear from the above explanation, in conventional digital multi-frequency reception systems, kernel function generation circuits 2 and 4, accumulation circuits 6 and 7, etc. are required in order to obtain the required discrete Fourier transform output. In addition, the time required to identify the component frequencies of the digital signal is determined by the calculation interval NT, which has the disadvantage that it cannot be shortened freely.

An object of the present invention is to eliminate the drawbacks of the conventional digital multi-frequency reception system as described above, and to realize a means for shortening the identification time of component frequencies of digital signals without impairing the economic efficiency of the digital multi-frequency receiver. It is in doing.

(e) Structure of the Invention This object is to provide a digital multi-frequency receiver that receives a digital signal obtained by sampling and quantizing a signal having arbitrary three frequencies among a plurality of predetermined frequencies. a first means for detecting a sign change point; a second means for measuring an interval between adjacent sign change points detected by the first means; and a second means for detecting an extreme point of an envelope of the digital signal. and a fourth means for measuring the interval between adjacent extreme point points detected by the third means, and the measured values of the second and fourth means are used as components of the digital signal. This is achieved by identifying three frequencies.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a digital multi-frequency reception system according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, the first means is composed of a multiplier 12 and a delay circuit 13, the second means is composed of a counting circuit 15, the delay circuit 13, a subtracter 14, and a comparison circuit 17. , the third means comprising a threshold circuit 18, a holding circuit 19, a subtracter 20, a delay circuit 21, a comparator circuit 22 and a threshold circuit 23, and the fourth means comprising a counting circuit 24. be done. A digital signal arriving from input terminal 1 is transmitted to multiplier 12, delay circuit 13 and subtracter 14.

After the delay circuit 13 gives a delay of one sampling period T (125 microseconds in the example) to the transmitted digital signal,
It is transmitted to multiplier 12 and subtractor 14. The multiplier 12 multiplies the digital signal directly transmitted from the input terminal 1 and the digital signal transmitted from the delay circuit 13 one sampling period T ago, and calculates the sign bit (most significant bit) of the multiplication result. It is transmitted to the reset terminal R of the counting circuit 15. The sign bit becomes negative if the digital signal changes sign during one sampling period. The occurrence of a negative sign bit therefore indicates the time of a sign change of the digital signal. The counting circuit 15 is incremented by a predetermined clock signal, and is reset every time a negative sign bit is input to the reset terminal R. The maximum count value of the counting circuit 15 thus indicates the interval between adjacent sign change instants of the digital signal. Next, the subtracter 14 calculates the difference between the digital signal directly transmitted from the input terminal 1 and the digital signal transmitted from the delay circuit 13 one sampling period T ago, and transmits the subtraction result to the comparison circuit 17. . The comparison circuit 17 compares the subtraction result transmitted from the subtracter 14 with the dark value generated in one day by the dark value circuit, and transmits a clock signal to the holding circuit 19 when the subtraction result becomes less than or equal to the threshold value. The dark value is set such that the time of generation of the clock signal indicates the time of the extreme value of the digital signal. The holding circuit 19 holds the digital signal transmitted from the input terminal 1 when the clock signal is transmitted from the comparison circuit 17 . That is, the holding circuit 19 holds the extreme value of the digital signal. Holding circuit 19 transmits the extreme value of the held digital signal to subtracter 20 and delay circuit 21 . The delay circuit 21 applies a predetermined time delay to the extreme value of the digital signal transmitted from the holding circuit 19 and then transmits it to the subtracter 20 . The subtracter 20 calculates the difference between the extreme value of the digital signal transmitted from the holding circuit 19 and the digital signal transmitted from the delay circuit 21 a predetermined time ago, and transmits the subtraction result to the comparison circuit 22 . The comparison circuit 22 includes a subtracter 2
The subtraction result transmitted from 0 is compared with the dark value generated by the dark value circuit 23, and when the subtraction result becomes less than the threshold value, an extreme value detection signal is transmitted to the reset terminal R of the counting circuit 24. The dark value is set such that the time point at which the extreme value detection signal is generated indicates the time point at which the extreme value of the envelope of the digital signal is the extreme value. The counting circuit 24 is incremented by a predetermined clock signal, and is reset each time the extreme value detection signal is input to the reset terminal R. The maximum count value of the counting circuit 24 thus represents the interval between adjacent extreme points in the envelope of the digital signal. On the other hand, a digital signal whose component frequencies are two frequencies f1 and f2 is expressed by the +11 formula.

s in (2πf 1nT)+s in (2πf
2nT+φ)...(1) The +11 equation is further transformed as shown in equation (2).

2s in (yc (f 1+f 2) nT+φ/
2]xcos (π(f 1-f 2)nT-φ/2
) ・(2) In equation (2), the fundamental frequency of the digital signal is (f1 + f 2)/2, and the frequency of the envelope line is (
fl−f2)/2. In Figure 2,
The maximum count value of the counting circuit 15 outputted from the output terminal 16, that is, the interval between the sign change points of the digital signal corresponds to a half cycle of the fundamental frequency (f l + f 2) /2, and the maximum count value outputted from the output terminal 25 The maximum count value of the counting circuit 24, that is, the interval between adjacent extreme points of the envelope of the digital signal corresponds to a half period of the envelope frequency (fl-f2)/2. Therefore, the component frequencies fl and f2 of the digital signal can be easily determined from the rainfall total count values output from the output terminals 16 and 25.

As is clear from the above description, according to this embodiment, the half cycle of the fundamental frequency (f1+f2)/2 and the envelope frequency (fl-f2)/2 output from the output terminals 16 and 25, respectively, are Due to the half-cycle, the component frequencies f1 and f2 of the digital signal can be immediately determined, and the identification time is significantly reduced. Moreover, since the kernel function generating circuits 2 and 4 and the accumulating circuits 6 and 7 as shown in FIG. 1 are not required, the digital multi-frequency receiver can also be made economical.

Note that FIG. 2 is merely one embodiment of the present invention, and the configurations of the first to fourth means are not limited to those shown in the figure (although many other modifications may be considered). However,
In either case, the effects of the present invention remain the same.

(g) Effects of the Invention As described above, according to the present invention, in the digital multi-frequency receiver, the time required to identify component frequencies of a digital signal is significantly shortened, and the economical efficiency of the digital multi-frequency receiver is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional digital multi-frequency reception system, and FIG. 2 is a diagram showing a digital multi-frequency reception system according to an embodiment of the present invention. In the figure, 1 is an input terminal, 2 and 4 are kernel function generation circuits, 3.5.8.9 and 12 are multipliers, 6 and 7 are accumulation circuits, 10 is an adder, and 11.16 and 25 are outputs. terminals, 13 and 20 are delay circuits, 14 and 20 are subtracters, 15 and 24 are counting circuits, 17 and 22 are comparison circuits, 18 and 23 are threshold circuits, 19 is a holding circuit,
shows.

Claims (1)

[Claims] In a digital multi-frequency receiver that receives a digital signal obtained by sampling and quantizing a signal having arbitrary three frequencies among a plurality of predetermined frequencies as components, a first means for detecting a sign change point of the received digital signal. a second means for measuring the interval between adjacent sign change points detected by the first means; a third means for detecting an extreme point in the envelope of the digital signal; and a fourth means for measuring the interval between adjacent extreme point points detected by the digital signal, and the three frequencies to be the components of the digital signal are identified from the measured values of the second and fourth means. Digital multi-frequency reception method.