JPS59112737A - Digital speech interpolation device - Google Patents

Abstract

PURPOSE:To remove a click noise due to the level difference of a reproduced sound signal by outputting a significant sound PCM signal which is transmitted intermittently in a significant sound section at a reception part, and inserting a low noise with a DC pedestal in a pause section. CONSTITUTION:The reception part of a digital speech interpolation device DSI device is provided with an insertion part 19 for the low noise with the DC pedestal. The insertion part 19 inputs an individual significant sound PCM signal (a) which is transmitted intermittently to an accumulator 39, which accumulates the signal (a) at a specific position specific numbers, so that the accumulated value is held in a register 42 for a specific period. The output of the register 42 is divided by the expected number of times at a mean value circuit 43 to calculate the mean DC pedestal level. The signal (i) is added 44 to a low noise (b) from a low noise generator 17 to generate the low noise (j) with the DC pedestal, which is inputted to a switch 37. The switch 37 inserts and couples the signal (a) in the significant section or signal (j) in the pause period under the control of a sound detection signal (d) to reproduce a continuous sound PCM signal C.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes the statistical properties and crowd effect of conversational voices on the telephone to digitally interpolate only significant voice sections in a conversation with pause sections. The present invention relates to a digital speech interpolation device (hereinafter referred to as DSI) for highly efficient transmission.

Generally, a DSI device transmits m input channels (POM channels) through n transmission channels (DSI channels), and if m>60, then n=m/
It is known that transmission can be carried out over two channels ('''-).

To explain the general form of a DSI device, significant audio information is detected for each channel from the input PCM channel by the action of an audio detector on the transmitting side, and only the significant audio information is allocated to the DSI channel. It also transmits information.

On the receiving side, the allocation information is first decoded and each significant voice information transmitted on the DSI channel is distributed to the destination PCMf-yang-il. At this time, a silent signal is inserted into the pause section where no signal is transmitted, and the signal is reproduced as a continuous signal.

Usually, in order not to spoil the naturalness of the conversation,
Inserting low-level noise is being done.

Generally, in a PCM encoding/decoding device (CODEO) that encodes an analog signal with PC1φ.

The zero level of the voice does not necessarily match the zero level of the PCM code. That is, the PCM'C0DEC has some DC pedestals.

P' having the above DC pedestal in a DSI device
A problem when performing DSI processing on CM signals is the malfunction of the audio detector, and in conventional DS processing equipment actually used, a DC pedestal removal circuit is installed in the audio detector to prevent this malfunction. It is well known that it has been established.

However, although the conventional method takes measures against the voice detector in the transmitter, it does not take any DC countermeasures in the receiver.
No countermeasures against C pedestal were taken. For this reason, a DSI device that attempts to reproduce a continuous PCM signal by inserting a silent signal into significant audio information and splicing the signals has the following drawbacks.

In other words, since no consideration is given to the DC pedestal in the receiving section, a zero level is inserted into the silent signal that combines significant audio information, and when there is almost no DC pedestal in the input PCM signal of the transmitting section. Although this is not a problem, if the DC pedestal is large, a large C level step will occur at the connection point between the sound section and the silent section. This DC level difference causes a large waveform distortion, and also causes a large auditory defect such as audible click noise.

As mentioned above, in the conventional DSI device.

As long as a PCM signal having a DCC pedestal is handled, there is a drawback that deterioration of hearing sensation cannot be sufficiently prevented.

Therefore, an object of the present invention is to prevent the reproduced PCM signal from being affected by the Do pedestal even when a DSI device performs DSI processing on a P Olvi signal having a DC pedestal, and to provide a connection point between a significant voice section and a silent section. An object of the present invention is to provide a DSI device that can make the DC level difference extremely small.

In order to achieve the above object, the present invention adds means for level correction.

In other words, according to the present invention (=), by using the statistical properties of conversational voices and the crowd effect in telephone conversations, only significant voice sections in the conversation are digitally interpolated ('''-interpolation) from the transmitter into the pause sections. In a digital speech interpolation device that transmits data to a receiving section with high efficiency, the receiving section is provided with a predetermined position for each significant audio PCM signal that is transmitted in a piecemeal manner for a predetermined number of times. an accumulator that performs calculation, a register that holds the output of this accumulator for a predetermined period of time, and a DC pedestal that divides the cumulative value of the output of this register a predetermined number of times and calculates the average value. A generation circuit, a low noise generation circuit that generates low noise digitally in advance, and the output of this low noise generation circuit and the output of the average value calculation circuit are added together, and Do
an adder with a pedestal that generates low noise; the output of the adder is input to one input terminal; the significant audio PCM signal is input to the other input terminal; Under the control of the detection signal, the switching device operates to output the significant audio PC1M signal that has been transmitted in fragments in the active period, and to output the generated low noise with the DQ pedestal in the idle period. A digital speech interpolation device is obtained which is characterized in that a low noise insertion means with a DC pedestal is provided.

Next, a detailed description will be given with reference to the drawings.

FIG. 1 is a block diagram of a DS terminal station device according to an embodiment of the present invention, in which (A) shows the structure of a transmitter and (B) shows the structure of a receiver.

In the transmitter shown in FIG. 1(8), PCM signal sequences are applied to the four signal terminals 1. This PCM signal train is PcM
A line interface circuit 2 is provided, further multiplexed, and added to a delay circuit 3 and a voice detection circuit 4.

The audio detection circuit 4 detects the presence or absence of audio for each channel from the input multiplexed PC1M signal. Information on the presence or absence of voice is added to the allocation control circuit 5 as a voice detection signal. In the allocation control circuit, significant audio information is allocated to the DS channel to be transmitted. This allocation information is sent to the transmission buffer memory 6 via the signal line 51 together with the destination PCM channel number, and at the same time
It is sent to the allocation information encoding circuit 7 via the. .

On the other hand, the PCM signal train applied to the delay circuit B is time-adjusted including the processing time required by the audio detection circuit 4 and the allocation control circuit 5, and is added to the transmission buffer memory B. In the transmission buffer memory 6, the PCM channel number assigned to the DS channel by the 1 assignment control circuit 5 is written to the memory address corresponding to the DSI channel number. Reading from the transmission buffer memory 6 is D.
The signals are sequentially read out according to the SI channel frame configuration and applied to the multiplexing circuit 8.

The allocation information encoding circuit 7 converts the allocation information, which is a pair of the destination PCM channel number and the DSI=channel number received from the allocation control circuit 5, into a transmission line code and sends it to the multiplexing circuit 8. Add.

The multiplexing circuit 8 multiplexes the DSI signal read from the transmission buffer memory 6 and the allocation information from the allocation information encoding circuit 7, and inserts a DSI frame synchronization signal from a circuit not shown to create a transmission line frame. The configuration is established and sent to the transmission DSl line interface circuit 9.

The DSI line interface circuit 9 converts the signal into a DSS multiplied signal transmission line code, and sends it out to the transmission line via the signal terminal 10.

In the receiving section of FIG. 1(B), the DS engineering transmission line code input manually from the signal terminal 11 is applied to the receiving DSI line interface circuit 12, and in this line interface circuit, the transmission line code is converted into the equipment internal code. along with being converted to.

After establishing frame synchronization, 1 assignment information is added to the subsequent circuit 15 and the delay circuit 14.

In the allocation information decoding circuit 16, allocation information is extracted from the DSI signal, decoded, and sent to the two-way distribution control circuit 15.

The distribution control circuit registers the P'CM channel number of the connection destination based on the reception assignment information, and controls the reception buffer memory circuit 16.

The reception buffer memory circuit 16 receives the DSI signal time-adjusted by the required time in the delay circuit 14, and stores the data in the memory address corresponding to the connected PCM channel number based on the distribution control information from the distribution control circuit 15. written. The fragmentary audio PCM signal a is read out in the order of channel numbers based on the POM frame structure and is applied to the low noise insertion circuit 18.

The configuration of the low noise insertion circuit 18 with DC pedestal will be described in detail later, but in this circuit, the low noise from the low noise generation circuit 17 is transmitted piecemeal for each POM channel from the reception buffer memory 16. A continuous audio POM signal G is reproduced by inserting the incoming signal a between significant audio PCM signals. The low noise generation circuit 17 and the low noise insertion circuit 18 together form a low noise insertion circuit 19 with a DC pedestal. The reproduced audio PCM signal is sent to the receiving PCM inter 7141 circuit 20. In this receiving PCM interface circuit, the multiplexed PCM signal train is rearranged into a connected PCM signal train, converted into a transmission line code, and outputted to four signal terminals 21.

FIG. 2 is a diagram showing the configuration of the above-mentioned low noise insertion circuit with DC pedestal.

FIG. 6 shows a waveform time relationship diagram of the device of FIG. Referring to FIGS. 1 to 3 below, a fragmentary significant audio PCM signal a read out from the reception panzer memory 16 based on distribution control information from the distribution control circuit 15 is input to the signal terminal 61. Ru. However, in this figure, analog waveforms are used for convenience of explanation. The signal terminal 62 has the corresponding P
An audio detection signal d of the OM channel (detector not shown) is input. A gate pulse e created based on the above voice detection signal d is input to the signal terminal 66. A clock pulse f is input to the signal terminal 64 (=. A reset pulse g is input to the signal terminal 65.

Added. A feedback signal from the register 38 is applied to the other input terminal of the adder 66.
The adder 36 and the register 68 constitute an accumulator 59. The gate circuit 40 is controlled so that the clock to the register 8 is supplied as a signal only during the period of the gate pulse e.

Therefore, the audio POM signal a is the section of the gate pulse e, that is, the last section of the audio PCM signal.
is transmitted to register 6 by reset pulse g.
The contents of 8 are cleared. The value is held in the register 42 until the next accumulation result is transmitted.

The cumulative result of the register 42 is added to the average value circuit 43,
In this average value circuit, the accumulated results are averaged to determine the average DC pedestal level l. Calculation of the average DC pedestal level requires only a simple digit shift as long as it matches the number of accumulations by the accumulator. That is, for 2M accumulations, shifting by M digits is equivalent to performing 2M operations, so the average value circuit becomes very simple.

The average DC pedestal level 1 is applied to the adder circuit 44, where it is added to the low noise signal from the low noise generation circuit 17 to generate the low noise level J with DC pedestal, which is applied to one input terminal of the switch 37. In the switch 37, the voice PCM signal a from the signal terminal 31 and the low noise J with DC pedestal are switched under the control of the voice detection signal d from the signal terminal 62, and thus the meaning that has been transmitted in a piecemeal manner is A low noise J with a DO pedestal is inserted and coupled to the audio PCM signal a in its rest period.

A continuous audio PGM signal C is reproduced.

By adding the DC pedestal estimated from the received PCM signal as described above, click noise and waveform distortion due to level differences in the reproduced audio signal are eliminated.

Therefore, in the DSI device according to the present invention, audible deterioration can be extremely reduced and high-quality audio transmission can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a DS equipment, which is an embodiment of the present invention, divided into a transmitting section (A) and a receiving section (B).
FIG. 2 is a block configuration diagram of a low noise insertion section with DC pedestal used in the device (1) of the present invention, and FIG. 6 is a waveform time relationship diagram for explaining FIG. 2. Explanation of symbols: 12 is a receiving DSI Line interface circuit, 1 is an allocation information decoding circuit. 14 is a delay circuit, 15 is a distribution control circuit; 16 is a reception buffer memory, 17 is a low noise generation circuit. 18 is a low noise insertion circuit with DC pedestal, 19 is a D O
20 is a receiving PCM interface, 66 is an adder, 67 is a switch, 68 is a register, and 39 is an accumulator. 41 is a register, 42 is an average value circuit, 46 is an addition circuit,
a is a signal that has been transmitted in fragments; 7b is a low noise signal; C
are each broadcasting a continuous audio POM signal. °te no\ノ
()
- Sweet Figure 2 7b □ Figure 3

Claims (1)

[Claims] 1. A transmitting unit that utilizes the statistical properties of conversational speech on the telephone and the large group effect to digitally interpolate significant voice sections in a conversation into pause sections. In a digital speech interpolation device that transmits signals from a voice to a receiving section with high efficiency, a predetermined position is predetermined for each significant voice POM signal that is transmitted and sent in fragments to the receiving section. An accumulator that accumulates the number of times, a register that holds the output of this accumulator for a predetermined period, and a DC that divides the cumulative value of the output of this register by a predetermined number of times and calculates the average value. a pedestal generating circuit, a low noise generating circuit that digitally generates low noise in advance, and an adder that adds the output of this low noise generating circuit and the output of the average value calculation circuit to generate low noise with a DC pedestal. , the output of this adder is input to one input terminal, the significant voice POM signal is input to the other input terminal, and the voice interval is determined by controlling the voice detection signal representing the voice interval and the pause interval. A Do pedestal low noise insertion means is provided, which has a switch that operates to output the significant voice POM signal that has been transmitted in fragments and output the generated DC pedestal low noise during the pause period. A digital speech interpolation device characterized by: