JPS59110218A - Generating circuit of multivalued impulse response waveform - Google Patents

Abstract

PURPOSE:To simplify the constitution of a response waveform generating circuit and to generate an impulse response waveform by composing a filter for base- band limitation of a digital circuit. CONSTITUTION:A signal 2Xfb from an input terminal 10 is converted by a two- sequence converting circuit 12 into two sequences of binary codes, which are transmitted to sequence transmission lines 101 and 102 for binary codes I a and IIa. The binary codes transmitted by the lines 101 and 102 are converted into Gray codes by a binary/Gray converting circuit 13, whose outputs are inputted to (x)-bit storage circuits 14a and 14b. Those circuits 14a and 14b store an ROM15 with information of a multivalued waveform corresponding to 2<2xx> kinds of bit patterns which can be observed. The information stored in the ROM15 is read out by an (y)-bit binary counter 16 connected to an input terminal 19 for a clock fkX2<y> and converted by a D/A converter 17 into an impulse response waveform in the form of an analog value. Then, the response waveform generating circuit consists of the digital circuit and its constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing circuit in digital communication, and particularly to a multi-value impulse response waveform generation circuit comprising a digital circuit as a baseband band limiting filter for multi-value transmission.

Conventionally, as this type of impulse response waveform generation circuit, a binary impulse response waveform generation circuit as shown in FIG. 1 is known. To explain this type of conventional circuit with reference to FIG. 1, first, the bit rate synchronized with the clock pulse fCL
When an input signal of ta (fa=fcL) is input to input terminal 1, that input signal is continuously stored in the next stage n-bit storage circuit (n-bit shift register) 2, and the stored information is transferred to n outputs. It is outputted from the terminal DO'Dn-1 to the address terminal Am-An+m-1 of the next stage ROM3 in synchronization with the clock pulse fCL. ROM3 has n
2m pieces of information on 20 types of binary impulse response waveforms corresponding to bit patterns of bits are stored as sampling values obtained by dividing one symbol period 1/fa into 2m pieces for each type. Therefore, 2m pieces of waveform information corresponding to the state of the n-bit storage circuit 2 are sequentially read out by the m-bit binary counter 5 until the state of the n bits changes at the next timing of the clock fCL. This read information is converted into an analog quantity by the digital-to-analog conversion circuit 6, and output from the output terminal 7 as a binary impulse response waveform. Note that 4 in the figure is an input terminal to which a clock pulse 2m times the clock pulse fCL for synchronizing the operation of the entire circuit is input. FIG. 2 is an eye pattern diagram based on a binary impulse response waveform obtained by the circuit configuration shown in FIG.

However, as the need for multi-value transmission increases with the recent increase in the amount of information, so-called multi-value impulse response waveform generation circuits other than the above-mentioned binary have not yet been realized.

In view of the above-mentioned circumstances, an object of the present invention is to provide a multi-value impulse response waveform generation circuit using a digital circuit with a baseband band limiting filter for multi-value transmission. To explain, there is a multi-sequence conversion circuit that converts an input signal for one-sequence transmission with a bit rate of 1×fb to a ↓-sequence transmission with a bit rate of fb, and a multi-sequence conversion circuit that converts the input signal of one-sequence transmission with a bit rate of 1×fb into a ↓-sequence transmission signal with a bit rate of fb. An X-bit shift register that must be observed one by one! A focus accumulation circuit inserted into each stream of single-series transmission, and a binary/bit accumulation circuit inserted between the bit accumulation circuit and the multi-sequence conversion circuit to convert the binary code into a gray code.
A gray conversion circuit and a multi-value (
2f value) RO that stores impulse response waveform information
M, a binary counter for reading out the information in the ROM, and a digital/analog (D) for converting the information read out by the binary counter into an analog quantity.
/A) conversion circuit. Accordingly, if the outputs 1×X of the bit storage circuits of the
-1 when viewed from
By sequentially observing xz signals bit by bit,
X pieces of 2f value signals can be continuously observed. Also R8M171j, 2i x 8 seeds. 2”iW
y'yvxfi5g waveform information is stored as 2y sampling values divided into 2y for each symbol period 1/fb for each type. Information can be read out with an X-bit binary counter. This read information is converted into a second-value (multi-value) analog impulse response waveform by a D/A conversion circuit and output.

Hereinafter, as an embodiment of the multilevel impulse response waveform generating circuit according to the present invention, a circuit for generating a four-level impulse response waveform will be described in detail with reference to FIGS. 3 to 7.

Figure 3 is a four-level impulse response waveform generation circuit diagram.
10 is an input terminal for a signal with a bit rate of 2×fb, 12 is a two-series conversion circuit, 13 is a binary/gray conversion circuit consisting of an exclusive OR element, 14a and 14b are each a gray code Ib, a sequence transmission line 201, and a gray code I
An X-bit storage circuit from an X-bit shift register used to observe changes in the signal on the Ib series transmission line 202, and a ROM that stores four-value impulse response waveform information of a H-S band band limiting filter, 22Xx types of waveform information are stored. 1
6 is an X-bit binary counter for reading out the information stored in the ROM 15; 17 is a D/A conversion circuit for converting the information output from the ROM 15 into an analog quantity; 18 is an output terminal for a four-value impulse response waveform of the analog quantity; 19 is an input terminal for a clock 2y times the clock f' that synchronizes the operation of the entire circuit, 101 is a binary code ■8 series transmission line, 102 is a binary code ■8 series transmission line, 301 is a clock fk transmission line ,
302 is a clock 2Xfk transmission line, and 303 is a clock fk×2y transmission line. Furthermore, the transmission line 20
1 (Ib), 202 (IIb), and 4
The value level relationship is as follows.

(TIb, Ib) - (0, O)...0 level, (IIb, Ib) = (0,1)...
Rubel, (TIb, Ib) ='(1,0)...
...2 levels, (IIb, Ib) = (1
, 1)...3 level 0 Next, the operation of the circuit shown in FIG. 3 will be explained.

Bit rate 2×fb synchronized with clock 2×fk (
fb=fk) is input from the input terminal 10, this input signal is reduced in bit rate to fb in the two-series conversion circuit 12, and
and (1) 8-sequences are converted into two-series binary codes transmitted through the transmission line 102.

Next, since the transmission is four-valued, the binary code is converted into a gray code by the binary/gray conversion circuit 13 inserted on the 8-series transmission line 101 side. Next, each signal converted into a Gray code is transmitted to the Ib series transmission line 201.
, IIb are input to the respective X-bit storage circuits 14a and 14b of the series transmission line 202.

Here, - as an example, the X-bit storage circuit 14a.

14b is a 3-bit storage circuit, the storage capacity of the ROM 15 is 211 bytes, the X pinto binary counter 6 is a 5-bit binary counter, and the input signal at the input terminal 10 at this time is 0.0.1.0°1. Assuming a 6-bit signal of 1, input terminal 10, Ia series 101, II
The states of each part of the a series 102 and the X focus (3 bits in this case) storage circuits 14a and 14b are as shown in FIG. In other words, in Figure 5, a) is the clock 2Xfk, b) is 10
β ~n 5 is the six-pin state of the signal synchronized with the clock 2×fk at the input terminal 10, and c) is the clock fk.

d) is the state of ■3 series transmission line 101 after 2 series conversion, e) is the state of Ib series transmission line 10 after 2 series conversion
State 2, f) is the state of the memory of the 3-bit storage circuit 14a, and its signals 300.301.30.2 are respectively output terminals D ao and D al (D
an-2) + D output from a2 (Dan-t). g) is the state of the memory of the 3-bit storage circuit 14b, and the signals 400, 401, and 402 are respectively connected to the circuit 1.
4b output terminal I)bo, Dbl(Dbn-2) +
More than Db2 (Dbn-1) is output. The signals output from the output terminals DaO to Da2 and I)bo to])b2 of the 3-bit storage circuits 14a and 14b are
As shown in the figure, address terminal A6 (Ay) of ROM15
~All (AX+y-1) are input alternately and sequentially.

This is because this circuit is synchronized with the clock fk. In other words, A6 (Ay) = Dbo = Q
, A7 (Ay+t)=Dao=O+As (
Ax+y-4)"Dbl:1, A9 (Ax+y-
3) = Dal = 1, Alo (Ax+, -2)
=Db2= 1 + All (Ax+y-1)=l)
32=Q, and if we sequentially observe 2 bits at a time from ROM15, (As, A7) - (0, 0) is 0 level, (A8.A9) = (1, 1) is 3 levels/+
(Aio.

An) - (1, O) can be recognized as 2 levels.

Incidentally, the ROM 15 is made to store information on impulse response waveforms in consideration of reducing the code amount interference caused by the preceding and succeeding symbols.

Therefore, in this example, the stored information in the case of a level bit pattern of o, :3.2 is the dotted line portion 60 in FIG.
It becomes 4. In other words, since the ROM 15 stores the sampled values of the dotted line portion 604 divided into 25 parts for one symbol period l/fb, the 3-bit storage circuit 14
Before the contents of the memories a and 14b change at the next timing of the clock fk, the X pinpoint (5 bits in this case) binary counter 16 sequentially reads out 25 pieces of information from the ROM 15, and the D/A conversion circuit 17 reads this information. This is to convert it into an analog quantity.

Next, the information stored in the ROM 15 will be explained.

As shown in Fig. 6, the 4-level impulse response waveform is based on 0, considering the innogulse response waveform of -3+-1+''L+3, and setting the respective levels to 0°1 and 2.3.
It can be obtained by Therefore, an impulse response waveform is determined in consideration of the influence of the code amount interference of the preceding and following x-1 symbols determined by the X-bit storage circuits 14a and 14b, and the waveform information is stored in the ROM 15. Here, if the level of the three consecutive symbols considered in the above example is 0° 3.2, then the one symbol before and after is changed to 0.
A composite wave of one symbol period 1/fb interval taking into account the influence of the code amount interference of 2 and 2 degrees is shown as the dotted line waveform 604 in Fig. 7. That is, waveform 6 in FIG.
01 is O level, waveform 602 is 3 level, waveform 60
3 is an impulse response waveform of each symbol of two levels, and a dotted line waveform 604 is a 1-symbol period 1/fb portion of the combined wave. The sampling value obtained by dividing this into 2y is stored in the ROM 15. By the way, there are 22 x types of 4-value patterns, and 2y information is stored for each waveform, so
When read out using the y-bit binary counter 6, the four-level impulse response waveform becomes continuous, and the resulting eye pattern becomes as shown in FIG. Incidentally, the storage capacity of the ROM 15 is 22Xx+y (items).

Further, information on multivalued impulse response waveforms can also be stored in the ROM.

As is clear from the above description, the circuit of the present invention transmits one series of bits at a bit rate of -1'Xfb! A multi-sequence conversion circuit that converts the signal into fb and converts it into l-series transmission, and inserts it into each sequence of l-series transmission converted by the conversion circuit to continuously change the state of the signal of each sequence by X bits. Multi-value transmission is achieved by inserting a binary/gray conversion circuit between the bit storage circuit to be observed, so multi-value impulse response waveforms such as 4-value, 8-value, etc. can be converted for multi-value transmission as needed. can be easily generated as a baseband band limiting filter. Furthermore,
Since it is a digital circuit, the overall configuration of the circuit of the present invention is extremely simple, and it is possible to provide a multi-level impulse response waveform generation circuit that is advantageous in terms of cost.

[Brief explanation of the drawing]

FIG. 1 is a conventionally known binary impulse response waveform generation circuit diagram, FIG. 2 is a line diagram showing an eye pattern obtained by the circuit of FIG. 1, and FIG. 3 is a multilevel impulse response waveform generation circuit according to the present invention. A four-level impulse response waveform generation circuit diagram shown as an example of the circuit, FIG. 4 is a line diagram showing an eye pattern obtained by the circuit in FIG. 3, and FIG. A diagram showing the state of each part when a 6-bit input signal is input in a 3-bit storage circuit. Figure 6 is a diagram showing the basic waveform at each level of the 4-value innoculus response waveform. Figure 7 is a diagram showing the basic waveform at each level of the 4-value innoculus response waveform. FIG. 7 is a diagram showing each innocuous response waveform of a symbol and a waveform that takes into consideration the influence of code amount interference of 1 bit before and after the symbol. 10... Input terminal 12... Two-series conversion circuit 13... Binary/gray conversion circuit 14a, 14b... X-bit storage circuit 15...
ROM 16...y-bit binary counter 17...D/A conversion circuit 18...output terminal 19...input terminal 101 of clock fk×2y...
・Binary code I3 Series transmission line 102...Binary code ■3 Series transmission line 201...Gray code Ib Series transmission line 202...Gray code nb Series transmission line 301...Clock fk Transmission line 302... Clock 2Xfk transmission line 303...
Clock fkX2y transmission line patent applicant Japan Radio Co., Ltd.

Claims (1)

[Claims] In a digital signal processing circuit, there is provided a multi-sequence converting path for converting an input signal of 1-sequence transmission of 4×fb into 1-series transmission of 1-sequence transmission of bit 4×fb, and each signal of 2-sequence transmission. a bit accumulation circuit that inserts the states of A ROM that stores information on multi-level impulse response waveforms corresponding to two FXx types of observable bit patterns, a binary counter for reading out the information in the ROM, and an analog converter for the information read out by the binary counter. A multivalued impulse response waveform generation circuit consisting of a digital/analog conversion circuit for converting into quantities.