JPS59108120A - Power source monitor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a distributed intelligence power supply monitor, and more particularly to a distributed intelligence power supply monitor that continuously monitors and stores the status of a power supply for polling and provides an alarm signal when a power supply fails. It is connected to a distributed intelligence power supply monitor that sends out .

Prior Art The reactor protection systems used in modern nuclear power plants typically include a self-test subsystem and a distributed configuration card. Regarding such subsystems, see, for example, the pending 1982 No. 71-J 27 B
I Nj G-J (7) U.S. Patent Application No. 402.

No. 053, ``Self-Test Subsystem for Nuclear Reactor Protection System'', this is a method that can detect randomly failed parts at an early stage to determine the duration of the failure.
lnawachi [The goal is to make time window 4 smaller. Due to the multiple redundancy design, the probability that the failure time windows will coincide is extremely small. If the failures coincide, the operating efficiency of the power plant will decrease, and in rare cases (J means emergency shutdown).
) or even catastrophic failure. Backup systems, including power supplies, must be tested frequently. In order to test the voltage of a power supply in the prior art, it was necessary for the self-testing system to specify a card and serially load test instructions into it.

The card performs the test and places the results in the status register. Subsequently, the self-test subsystem reads this result placed in the status register to learn the status of the power supply. Differences in the tolerances of each power source within a nuclear power plant make testing difficult. While some power supplies must be kept very constant, C1 power supplies can be allowed to fluctuate to some extent.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide continuous monitoring for early detection and self-test notification of failed power supplies and to provide preliminary processing and storage of power supply status information. Distributed intelligence that performs the
It is to monitor the power supply.

The present invention is a monitor attached to the power supply of a nuclear reactor.

This monitor is used only while the self-test rib system is polling for information about failed power supplies.
Continuously monitors the power supply voltage and processes its pleasure. At the power monitor mountain, a micro T1 monitor controls two manual multiplexers. One input of the 1G of human power is selected by the first multiplexer. The outputs are configured in pairs (a3), where the second multiplexer selects one of the output pairs to minimize current leakage from the unselected multiplexer output line. It is converted into a voltage scale proportional to °C by two calculation scalers equipped with a mode removal adjustment mechanism.Continued with C
, an analog-to-digital converter digitizes the signal, and the digitized signal is stored in a buffer 110 (human output). The MicroZorocera 4 executes the algorithm stored in the memory to process the signal, and stores information about the failed power supply in the random access memory (RAM) in the I10 buffer. Blue
The controller sequentially reads the power supply data, updates the data, calculates the ΔC voltage (41), and monitors fluctuations in the DC line. The stored value is periodically examined (to determine if the power supply combination passes the test that the correct ff1LLr is present for H). The register interrupts the self-test subsystem.The self-test subsystem then polls the monitor to identify the failed power supply and identify the type of failure.

Other objects, features, and advantages of the invention will become apparent from the following description and drawings.

Detailed Description of the Embodiments FIG. 1 shows a block diagram of a power supply monitor according to the present invention, and the parts separated by broken lines are shown in FIGS.
Each is shown in detail in the figure.

Power supply monitor 99 is a distributed intelligence means that provides preprocessed information about the status of the power supply to the self-test subsystem. The self-test subsystem performs other testing functions of the reactor control system, while
The monitor 99 independently tests the status of the power source connected to the power source 50 and stores the test results in the 110 buffer 23. The power sources monitored by this device are AC and DC.
Both are within a range of ±50 volts, and their characteristics vary. The AC power source is monitored for frequency drift 1~ and the effective (rms) power IF level is calculated.

Some DC power supplies are highly susceptible to temporary fluctuations,
Some power supplies have a tolerance for average variation from a specified level of -C greater than that of a power supply, and some power supplies require a specified ratio of J5 to -C on phase H. .

The power supply monitor 99 is on one card, and has 16 pairs of input terminals connected to the power supply to be monitored.
Pair-to-8-pair multiplexer 18, second stage 8-pair to 1-pair multiplexer 19, electrical IJ difference network 60, Aflog digital converter 25.1/○ buffer 23,
Multiplexer A5, which controls the 1.10 buffer buffer 1', the memory 3 which controls the algorithm for the converter 22, the address latch 30, and the computer 22.
1. Provides card selector cuff 0 from an external self-test subsystem computer, and power status outputs 135 and 136 for an external combicoater. Algorithms for passing each test pair individually or in combination are stored in memory 31. This memory 31 is a standard industrial component such as NMC27G16.
p ) < OM.

The product names used in this article are based on the book [D.N.T. It is shown in "T.1-". The algorithm is executed by the microcomputer 22, for example, product name N.
(preferably an SC800-r). Computer 22 is a CMOS processor with an .epsilon.3 pixel and has a cycle rate of 2.5 MHz when clocked by a 5 MHz clock 59. The monitoring routine starts immediately, and by default the monitor 22 sets the start address to 1.
It is sent to the bus 100 of 6 people. Computer 22 sets bus bar 100 by setting line 145 to a high level.
This indicates that the address is in the upper half of the . Latch 30.
(preferably product name 54C373, for example) latches the upper half of the address on bus 100 to memory 31.

] button 22 disables latch 30 by setting line 145 low and the lower half of the address is provided to memory 31. Memory 31 is 8 pins 1-
data bytes are sent to bus 100, which computer 22 reads and executes. Computer 22 repeats this cycle to execute the test algorithm stored in memory 31. vs. 50
In order to select a new manpower in -1 amp coater 2
2 sends the address to the bus 100, and by making the line 145 high, it indicates that there is an address in the upper half of the bus.
810 (preferably). Combi coater 22 signals I10 buffer 23 that converter 22 is writing to I10 buffer 23 by pulling write line 146 low. The computer 22 also indicates that data is in the lower half of the bus by pulling the data/address line 145 low. Write the data.l, 10 By the output of 4 pins 1~, which is the output between 5 volts from buffer 23 and ground,
One pair of the 16 manpower will be designated. In order to improve the ratio between the signal and the ambient background noise, the 5 volt signal is transferred to a level shifter 21 (for example, product name 541-S0).
(preferably composed of 3), the mother IgA53 has 1
2pol] is raised to ~. A decoder 20 (preferably comprising, for example, MCI4514) decodes the 4 bits 1 and sends 16 outputs 101 to 116 to the bus 54. All but one of the outputs of decoder 20 are unselected signals, such as low voltages. The line from the human power pair to be tested, e.g. 49h (high voltage selected
). The rising edge of a high level signal pulse arriving at a selected switch in the multi-reflector 18 closes the switch. When viewed from the input pair 50, the monitor 99 always appears to be grounded. The unselected switches are grounded, and the selected switches carry very little current in the line to multiplexer 19, which is shared with the other switch. Since switching causes a practical voltage change at the input terminals, switching failures due to capacitive loads are avoided.
Use the line 125 to select one pair.

The current from multiplexer 19 is output on lines 109 and 110, which is input to voltage difference network 60. line 11
The zero small current is converted and a voltage of the opposite direction appears at the output pin of the operational amplifier 2.

The voltage across adjustable common mode rejection resistor 38a3 and resistor 39 causes a current that is opposite to that of line 110. The current in line 110 is added to the current in line 109 at the negative input of operational amplifier 1.

The operational amplifier 1 produces at its output 56 a voltage that is reduced by, for example, 1/1''N from the voltage between the two power supply input lines 490.

The analog voltage at the output 56 of the voltage difference network 60 is converted to a 10-bit digital value by a bipolar input analog-to-digital converter 25 (eg, preferably constructed from the standard designation AD571). This digital value is sent from the bus 58 to the I10 buffer ?23.

Computer 22 reports the address to I10 buffer 23 by driving line 145 high, and then reads the I10 address of bus 58 onto bus 100. Computer 22 forces read line 147 low and I10 buffer 23 provides data from bus 58 to bus 00 for reading. The computer 22 reads this data, executes the algorithm from the memory 31, and compares the data from method (a) above with reference values also obtained from the memory 31. Since the A/D converter can only convert instantaneous voltage,
AC voltage calculations are performed by routines from memory 31. This routine locates zero voltage crossings and takes many equally spaced samples during one AC1111 interval. Each sample and its combination is compared to the individual and total range limits stored in memory 31. If the lean pull is more than 3 samples or beyond those ranges, the power supply is declared "out of tolerance" and an alarm signal is sent to I10 line 125.
will be sent to.

The monitor 922 determines whether the voltage of each power pair is good or not, and if it is not good, sends a diagnostic message to the I10 buffer 2.
3. Stored in 4. The I10 buffer 723 includes a watchdog timer that sends an abort signal to the C Combi coater 22 via line 14B if the buffer does not receive a diagnostic message within a selected millisecond.
Sends a restart setting signal. Output line 12 of buffer 23
If the "Alarm 1\" bit of 5, ie, the flag, has been rehit by the initialization cycle, the flag is let by the first fault diagnosis message. Diagnostic details may include the time, duration and magnitude of the bad voltage, which are stored at other addresses in the I10 buffer 23 and later serially output on line 126. Output line 12 to self-test subsystem
5 &) and 126 are level shifted as described above by a level shifter 24 of the same type. Line 125 is shifted to become line 135, which becomes one input of AND gate 29. Another source of power for the two gates is the activating high level signal on line 41 from the self-test subsystem. A high level signal on line 135 causes the outputs of groups 1-29, alarm line 47, to go high, which preferably causes a hardware interrupt within the self-test 4-knob system.

The system then polls the monitor for pre-processed details of the apparent failure stored in the 110 buffer 23.

The self-test subsystem polls the monitor 99, typically every 2.3 minutes, and sends a high level card selection signal over line 70 to the interrupt input of the computer 22 in the event of an alarm. This will be done immediately. By executing another algorithm stored in the memory 31, the 21-impicoter 22 writes diagnostic items in series on the 10-buffer line 126. This is level shifted and sent to the self-test subsystem via serial test f' output line 67.

The self-test subsystem then executes routines that further analyze the data. Typically, a failure of one power supply will cause a message to be sent to the reactor operations indicating that the power supply is out of tolerance.

The present invention has been described above with reference to embodiments of the C IC, but those skilled in the art will be able to make changes and modifications thereto within the spirit and scope of the present invention. The scope of the present invention is defined in the claims, and the specifications of parts used in the embodiments of the present invention are shown in the table below as a reference example.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a power supply monitor of the present invention which receives input from multiple power supplies and sends preprocessed data to a self-test subsystem. FIG. 2 is a circuit diagram of a first stage multiplexer for selecting power supply monitor leads. Figure 3 shows the second stage multiplexer,
1 is a small circuit diagram of the voltage difference network, analog-to-digital converter, and input/output buffer 1; Fourth
The figure is a wiring diagram showing a microcomputer, a memory storing test algorithms and voltage standard values, and a 1.10 buffer. FIG. 5 is a circuit diagram showing the card select lines from the self-test subsystem as well as the alarm and serial data lines to the self-test subsystem. (Explanation of symbols) 1.2... Performance amplifier; 18.19... Multiplexer; 22... Microphone [''] button; 23... I10 buffer; 24... Level shifter; 25. ...Analog-digital converter; 31...Memory; 50...Manual power; 70...Card selection manual; 99...Power supply monitor; 135.136...Power status output. Attorney for patent applicant General Electric Company (76
30) Toku Numa 1146 Plainfield Street, Johnston, Rhode Island, United States of America ○Inventor William Anthony Mercanti Jr. 3517 South Bascom Avenue, 6 Campbell AP, California, United States of America

Claims (1)

[Claims] (1) Reactor Protection System Self-Test A power supply monitor that is periodically polled by the reactor protection system, has a single monitor input from multiple independent power supplies, and sends an indication of a failed power supply to the self-test subsystem. At-
C1 A single point input terminal for a plurality of lightning monitors, a multiplexer means for multiplexing and outputting the current from one point of the monitor, converting the current from the multiplexer means into a voltage proportional to the voltage between the phase H of one point of the monitor. analog-to-digital converter means for digitizing said proportional voltage; memory means for providing a stored voltage reference and a test algorithm; control means for controlling the output of test results such as an indication of a failed power supply in response to a power selection signal; 1. A power supply monitor comprising a combination of means 1 and 10 for outputting a monitor, and a monitor output means. (2) In the power supply monitor according to claim 1, the control means controls the power supply through the multiplexer means.
a microcomputer operatively connected to select another power supply point and to compare said digitized voltage with said stored reference; and said output means in the event of a power failure. A power supply monitor including a first terminal for displaying associated alarms and a second terminal for serially displaying details of a power supply failure.