JPS59107510A - Ohmic electrode forming method in compound semiconductor - Google Patents
Ohmic electrode forming method in compound semiconductorInfo
- Publication number
- JPS59107510A JPS59107510A JP57216826A JP21682682A JPS59107510A JP S59107510 A JPS59107510 A JP S59107510A JP 57216826 A JP57216826 A JP 57216826A JP 21682682 A JP21682682 A JP 21682682A JP S59107510 A JPS59107510 A JP S59107510A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- compound semiconductor
- ohmic electrode
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 150000001875 compounds Chemical class 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000000470 constituent Substances 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims abstract 4
- 239000010931 gold Substances 0.000 claims description 8
- 238000005275 alloying Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000007738 vacuum evaporation Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
- H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/3235—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Electromagnetism (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明ｔｉｔ電極形成方法に関し、詳しくはリンＰを含
む川−Ｖ族化合物半導体結晶及び混晶、例えばＧａＩｎ
ＰあるいはＧａＩｎＡｓｐ等の化合物半導体のウェーハ
上に電極を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for forming a tit electrode.
The present invention relates to a method of forming electrodes on a wafer of a compound semiconductor such as P or GaInAsp.
従来、ｐ ＩｎＰ、 ｐ−ＩｎＧａＡｓＰ系の化合物半
導体に対しては、生ＫＡｕベースの合金（側光ばＡｕＺ
ｎ／ＡＬｌ、ＡｕＭｇ／Ａｕ等）ノ多層構ｍ（Ｄ金属膜
によりオーム性電極を形成していた。これらの金属膜を
蒸着あるいはメッキ後、Ｎ２あるいはＨｌｌ Ｎ２ガ
ス芥囲気で半導体との合金化処理を施す。Conventionally, for p-InP and p-InGaAsP-based compound semiconductors, raw KAu-based alloys (side-lighting AuZ
The ohmic electrode was formed using a metal film (D). After depositing or plating these metal films, they were alloyed with a semiconductor in an atmosphere of N2 or HllN2 gas. Apply processing.
合金化によりオーム性電極を作る方法は、半導体と金属
膜を互いに溶ける温度まで加熱する。ついで冷却過程で
半導体は再結晶するが、このとき金属（例えばＡ ｕ
）中に添加されている不純物（例えばＺｎ２Ｍｇ）をと
り込みながら成長する。The method of making ohmic electrodes by alloying involves heating a semiconductor and a metal film to a temperature where they melt together. Then, during the cooling process, the semiconductor recrystallizes, but at this time metals (for example, Au
) grows while incorporating impurities (for example, Zn2Mg) added in the film.
この結果、接触するバルク牛導体と同型の高ａ＃ドーピ
ング層をつくる。しかしこの合金化処理によってＡｕと
半導体構成元素からなる商抵抗の金属間化合物層をその
界面に形成すると、かえって接触抵抗を上ける結果とな
り好ましくない。また合金化が不十分な場合は、高濃贋
ドーピング層が十分に形成されないため接触抵抗が高く
、これも好ましくない。ＩｎおよびＰ’を主要構成元素
とする化合物半導体ではこのオーム性電極を形成する際
の最適熱処理条件の範囲が狭く、素子の量産の場合再現
性良く良好なオーム性電極を得ることは困難である。This results in a high a# doping layer that is the same type as the contacting bulk conductor. However, if an intermetallic compound layer with a quotient resistance consisting of Au and semiconductor constituent elements is formed at the interface by this alloying treatment, the contact resistance will increase on the contrary, which is not preferable. Furthermore, if the alloying is insufficient, the highly concentrated counterfeit doping layer will not be sufficiently formed, resulting in high contact resistance, which is also undesirable. In compound semiconductors whose main constituent elements are In and P', the range of optimal heat treatment conditions when forming ohmic electrodes is narrow, and it is difficult to obtain good ohmic electrodes with good reproducibility when mass producing devices. .
本発明の目的はリン（Ｐ）を主要構成元素として含む■
−■族化合物半導体に対して再現性の良い接触抵抗の小
さいオーム性電極形成法を提供することにある。The object of the present invention is to contain phosphorus (P) as a main constituent element.
- To provide a method for forming ohmic electrodes with good reproducibility and low contact resistance for group compound semiconductors.
半導体表面に高濃度ドーピング層を形成する方法として
は、先に述べた合金化の他に不純物元素の拡散あるいけ
イオン打込みによる方法がある。In addition to the above-mentioned alloying, methods for forming a highly doped layer on the semiconductor surface include diffusion of impurity elements or ion implantation.
この後、電極に高融点金属を被着すれは、熱的に安定で
耐熱性の良いオーム性電極が得られる。しかしＰは気化
しやすいため、高融点金塊被着時のウェーハ温度によっ
ては、蒸着前の加熱によってＰが気化して金属−半導体
界面に変成層を形成する。このため、その後の熱処理に
よっても接触抵抗が高く良いオーム性を極とならない。Thereafter, by coating the electrode with a high melting point metal, a thermally stable and heat resistant ohmic electrode is obtained. However, since P is easily vaporized, depending on the wafer temperature at the time of depositing the high melting point gold ingot, P may be vaporized by heating before vapor deposition to form a metamorphosed layer at the metal-semiconductor interface. Therefore, even after subsequent heat treatment, the contact resistance is high and good ohmic properties cannot be obtained.
そこでウェーハ表面からのＰの気化を防止するため、低
温で被着した俊、高温で熱処理したところ良好なオーム
性電極になることが明らかになった。Therefore, in order to prevent the evaporation of P from the wafer surface, it was revealed that the material deposited at a low temperature was heat-treated at a high temperature, resulting in a good ohmic electrode.
第１図はｐ−ＩｎＰ基板１０１（Ｚｎドープ５ｘ １０
”／ｃｍ” ；ρ＝ ０．０５Ω−Ｃｒｎ）上にｐ”−
Ｉｎｏ、ｔＧａｏ、ｅＡＳｏ−２Ｐｏ、ｓ 層１０２（
厚さ０．４ μｍ；Ｚｎ表面濃度〜１０′９／ｃｒｎ３
）を設けたウエーノ・に裏面全面（ｐ −Ｉ ｎ Ｐ基
板側）にＡｕＺｎ／Ａｕ２虐の合金電位１０３を、表面
（ｐ＋−Ｉ ｎｏｓｔＧａｏ、５ＡＳｏ、２Ｐｏ、ｓ層
側）に第１の金属層１０４に’ｌ’ ｉ ５ Ｑ ｎ
ｍを第２の金属層１０５にＭｏ ２００ ｎ ｍｅ、第
３の金属層１０６にＡＵ５００ｎｍを用いた円形の電極
（６０μｍφ）をもつ構造のチップであり、円形電極の
オーム性を調べる目的でつくられたものである。第２図
および第３図はこの電流電圧特性を示すものである。FIG. 1 shows a p-InP substrate 101 (Zn doped 5x 10
p”- on “/cm”; ρ=0.05Ω-Crn)
Ino, tGao, eASo-2Po, s layer 102 (
Thickness 0.4 μm; Zn surface concentration ~10'9/crn3
) was provided with an AuZn/Au2 alloy potential 103 on the entire back surface (p-I n P substrate side), and a first metal layer on the front surface (p+-I nostGao, 5ASo, 2Po, s layer side). 'l' in 104 i 5 Q n
This chip has a circular electrode (60 μmφ) using Mo 200 nm for the second metal layer 105 and AU 500 nm for the third metal layer 106, and was created for the purpose of investigating the ohmic properties of the circular electrode. It is something that FIGS. 2 and 3 show this current-voltage characteristic.
第２図の曲ｆｔＭ１０８はウェーハに第１の金属層１０
４（’ｌ”ｉ）を室温で蒸着したものであり、多層構造
の電極全蒸着したのみで熱処理前の特性である。これを
水素雰囲気中で４００Ｃ，１０分間の熱処理を施すこと
によって曲線１０７に示すような直線性の良いオーム性
電極が得られた。この時の接触比抵抗はρｃ”１〜３Ｘ
１０−’Ω−ｃｒＡであった。第３図の曲線１１（ｌウ
ェーノミに第１の金属層１０４（’ｌ’ｉ）を２０００
の条件で蒸着した多層金属電極の電流電圧特性であシ、
これに同様の熱処理を施したものの電流″ε圧特性が曲
線１０９である。いずれも良い直藏性が得られずオーム
性を極になっていない。第４図は第１層のＴｉの蒸着温
度を変えた場合について、４００Ｃ熱処理後の上記多層
電極のρＣの層化を調べたものである。これから明らか
なように２００Ｃ未満の温度で第１層の金属を蒸着し、
その後４００Ｃまで加熱することによって良好なオーミ
ンク電極となる。なおＡｕがｐ” Ｉｎｏ＊５Ｇａｏ
、ｔＡＳｏ、２Ｐａ、ｓ層と反応するまで熱処理温度を
上けるとかえって接触抵抗が上昇する。これはＡｕベー
スの合金型ｉｌｉ；惨に比べて、反応開好温度も５５０
Ｃと高く、耐熱性に優れていることが明らかとなった。The curve ftM108 in FIG.
4 ('l"i) was deposited at room temperature, and the characteristics are those before heat treatment, even though the entire electrode of the multilayer structure was deposited. By heat-treating this at 400C for 10 minutes in a hydrogen atmosphere, curve 107 was obtained. An ohmic electrode with good linearity was obtained as shown in .The contact specific resistance at this time was ρc"1~3X
It was 10-'Ω-crA. The first metal layer 104 ('l'i) is applied to the curve 11 in FIG.
The current-voltage characteristics of the multilayer metal electrode deposited under the conditions of
Curve 109 shows the current and ε pressure characteristics of the same heat-treated product. In both cases, good directivity was not obtained and the ohmic property was not achieved. Figure 4 shows the deposition of the first layer of Ti. The layering of ρC of the above multilayer electrode after heat treatment at 400C was investigated when the temperature was changed.As is clear from this, the first layer of metal was deposited at a temperature below 200C,
A good ohmink electrode is then obtained by heating to 400C. Note that Au is p” Ino*5Gao
, tASo, 2Pa, if the heat treatment temperature is increased until it reacts with the s layer, the contact resistance will increase on the contrary. This is an Au-based alloy type ili; the reaction opening temperature is also 550
It was revealed that the heat resistance was high, and the heat resistance was excellent.
以下、本発明の一実施例全図を用いて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to all drawings.
第５図は本発明によるＩｎＧａＡｓＰ／ＩｎＰ半導体レ
ーザを示す。ｎ型Ｉｒ１Ｐ基板２０１に形成されたｐ型
ＩｎＰからなる埋め込みＪ＊ ２０２およびｎ型ＩｎＰ
からなる埋め込み層２０３によって埋め込まれたＩｎＧ
ａＡｓｐ活性層２０５に電流を限定して流すために、埋
め込み層２０２と伝導型の異なるｈ型ＩｎＧａＡｓＰ層
２０４が表面に設けてあり、またＩｎＧａＡｓＰ活性層
２０５の上には、ｐ型Ｉｎｐからなるクランド／＊ ２
０６とキャンプ層と呼ばれるｐ＋型ＩｎＧａＡｓｐから
なる高伝導度を膏２０７が設けられている。埋め込み層
２０２，２０３とキャンプ層２０７に位置合わせして電
極を設けるために表面に５ｉｎ２又はＰ Ｓ Ｇ （Ｐ
ｈｏｓｈｈｏ −８ｉｌｉｃａｔｅ Ｇｌａｓｓ）膜か
らなる絶縁膜層２０８ｆ：設け、その一部に穴開けを行
なった後、真窒蒸漸法によって第１の金属層２０９とし
てＴｉを３０〜５０ｎｍ破着する。第１の金属層として
は高融点金属でかつ絶縁路２０８との密着性が良いこと
が必要である。Ｔｉの他にＣｒも同様の効果がある。そ
の上に第２の金属層２１０としてＭｏ、Ｗ又はｐｉを２
００〜３００ｎｍ、さらにその上に第３金属増２１１と
してＡｕを０．５〜１μｍ破着する。この第２の金属層
２１０の役割は第１の金属層２０９と第３の金属層２１
１（Ａｌｌ）との熱処理による反応を防ぐために挿入さ
れたものである。第３の金属４Ａｕけボンディングを容
易にするために用いられる。この仙薬１の金属層と第２
の金属層との役割を兼ねる金属として第１層にＭＯ又は
Ｗを用いて、その上にＡ ｕ ′（＋−用いる構造も可
能である。第喧の金属層の被着開始時はウェーハ表面温
度は室温である。被着中に蒸着源からの輻射熱のためウ
ェーハ表面温度は１００ｒ程度まで上昇する。この後第
２の金属層および第３の金属層の被着は金属層間の密層
性を艮くするため１５０Ｃで行なう。この後ｐ９ｆ！Ｉ
電極をＨ２雰囲気中で４００Ｃ，２０分間熱処理を施す
ことによって良いオーム性′Ｉｔｌｌｆ！、、となる。FIG. 5 shows an InGaAsP/InP semiconductor laser according to the present invention. A buried J* 202 made of p-type InP formed on an n-type Ir1P substrate 201 and an n-type InP
InG embedded by a buried layer 203 consisting of
In order to limit the current flow to the aAsp active layer 205, an h-type InGaAsP layer 204 having a different conductivity type from the buried layer 202 is provided on the surface, and on the InGaAsP active layer 205, a ground made of p-type InP is provided. /* 2
06 and a highly conductive layer 207 made of p+ type InGaAsp called a camp layer. 5in2 or P S G (P
After forming an insulating film layer 208f made of an insulating film layer 208f, which is made of a nitride glass film, and making a hole in a part of the insulating film layer 208f, 30 to 50 nm of Ti is deposited as a first metal layer 209 using a true nitrogen evaporation method. The first metal layer needs to be a high melting point metal and have good adhesion to the insulating path 208. In addition to Ti, Cr also has similar effects. Thereon, a second metal layer 210 of Mo, W or pi is applied.
00 to 300 nm, and on top of that, Au is broken to a thickness of 0.5 to 1 μm as a third metal layer 211. The role of this second metal layer 210 is to support the first metal layer 209 and the third metal layer 21.
This was inserted to prevent reaction with 1 (All) due to heat treatment. Used to facilitate bonding to the third metal 4Au. The metal layer of this elixir 1 and the second
It is also possible to use MO or W in the first layer as a metal that also serves as the second metal layer, and use A u '(+-) on top of it. The temperature is room temperature.During deposition, the wafer surface temperature rises to about 100r due to radiant heat from the evaporation source.After this, the second and third metal layers are deposited due to the dense layer between the metal layers. Do it at 150C to make it look better.After this, p9f!I
By heat-treating the electrode at 400C for 20 minutes in an H2 atmosphere, good ohmic properties can be obtained. ,, becomes.
最後にｎ側電極２１２を例えばＡｕＧｅＮｉ／Ｐｄ／Ａ
ｕ （７）三ｌ−構造によって蒸着アロイ法で形成し、
へき開によりチック化する。このチップを放熱体（例え
ばＣｕ又はＳｉＣブロック）にＰｂ−８ｎ半田を用いて
ポンディングして組立てる。Finally, the n-side electrode 212 is made of, for example, AuGeNi/Pd/A.
u (7) formed by a vapor deposition alloy method with a tril-structure,
Tic occurs due to cleavage. This chip is assembled by bonding to a heat sink (for example, a Cu or SiC block) using Pb-8n solder.
第６図にこの半導体レーザの電流電圧特性を示す。曲線
３１は正常な特性であり、立上がり電圧は活性ノーの禁
制帯幅から予想される値である。一方３２は第１の金属
ＪｖｉＴｉを２００Ｃで蒸着した後に同様の熱処理ｆｆ
：施したものである。電極−半導体界面に形成された変
成層のため立上が９電圧が高くなるとともに、ダイオー
ドの直列抵抗も高くなってしまっている。FIG. 6 shows the current-voltage characteristics of this semiconductor laser. Curve 31 is a normal characteristic, and the rising voltage is the value expected from the forbidden band width of the active node. On the other hand, 32 is subjected to the same heat treatment after depositing the first metal JviTi at 200C.
: It was given. Due to the metamorphic layer formed at the electrode-semiconductor interface, the rising voltage becomes high, and the series resistance of the diode also becomes high.
本発明によれは、Ｐを主要構成元累として含む■−■族
化合物半導体に対して再現性の良い、接触抵抗の小さい
オーム性電４！ｊ！、全形成できるので、例えは１〜１
．５μｍμｍ波長波長レーザ光ダイオード、受光ダイオ
ードの電極として有効である。According to the present invention, the ohmic conductor 4! has good reproducibility and low contact resistance for ■-■ group compound semiconductors containing P as a main constituent element. j! , all can be formed, so the example is 1 to 1
．． It is effective as an electrode for a 5 μm μm wavelength laser photodiode and a light receiving diode.
第１図はオーム性＠物の特性評価をするチップを示す断
面図、第２図、第３スｄオーム性電極の電流電圧特性を
示す図、第４図は第１層Ｔｉ蒸着温度と接触比抵抗の関
係を示す図、第５図は半導体レーザの構造金示す斜視図
、第６図は半導体レーザの電流は比特性を示す図である
。
１０１−ｐ−Ｉ ｎＰ基板、１０２−ｐ”−Ｉｎ０．ｌ
Ｇａ０．９ＡＳＯ−２ＰＯ−８層、１０３ ・ＡｕＺｎ
／Ａｕ合金電極、ＸＯ４・・・第１の憧属層Ｔ ｉ、
１０５・・・第２の金属層Ｍｏ、１０６・・・第３の金
属層ＡＵ、２０１・・ｎ−Ｉ ｎ Ｐ、 ２０２−埋
め込み層ｐ−Ｉ ｎ Ｐ、 ２０３−−・ｎ−Ｉ ｎ
Ｐｍめ込み層、２０４”’ｎ−ＩｎＧａＡｓＰ層、２０
５・・・■ｎＧａＡｓＰ活姉層、２０６−・−ｐ−Ｉ
ｎＰ層、２０７．、・ｐ＋−ＩｎＧａＡｓＰキャンプ層
、２０８・・・絶縁膜、２０９・・・ｐ側電極の第１の
金属層（１’ｉ）、２１０・・・ｐ側電極の第２の金属
層（ＭＯ）、２１１・・・ｐ側電極の第３の第 １ 図
冨 Ｚ 図 Ｎ ３ 図
電圧 電圧
■ ４ 図
箭 ５ 図
７／／
′ＦＪに図
電ＩＬ（Ｖ）
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 千葉勝昭
国分寺市東恋ケ窪１丁目２８０番
地株式会社日立製作所中央研究
所内
０発 明 者 加藤弘
高崎市西横手町１１１番地株式会
社日立製作所高崎工場内
０発 明 者 小林正道
高崎市西横手町１１１番地株式会
社日立製作所高崎工場内Figure 1 is a cross-sectional view showing a chip for evaluating the characteristics of ohmic objects, Figure 2 is a diagram showing the current-voltage characteristics of the d-ohmic electrode, and Figure 4 is the temperature and contact of the first layer Ti evaporation. FIG. 5 is a perspective view showing the structure of the semiconductor laser, and FIG. 6 is a diagram showing the current characteristic of the semiconductor laser. 101-p-I nP substrate, 102-p''-In0.l
Ga0.9ASO-2PO-8 layer, 103・AuZn
/Au alloy electrode, XO4...first aspiration layer T i,
105... Second metal layer Mo, 106... Third metal layer AU, 201... n-I n P, 202--Buried layer p-I n P, 203-- n-I n
Pm embedded layer, 204''n-InGaAsP layer, 20
5...■nGaAsP active layer, 206--p-I
nP layer, 207. , p+-InGaAsP camp layer, 208... insulating film, 209... first metal layer (1'i) of p-side electrode, 210... second metal layer (MO) of p-side electrode , 211...The third 1st part of the p-side electrode Figure Z Figure N 3 Figure voltage Voltage ■ 4 Figure 5 Figure 7// 'FJ to Figure IL (V) Kokubunji-shi Higashikoigakubo 1-280 Co., Ltd. 0 inventions in the Hitachi, Ltd. Central Research Laboratory, 1-280 Higashi-Koigakubo, Kokubunji-shi, Hitachi, Ltd. 0 inventions, Hirokato Kato, 111 Nishiyokote-cho, Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji City, Ltd. 0 inventions, Mr. Kobayashi Masamichi, Takasaki City, Nishiyokote-cho 111, Hitachi, Ltd., Takasaki Factory
Claims (1)
をもつ、少なくともＰを主要構成元素とする化合物半導
体結晶に少なくとも第１層に高融点金属層を２００Ｃ未
満の温度で被着し、かつ最上層にＡｌ１層を被着する多
層金Ｒ膜被清工程と、上記Ａｕ層と化合物半導体結晶が
合金化反応を起こさない温度および時間の範囲内で熱処
理を施す工程を少なくとも含む化合物半導体オーム性電
極形成法。A compound semiconductor crystal containing P as a main constituent element and having an acceptor impurity surface concentration of 10"10n" or more is coated with a high melting point metal layer as at least the first layer at a temperature of less than 200C, and an Al1 layer as the top layer. A method for forming a compound semiconductor ohmic electrode comprising at least a step of applying a multilayer gold R film and a step of performing heat treatment within a temperature and time range that does not cause an alloying reaction between the Au layer and the compound semiconductor crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57216826A JPS59107510A (en) | 1982-12-13 | 1982-12-13 | Ohmic electrode forming method in compound semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57216826A JPS59107510A (en) | 1982-12-13 | 1982-12-13 | Ohmic electrode forming method in compound semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59107510A true JPS59107510A (en) | 1984-06-21 |
Family
ID=16694495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57216826A Pending JPS59107510A (en) | 1982-12-13 | 1982-12-13 | Ohmic electrode forming method in compound semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59107510A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225280A (en) * | 1990-12-26 | 1992-08-14 | Nikko Kyodo Co Ltd | Formation method of ohmic electrode |
-
1982
- 1982-12-13 JP JP57216826A patent/JPS59107510A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225280A (en) * | 1990-12-26 | 1992-08-14 | Nikko Kyodo Co Ltd | Formation method of ohmic electrode |
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