JPS59106062A - Address selecting circuit - Google Patents

Abstract

PURPOSE:To reduce a required number of kinds of print board package, by providing exclusive OR gates on a package in accordance with respective bits of a peculiar identification code and discriminating the selection of packages by outputs of exclusive OR gates. CONSTITUTION:When an address (a)=x4xx (hexadecimal) is transmitted from a microprocessor MPU1, (0) is transmitted to input terminals A8, A9, and All of packages 60, 80, and 100, and (1) is transmitted to a terminal A10. The address is inputted to the first terminals of exclusive OR gates 24-27, 33-36, and 41- 44. Conditions of exclusive OR gates are satisfied in the packag 60 and a selecting signal (g) of logical (1) is outputted from a gate 18 to start a decoder 19, and a specific circuit 5 to be selected is selected by the address (a) other than the identification code inputted from a terminal A. However, conditions of exclusive OR gates 33-36 and 41-44 are not satisfied in packages 80 and 100, and consequently, decoders 21 and 23 are not started, and circuits 7 and 9 to be selected are not selected.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an address selection circuit, particularly in an electronic device having a plurality of pancages that determines selection by an address transmitted from a microprocessor via an address bus. This invention relates to an address selection circuit that can reduce the number of types.

(bl Technology background) Most modern electronic devices are composed of multiple printed circuit board packages with printed wiring.The increase in the number of types of printed board packages reduces the design man-hours and manufacturing costs for each printed board package. In addition to increasing
The number of printed board pancages that must be prepared for maintenance of the electronic device will also increase. Therefore, it is desirable to reduce the number of types of printed board packages constituting the electronic device as much as possible.

(C1 Prior Art and Problems) Figure 1 is a diagram showing an example of a conventional address selection circuit in this type of electronic device. A pancase 4 that mounts a memory 2, a read/write memory 3 for temporarily storing data, etc., and a 16-viso I
- A computer connected to the computer 4 by an address bus 11 capable of transmitting an address a of the configuration, and implementing a plurality of selected circuits 5 selected by the address a sent from the microprocessor 1 to the address bus 11 6, a package 8 on which a plurality of selected circuits 7 are mounted, and a package 10 on which a plurality of selected circuits 9 are mounted. Each selected circuit 5.7 and 9 has a unique address a - (x 4 x x)
H, (X 5 x x) H and (×EXX) H(
H indicates hexadecimal display) is given. The numbers 4.5 and E in t-a-address a represent each package 6.
It serves as the identification code for numbers 8 and 10. Each pancage 6.8 and 10 has terminals AO through A1, respectively.
5 to the address bus 11. In FIG. 1, only the terminals A8, AO, AIO, and A11 related to the identification code of each package 6.8 and 10 are individually shown, and the other terminals AO to A7 and A11 are individually shown.
12 to A15 are collectively labeled as terminal A. The terminals A8, AO and All are connected to the input terminal G of the gate 18 through the input terminals 12.13 and 14, and the terminal AIO is directly connected to the input terminal G of the gate 18. This is connected. Also, package 8
Terminals A9 and All are inno\-
8 and AIO are connected directly to the input terminals of gate 20 through terminals 15 and 16, respectively. Furthermore, in the package 10, the terminal A8 is connected to the gate 21 via the inverter 17, and the terminal A9, AIO and AIH are directly connected to the gate 21.
Connected to the second input terminal. Now Micro Pro Sensor 1
In order to select a specific selected circuit 5 in the package 6, the upper number of the address nomas 11 and the address a= (x4xx
) H is transmitted to the terminals A8, AO, and All of each noise cage 6.8 and lO, and the logic value 0 is transmitted to the terminals A10 & 4 straight and 1 wall (note that the logic value 0 is , logical IG corresponds to voltage +V). In the pan cage 6, the logic value O transmitted to the terminals A8, AO and All is connected to the inverter 12.13.
and 14 and input to the gate 18, and the logic value 1 transmitted to the terminal AIO is directly input to the gate 18. Therefore, from 1B, the logical value is 1
A selection signal g is output, and the decoder 19 is activated. As a result, the decoder 19 selects the specific selected circuit 5 using the address a other than the identification code input from the terminal A. On the other hand, in the PC cage 8, terminals A9 and ALL
After the logical value 0 transmitted to the terminal AIO is converted to a logical value 1 by the inverters 15 and 16, the logical value 1 transmitted to the terminal AIO is inputted to the gate 20, respectively, but is not transmitted to the terminal 8. The logical value O is the left gate 20
Therefore, the selection signal g of logic value O is output from the gate 20. As a result, the decoder 21 is not activated,
The selected circuit 7 is also not selected. Similarly package 10
Also, the logic value O transmitted to the terminal 8 is converted to the logic value 1 by the inverter 17, and then the logic value O transmitted to the terminal AIO
The logic value 1 transmitted to the terminals A9 and A11' is input to the respective gates 22, but the logic value O transmitted to the terminals A9 and A11' is input to the gates 22.
A selection signal g with a logical value of 0 is output from the decoder 23.
is not activated and does not select the selected circuit 9. Next, when the microprocessor 1 sends the address a=(x5xX)H onto the address bus 1 in order to select a specific selected circuit 7 in the pancage 8, each pancage 6.
Logic value 0 is set to terminals A9 and All of terminals 8 and 10,
Furthermore, since the logic value 1 is transmitted to the terminals A8 and AIO, through the same process as described above, only the gate 20 in the panel cage 8 outputs the logic value 10 selection signal g and the decoder 2
1 is activated, and the gate 18 in the package 6 and the gate 22 in the package 10 each output a selection signal g having a logic value of 0 and do not activate the decoders 19 and 23. As a result, the required selected circuit 7 in the knob cage B is selected.

Furthermore, when the microprocessor 1 sends the address a= (XEXX)) (on the address bus 11 in order to select a specific selected circuit 9 in the package IO, the terminal A8 of each package 6, 8 and 10 is Since the logic value 0 is transmitted to the terminals A9 to All, and the logic value 1 is transmitted to the terminals A9 to All, the gate 22 in the package 10 is transmitted through the same process as described above.
gate 18 in package 6 and gate 20 in package 8 each output a selection signal g with logic value O to activate decoder 23. does not start.

As a result, the required selected circuit 9 within the package 10 is selected.

As is clear from the above description, in the conventional address selection circuit, each pancage 6.8 and 10 has a different configuration in order to identify the identification code assigned to each pancage 6.8 and 10.

Therefore, there are four types of printed board packages, which has the drawback of increasing design man-hours and manufacturing costs.

fd) Object of the Invention An object of the present invention is to eliminate the drawbacks of the conventional address selection circuits as described above and to realize a means that can reduce the number of required types of printed board panels as much as possible.

te+ Structure of the Invention The object of the present invention is to provide an electronic system having a plurality of bar cages, each of which is given a unique identification code, and which determines selection by comparing an address transmitted from a microprocessor via an address bus with the identification code. In the apparatus, an exclusive OR gate is provided in the bar cage corresponding to each bit of the identification code, and the identification code of the address transmitted from the address bus is input to one input terminal of the exclusive OR gate. The identification is performed by inputting the corresponding bit, supplying a logic value setting voltage to the other input terminal of the exclusive OR gate via a resistor, connecting each to an external terminal, and grounding the required external terminal. This is achieved by setting a sign and determining the selection of the pancage based on the output of each of the exclusive OR gates.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an address selection circuit according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, a package 60 mounting a plurality of selected circuits 5 is provided with four exclusive OR gates 24 to 27, and each exclusive OR gate 24 to 2 is provided with four exclusive OR gates 24 to 27.
Terminals 8 to All are connected to the first input terminal of 7, and a voltage +■ indicating a logical value 1 is supplied to the second input terminal via resistors 29 to 32, and terminals B8 to B8 are connected to terminals B8 to All. Connected to Bll. Furthermore, the pancage 80 on which the plurality of selected circuits 7 are mounted and the package 100 on which the plurality of selected circuits 9 are mounted have exactly the same configuration as the pancage 60. However, in the package 60, only the terminal BIO is grounded, so that the logic value 0 is input to the second input terminal of the exclusive OR gate 26, but the second input terminal of the exclusive OR gates 24, 25 and 27 A logical value of 1 is input to the input terminal. Furthermore, in the package 80, the terminal B8 and BIO are grounded, so that the logic value O is input to the second input terminals of the exclusive OR gates 33 and 35, but the second input terminal of the exclusive OR gates 34 and 36 is A logical value of 1 is input to the input terminal. Furthermore, since the terminals B9 to Bll of the package 100 are grounded, a logical value of 0 is input to the second input terminals of the exclusive OR gates 42 to 44, but the second input terminal of the exclusive OR gate 41 is A logical value of 1 is input to . Now microprocessor 1 is puff cage 60
When the address a=(x4xx)H is sent onto the address bus 11 in order to select a specific selected circuit 5 in the package, the logic value 0 is set at the terminals A8, A9 and All of each package 60, 80 and 100. , and the logic value 1 is transmitted to the terminal A40, and the exclusive OR gates 24 to 27, respectively.
．． The signals are input to first input terminals 33 to 36 and 41 to 44. In the package 60, since the logic value 0 and the logic value 1 are respectively input to both input terminals of each exclusive OR gate 24 to 27, each exclusive OR gate 2
4 to 27 output a logic value of 1 and input it to the gate 18. Therefore, a selection signal g having a logic value of 1 is output from the gate 1-18 to activate the decoder 19. As a result decoder 1
9 is an address a other than the identification code input from terminal A.
A specific selected circuit 25 is selected. On the other hand, in the bankage 80, since the logic value 0 and the logic value l are respectively input to both input terminals of the exclusive OR gates 34 to 36, each exclusive OR gate 34 to 36 has the logic value 1.
However, since a logic value 0 is input to both input terminals of the exclusive OR gate 33, a logic value 0 is output. Therefore, the selection signal g having the logical value O is output from the gate 20, the decoder 21 is not activated, and the selected circuit 7 is not selected. Similarly, in the pancage 100, since the logic value 0 and the logic value l are respectively input to both the input terminals of the exclusive OR gates 41 and 43, each exclusive OR gate 4
1 and 43 output a logic value 1, but since a logic value O is input to both input terminals of the exclusive OR gates 42 and 44, a logic value 0 is output. Therefore, the selection signal g having a logic value of 0 is output from the gate 22, the decoder 23 is not activated, and the selected circuit 9 is not selected. Next, in order for the microprocessor 1 to select a specific selected circuit 7 in the package 80, an address a=(
x5xx)H, the logic value 1 is transmitted to the terminals A8 and AIO of each pancage 60.80 and 100, and the logic value 0 is transmitted to the terminals A9 and All.
In the same process as described above, only the gate 20 in the package 80 outputs the selection signal g with a logic value of 1 to activate the decoder 21, and the gate 18 in the pan cage 60 and the gate 22 in the package 100 each output a logic value of 0. selection signal g
is output and decoders 19 and 23 are not activated. As a result, the required selected circuit 7 within the pancage 80 is selected. Further, in order for the microprocessor 1 to select a specific selected circuit 9 within the package 100, an address bus 11 is used.
When address a = (XEXX)H is sent to the top, the logic value 0 is transmitted to the terminal A8 of each pancage 60.80 and 100, and the logic value l is transmitted to the terminals A9 to All, so the same process as above is performed. In the process, only the gate 22 in the pan cage 100 outputs the selection signal g with a logic value of 1 and the decoder 2
The gate 18 in the pan cage 60 and the gate 20 in the package 80 each output a selection signal g having a logic value of 0, and the decoders 21 and 23 are not activated. As a result, the required selected circuit 9 within the pancage 100 is selected.

As is clear from the above description (according to this embodiment, the packages 60, 80 and 100 all have the same configuration, and the unique identification codes assigned to each are identified only by the grounding type of the terminals B8 to Bll. Therefore, there is only one type of printed board pancage, which reduces design man-hours and manufacturing costs.

It should be noted that FIG. 2 is merely one embodiment of the present invention; for example, each package 60, 80 and 1o.

The identification code provided is not limited to the one shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case. Also each package 60,
The configurations of 80 and 1oo are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case. Further, the number of packages connected to the address bus is not limited to what is shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

(g) Effects of the Invention According to the present invention, in the electronic device, the number of types of printed board packages required is significantly reduced, which not only makes it possible to reduce design man-hours and manufacturing costs, but also enables maintenance printed boards. Since the number of types of pancage required is drastically reduced, operation and maintenance costs are also significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional address selection circuit, and FIG. 2 is a diagram showing an address selection circuit according to an embodiment of the present invention. In the figure, 1 is a microprocessor, 2 is a continuous memory, 3 is a read/write memory at any time, 4.6, 8.10.6
0.80 and 100 are bread cages, 5.7 and 9 are selected circuits, 11 is an address bus, 12 to 17 are inverters, 18.2o and 22 are gates, 19.21 and 23 are decoders, 24 to 27.33 36 to 41 to '44 are exclusive OR gates, 8 to All
, A and B8 to Bll are terminals, a-(x4xx)H
2a=(X5XX)H and a-(XEXX) are addresses, g is a selection signal, and does not indicate. prisoner l

Claims (1)

[Claims] In an electronic device having a plurality of packages, each of which is given a unique identification code, and the selection is determined by comparing an address transmitted from a microprocessor via an address bus with the identification code, each bit of the identification code is Correspondingly, an exclusive OR gate is provided in each of the packages, the bit corresponding to the identification code of the address transmitted from the address bus is input to one input terminal of the exclusive OR gate, and the other of the exclusive OR gate is The identification code is set by supplying a logic value setting voltage to the input terminals of each through a resistor and connecting each to an external terminal, and grounding the required external terminal, and outputting the exclusive OR gate. An address selection circuit characterized in that it determines the selection of a pan cage.