JPS59105691A - Multiplex drive liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplex liquid crystal display device, and more particularly to a multiplex liquid crystal display device having means for displaying while satisfying the condition that the number of selected pixels on each signal electrode is mutually the same. When multiplex driving a liquid crystal display device, the following holds true in any case. That is, when the scan electrode is selected, the voltage t applied to the scan electrode is
V: +, when a scanning electrode is not selected, the voltage applied to the scanning electrode is Vz; when the signal electrode is selected, the voltage applied to that signal electrode is VY1, when the signal electrode is not selected, the voltage applied to that signal electrode Assuming that the voltage applied to the pixel is fV y, the voltage applied to each pixel during the frame period T is the time series of the following four voltages ■Is■2 p ■3 p ■4 It is made up of a combination of

v,==■π−V Y (1)
v, ==■π−v i (2)y
, == v Z V Y
(3) V, :V King-V Y
(4) Then, the number of scanning electrodes is N1, the signal electrode 1
Assuming that the number of selected pixels on the book is one frame period and the scanning electrode selection period is L, then one frame is selected for each selected pixel on the signal electrode of interest (hereinafter, selected pixels are referred to as P and N). The voltage applied during the period T is made up of the combination of (1) of the period t, (3) of the period (K-1) t, and (4) of the period (N-K) t. In addition, the voltage fL,6 applied during one frame period T to the non-selected pixel C and below on the signal electrode of interest, referred to as the non-selected pixel iPoπ] is
2, period Kt (3), and period (N- to -1) t (4).

Also, T = N i (5).

At this time, the effective voltage applied to the PON (hereinafter referred to as ■) and the effective voltage applied to the PFF (hereinafter referred to as ■OF
The ratio of F is drive -? - Jin (hereinafter referred to as α)
It's called.

Two types of display methods can be considered depending on the magnitude of V ON and V OFF. In other words, there is a display method in which V ON >V oyy and a display method in which V ou (V・FF). Here, the former is called a positive display and the latter is a negative display. α in equation (6) is This is the drive margin in positive display, and the drive margin α1 in negative display is defined as follows.The larger both α and α1 are than 1, the clearer the display will be, and the closer they are to 1, the less clear the display will be.

Now, from what has been said above, the voltage applied to the PON during period T and the voltage applied to P yy vcIEII are
It is known that N and K have an effect. However, V
There is a driving method in which ON and VoFy do not depend on K, and it is called a voltage averaging method. V ON and V O
When FF is affected by K, the display and background become mottled, resulting in a poor quality image. Furthermore, among the voltage averaging methods, the driving method that can obtain a large α is the optimized rt7
It is known that α can be expressed by the following formula, which is called the c voltage averaging method.

As is clear from equation (8), as N increases, α
approaches 1, and the display becomes unclear. This is the limit of N in the voltage averaging method.

If certain conditions are given to the displayed image, a high-quality display may be possible with a driving method that does not rely on voltage averaging. In other words, K is limited to a constant value. For example, if K = 1, ``the condition that there is always one P orT in each @signal electrode, and all other pixels are P QFF'' (hereinafter, this condition is referred to as condition 1) is always satisfied. In this case, a display without crosstalk can be realized by the driving method shown in the time chart of FIG. FIG. 1 shows a time chart when 1J=4. That is, the scan electrode drive voltage VC1~
Apply VC. This VQ, ~vc, means VZ=V
, ■ is nothing but the scanning electrode drive voltage when ==0. On the other hand, a signal electrode drive voltage as indicated by ①S1 is applied to the signal electrode. This V8. For each signal electrode,
Depending on which scan electrode the PON is on, its scan@polar wind voltage should be the same. Therefore, ■Si illustrated in FIG. 1 shows the case where P and N exist on the scanning electrode where vC2 is located. Such a voltage is nothing but the signal electrode drive voltage when ■Y=■ and VY=0. Therefore, in this driving method, ■□-〇(9) ■ ==v (OV, =-
V (11)V,=O(12
), ■The voltage applied to each pixel on the signal electrode where 8t is applied is VCIB, ~Vc, sl.

VC2B17% P is the voltage applied to ON, and V
Cl31, vC381, vC,s, 7'): F
This is the voltage that is applied to the iJD when it is turned off. That is, during l frame period T, P o on the signal electrode of interest
+i is applied during period tI7) and during period (N
-l ) t +7) O (Dm), and the voltages at P OFF K Utoguchi are -■ in period t, -■ in period t, and O in period (N-2) t. Therefore, in this case, P ON , P
aFFic i=1. ] Since the average value of the voltage 7JD is 0 throughout one frame period, there is no superposition of DC voltage. Further, the effective value of n applied to PoN and P@py is as follows. From equations (13) and (14), V ON < V
Since it is OFF, Ne is displayed and the drive margin is
α1- (15) It can be seen that this is a driving method that can produce a high-quality display without bumps or crosstalk.

However, this driving method can only be applied when Condition 1 is always satisfied. FIG. 2 shows the driving method explained in FIG. 1, that is, Vz=V,
By adding K==2 to the driving method when Vx=Q, Vr=V, V; An example is shown below in which the condition is always satisfied.

Therefore, ■c, ~VC, are exactly the same as those shown in FIG. 1, and ■1 to ■4 also become equations (9) to 12. On the other hand, a signal electrode drive voltage as shown by ■s2 is applied to the signal electrode. Each signal electrode is selected at the same time as the scan electrode is selected depending on which scan electrode the PON is on, so the signal electrodes to be focused on here include ■c and vQ. Applying P O on the scanning electrode
The case where N exists is shown. This ■s2 is applied n
The voltage applied to each pixel on the signal electrode is vc, 8'
l to v, number S2.

■C2S2 and ■c4s2 are the PoN [marked 7111 lumi pressures, and Vcl s2b and 70m82 are the voltages applied to P@IFF. That is, 1
During a frame period T, P on the signal electrode of interest
The voltage applied to oii is made of the combination of ■□=0 in period t, V, =V in period t, and V number 20 in period (N-2) t, and is applied to PoFF. The voltage to be calculated is
v,=■ in period t, v3=v in period 2t, and period (N
-3) It is made by combining t with ■4-0. Therefore, in this case, the average value of the voltages applied to P ON and P OFF does not become O throughout one frame period.

Therefore, direct current is superimposed on all pixels, significantly deteriorating the t1 liquid crystal material. In FIG. 2, K-2 has been explained, but it can be easily confirmed that DC is superimposed in the same way in other cases as well. Therefore, conventional V Z = V, V x = O, V Y:
The driving method where V, V; = Q is a method that can only be used when [=1, and in the case of K\1,
Not available.

The purpose of the invention is to solve the above-mentioned drawbacks, and to ensure that each signal electrode always has the same number of P ONs, and that all other pixels
"Condition for ry" (hereinafter, this condition will be referred to as Condition 3)? To provide a multiplex liquid crystal display device in which, when always satisfied, α or α1 is at most 7L1 regardless of the number of scanning electrodes, and the DC component of the voltage applied to each pixel is 0.

Embodiments of the present invention will be described in detail below.

FIG. 3 is a block diagram of a multiplex liquid crystal display device according to a first embodiment of the present invention. period t
A clock voltage with a duty of 1:1 is applied to the input terminal 300. 300 is connected to clock terminals 330 and 340 of the liquid crystal driving voltage generating circuit 33 and the shift register. The shift register 34 has N
Output terminals 341 to 34 N? The output terminal of Izun also outputs logic 1 once every N clocks, and
At any given time, only one output of N rabbits is logic 1 and the other (N-
1) The outputs operate to satisfy logic 0. The liquid crystal drive voltage generation circuit 33 is configured to perform the above-mentioned (1) 2 to (4)
) Formula FC Okel ■ z , V 2 , V'y ,
This is a circuit for generating Vyi, and this V, , VZ
, V x , V y , son (X'n output terminal 33
1. 332, 333, and 334. In the present invention, the following voltage is output. The meanings of equations (, 16) and (18) are: V x = V −1−V,
VY:V for sea bream and mink. So, ■x2V
At the timing of o, ■Y2■10■. This means that Does this ■x or vy take V+Vo■
. Whether the clock voltage of 33oVc input is a logic 1 or a logic 0 determines whether the clock voltage is a logic 1 or a logic 0. The details of the liquid crystal and drive voltage generating circuit 33 that operate in this manner will be explained later.

The scanning electrode drive circuit 31 has N digital input terminals 31.
11 to 311N, two analog input terminals 3101 and 3102, and N analog output terminals 3121 to 31
This is a changeover switch circuit equipped with 2N. The digital input terminal 311$ of the first part and the analog output terminal 3124 of the second part operate correspondingly. That is, by applying a logic 1 or logic 0 voltage to the terminal 311j, the terminal 3101 or 3102 is applied to the terminal 312i.
The analog voltage applied to is selected and output.
) It has become a VC. Each input terminal 3111 to 311N is the output 17iE of the shift register 34.
341 to 34N. t', input terminal 3
101 and 3102 are connected to output terminals 331 and 332 of n1 liquid crystal drive voltage generation circuit 33, respectively. Therefore, the output terminals 3121 to 312N of Izn also output V2+i once every 1q clock, and moreover, [
Only one output out of N is V, and the other (N-1)
・(The output of the solid is every V.

Signal electrode drive circuit 3ItM digital input terminals 32
11 to 321M, two analog input terminals 3203 and 3204, and M analog output terminals 3221 to 32.
2M, and its operation is exactly the same as that of the scan electrode drive circuit 31. That is, the digital input terminal 3214 and the analog output terminal 322i operate correspondingly, and the terminal 321i operates in a corresponding manner.
By applying a logic 1 or logic 0 voltage to
The analog voltage applied to the terminals 320, 311 and 3204 is selectively outputted to the terminal 322i. Input terminals 3203 and 3204 are connected to output terminals 333 and 3 of liquid crystal drive voltage generation circuit 33.
34, when a logic 1 or logic O voltage is applied to the input dancer 321zvc, Vy or vY is output to the output terminal.

The output terminals 3121 to 312N of the scan electrode drive circuit 31 are respectively connected to the scan electrodes 3011 to 3 of the liquid crystal display panel 30.
01N, and the signal electrode drive circuit 3
The two output terminals 3221 to 322M are respectively connected to the signal electrodes 3021 to 302M of the n1 liquid crystal display panel 30. Therefore, it is shown in FIG. Also in the first embodiment of the present invention, each pixel on the liquid crystal display panel 30 has (1
)2 ~ [4) The time-series combination of the four voltages shown in equation 4 reduces stiffness. In non-invention, the valley v z , v
';1, vY, and VY are given by formulas (16) to (19), so ■1 to V4 are expressed as
No. 7 = O(13). Since the frame period T is expressed by the formula (5), P on the (th signal electrode 302) is
If the number of ONs is X, then P ON during one frame period T
The voltage generated by the force is a combination of one cycle of a rectangular wave with an amplitude of 1, a rectangular wave (K-1) with an amplitude of 10, and a voltage of 0 for (N4) cycles. Also, on the same signal electrode 302i, there is a combination of voltage 0 for (N-1) cycles. The duty of these n rectangular waves is l:1. Therefore, in the present invention, VoIq and VoFF satisfy Condition 3.
If the drive is always satisfied, K will be constant and PON
and is constant regardless of the location of POFF; in particular, α is
The number of scanning electrodes N is constant regardless of the number N, so N can be increased without affecting the contrast of the display.
On the diagram! When r-1, Vo=O1N=3, K=1,
An example of the voltage applied to the input terminal of each block in FIG. 3 is shown. ■300 is the voltage applied to the input terminal 300, v311], ~V3113 is the voltage applied to the input terminal 300,
Input terminals 3111 to 31 of the scanning electrode drive circuit 31
Digital voltage applied to 13, V3101~V3
104 is SofiVZ, VW, Vy, V
V6O13 to V3013 are the scanning electrodes 3011 to 3013 of the liquid crystal display panel 30.
is the voltage applied to n. Further, V321i is a digital voltage applied to the input terminal 321i of the signal electrode drive circuit 320, and 302i is a voltage applied to the signal electrode 302i of the liquid crystal display panel. At this time,
The voltage applied to each n pixel intersecting the scanning electrodes 3011 to 3013 on the signal electrode 3ozi is V31i~
It is V33i. V31i and V33i are P.

This is the voltage applied to FF', and ■32 i U P
It is the voltage applied to @N.

FIG. 4 is a block diagram of a multiplex liquid crystal display device which is a second embodiment of the present invention. Liquid crystal display panel 40, scanning electrode drive circuit 41, signal electrode drive circuit 42, liquid crystal drive voltage generation circuit 43, shift register 4
4 is the belly, 30, 31, 32 in Figure 3
, 33 and 34, and the connections between each block are almost the same as in FIG. FIG. 3 shows that a clock voltage input terminal 300 is connected to each of the clock terminals 330 and 340 of the liquid crystal drive voltage generation circuit 33 and the shift register 34, respectively.
In FIG. 4, the clock voltage input terminal 400 is connected only to the clock terminal 440 of the shift register 44,
The clock terminal 430 of the liquid crystal drive voltage generation circuit 43 is connected to the blade terminal 44N of the shift register 44 and a T-type flip.

It is connected via a flop 45. 450 and 45
1 is a T-type flip. These are the T input terminal and Q output terminal of the flop 45. Other connections are the same in both FIGS. 3 and 4. Terminal 3 of Sonozo in Figure 3
011-3011J, 3021-302M13101.
3102, 3111-311N, 3121-312N,
3203, 3204, 3211~321M, 3221~
322M, 331-334.340.341-341 (
are the terminals 4011 to 401N of the terminals in Figure 4.
, 4021-402M, 4101.4102.411
1~411N, 4121~412N, 4203,420
4.4211~42.1M, 4221~422M
, 431-434. Same as 440, 441-44N. Therefore, in the second embodiment as well, vz, v, i,
vY* ■” u (16) n given by equations 2 to (19)
However, whether V or My takes V-1-Vo-1 or vo is determined by whether the clock voltage input to the input terminal 400 becomes logic 1 or logic 0. Instead, ``v0'' and ``■'' are output alternately every frame period T. Therefore, in the second embodiment, every frame period T K F @N , n applied to POFF
When discussing the voltage, the voltage is biased across the current, but when discussing the period 2T, n is PON.

Since the polarity of the voltage at P OFF is reversed every cycle T, the voltage becomes 0 in the cycle 2T. ■, ~■4 are also given by equations (20) to (23) in this case, and VON, VoIPT? ,
a'' is also given by equations (24) to (26). In Fig. 6, when Vo = Q, N = 3, and = l, the voltage applied to each block in Fig. 4 is shown. An example of voltage is shown: v400,
V411-V4113, V430. V4101, V4
102. V4203. V4204. V4011~V40
13, V421j, V402? -, V41j~V4
34 are input terminals 400, 4111 to 4113
．． t30, 4101, 4102, 4203.4204.
4011-4013.421ffl, 402j, 41
The voltage ranges from 1 to 43i. v41 i>
42i is the voltage applied to PON.

The scan electrode drive circuits 31 and 41 and the signal electrode drive circuits 32 and 42 may have similar circuit configurations. The diagram for one scanning electrode or signal electrode is shown in FIG.

70 is a change-over switch circuit; the output terminal 74 is connected to the input terminal 71 or 72 depending on whether the digital voltage input to 73 is logic 1 or logic O; A circuit that operates in this manner can be easily realized by using an analog switch or the like.

′=! In addition, the liquid crystal drive voltage generation circuits 33 and 43 are connected to the eighth
This can be easily realized with the circuit configuration shown in the figure. The input terminal 7 is
331 and 431 of the n1 liquid crystal drive voltage generation circuit
, 333 and 433.332 and 432.334 and 434. Outputs DC voltage at the output end.

80 is constituted by a circuit including two changeover switches. When the n1 clock terminal 88 is logic 1, the output terminal 84 is connected to the input terminal 81 and outputs a voltage vl, and the output terminal 85 is connected to the input terminal 82. n and outputs a voltage O. Further, when the clock terminal 88 is at logic O, the output terminal 84 is connected to the input terminal 82 and outputs the voltage O, and the output terminal 85 is connected to the input terminal 81 and outputs the voltage V.
Output. 80 can also be simply configured by buffer circuits 9C and 1°902 and an inverter circuit 903, as shown in FIG. Each terminal 9 in Figure 9
1, 92.94, 95.98 are each terminal 81 in FIG.
, 82.84, and 85.88.

As described above, according to the present invention, when driving the liquid crystal display panel while always satisfying condition 3, the DC voltage is not superimposed on each pixel, and the PON and PON It is possible to provide a multiplex liquid crystal display device in which Voy and VoFy are independent regardless of the OFF position, and α is increased regardless of N.

[Brief explanation of drawings]

1 and 2 are time charts of the main parts of a conventional multiplex liquid crystal display device, FIGS. 3 and 4 are block diagrams of an embodiment of the multiplex liquid crystal display device of the present invention, and FIGS. Fig. 6 is a time chart of the main parts applied to the multiplex liquid crystal display device of the invention, Fig. 7 is a circuit diagram showing an example of the internal circuitry per output of the scanning electrode drive circuit and the signal electrode drive circuit, and Fig. 8 The figure is a circuit diagram showing an example of a liquid crystal overload voltage generation circuit.
8 is a circuit diagram showing an example of the internal circuit of block 80 in FIG. 8. 30.40°. Liquid crystal display panels 3011-301N, 4011-401N. . Scanning voltages 3021-302M, 4021-402M,. Signal electrode 31.41', scanning electrode drive circuit 32.42°. Signal electrode drive circuit Figure 1 Vc2s+. 21￥1 C452-17 Figure S

Claims (1)

[Claims] A liquid crystal display panel including a plurality of scanning electrodes and a plurality of signal electrodes, a scanning electrode drive circuit, and a signal electrode drive circuit, wherein the number of selected pixels on each signal electrode is mutually In a multiplex drive liquid crystal display device having means for displaying while always satisfying the same conditions, a voltage of -10 volts is applied to scan electrodes and signal electrodes in a non-selected state. is applied n
At the same time, the scan electrode and signal electrode in the selected state are
At the timing when the voltages v-4-vo are applied to the scanning electrodes, a voltage (2) is applied to the signal electrodes. A voltage ■ is applied to the r1 scan electrode. Voltage v+■o is applied to the id signal electrode at the timing when n is applied.
A multiplex drive liquid crystal display device, characterized in that it has means for applying a voltage.