JPS59104649U - Ｄｍｉ符号化回路 - Google Patents

Ｄｍｉ符号化回路

Info

Publication number
JPS59104649U
JPS59104649U JP1982197848U JP19784882U JPS59104649U JP S59104649 U JPS59104649 U JP S59104649U JP 1982197848 U JP1982197848 U JP 1982197848U JP 19784882 U JP19784882 U JP 19784882U JP S59104649 U JPS59104649 U JP S59104649U
Authority
JP
Japan
Prior art keywords
dmi
encoding circuit
circuit
converted
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1982197848U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0119485Y2 (cg-RX-API-DMAC7.html
Inventor
彰 宮内
曽根辻　昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1982197848U priority Critical patent/JPS59104649U/ja
Publication of JPS59104649U publication Critical patent/JPS59104649U/ja
Application granted granted Critical
Publication of JPH0119485Y2 publication Critical patent/JPH0119485Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Optical Communication System (AREA)
JP1982197848U 1982-12-28 1982-12-28 Ｄｍｉ符号化回路 Granted JPS59104649U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982197848U JPS59104649U (ja) 1982-12-28 1982-12-28 Ｄｍｉ符号化回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982197848U JPS59104649U (ja) 1982-12-28 1982-12-28 Ｄｍｉ符号化回路

Publications (2)

Publication Number Publication Date
JPS59104649U true JPS59104649U (ja) 1984-07-14
JPH0119485Y2 JPH0119485Y2 (cg-RX-API-DMAC7.html) 1989-06-06

Family

ID=30423363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982197848U Granted JPS59104649U (ja) 1982-12-28 1982-12-28 Ｄｍｉ符号化回路

Country Status (1)

Country Link
JP (1) JPS59104649U (cg-RX-API-DMAC7.html)

Also Published As

Publication number Publication date
JPH0119485Y2 (cg-RX-API-DMAC7.html) 1989-06-06

Similar Documents

Publication Publication Date Title
JPS59104649U (ja) Ｄｍｉ符号化回路
JPS5823432U (ja) 雑音抑圧回路
JPS59164332U (ja) バンド切換え回路
JPS58123626U (ja) Ａ／ｄ変換器ノイズ除去装置
JPS6092348U (ja) キ−入力装置
JPS58107633U (ja) 出力回路
JPS59144931U (ja) ラツチドコンパレ−タ
JPS6013591U (ja) 表示制御回路
JPS5927633U (ja) デイジタルｉｃ
JPS5823433U (ja) 雑音抑圧回路
JPS58123622U (ja) 遅延線
JPS58186633U (ja) スイツチヤ−制御回路
JPS58119239U (ja) 出力ラツチ回路
JPS5972035U (ja) 有極信号受信装置
JPS5991051U (ja) ノイズブランカ回路の表示装置
JPS5996610U (ja) バス異常検出回路
JPS5885814U (ja) 信号伝送回路
JPS59118036U (ja) デ−タ入力回路
JPS6035636U (ja) 反転禁止モ−ドを有するフリップフロップ回路
JPS6025037U (ja) 入力インタフエイス回路
JPS58194520U (ja) ゲインコントロ−ル回路
JPS604021U (ja) Ｌｓｐ型パラメトリツクイコライザ
JPS5893046U (ja) 半導体論理回路
JPS5850556U (ja) ２値化回路
JPS5984945U (ja) 信号伝送システムの入力回路