JPS59101097A - Bit error processing method of storage device - Google Patents

Abstract

PURPOSE:To discriminate suitably if a bit error comes into an important fault by checking whether or not there exists an error in the same bit of prescribed other addresses as a bit having the error in detecting a bit error in an address. CONSTITUTION:When a bit error is detected as to an address N1 of a memory 1 by an error check controller 2 and the bit number is >=2-bit, an alarm signal is raised and the processing is finished. When the bit number is (1), whether or not there exits the bit error as to addresses other than the address N1 is checked. When no error is detected, the error bit of the address N1 is corrected for itself. When the error is detected, whether or not the error bit is the same as that of the address N1 is discriminated. When the same, since it is highly possible that the error is an important fault, an alarm signal is generated. When not the same, the error is corrected by itself and the error processing is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bit error processing method for a storage device, which detects a bit error in a storage device and performs processing based on the content of the error.

[Technical background of the invention and its problems]

Conventionally, there are the following methods for handling bit errors in storage devices. If a bit error is detected in another bit of a certain address, self-correction is performed using parity bits, etc., and if a bit error is detected in two or more bits, self-correction is performed. It is impossible to correct and generates an alarm signal as it may lead to the failure of the entire storage device,
The operator was informed. On the other hand, the memory IT generally has the configuration shown in FIG.
vtt, . . . , Mn are configured corresponding to each bit in all addresses. For this reason, if a memory chip is out of order, a bit error will occur in only a specific bit of each address.

However, in conventional methods, inspection focuses only on the address where a bit error has occurred, so even if a memory chip is malfunctioning, it cannot be detected, which may lead to a malfunction of the entire storage device. A certain initial failure could not be discovered.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a storage device bit error handling method that can appropriately determine whether a bit error in a storage device will lead to a serious failure. do.

[Summary of the invention]

In order to achieve this object, the bit error processing method for a storage device according to the present invention is such that when a certain address in a storage device is checked for a bit error, the bit error occurs in a predetermined address other than the above address. It is characterized by checking whether a bit error has occurred in the same bit as the bit, and generating an obituary signal if a bit error has occurred in the same bit.

[Embodiments of the invention]

As shown in FIG. 2, the storage device to which the present invention is applied is comprised of a memory 1 for storing various data and an error check controller 2 for performing error checking. A write data bus 4, a read data bus 5, and a check bit bus 6 are connected between the memory 1 and the error check controller 2. A light mode control line 9 is connected. Note that data is exchanged between the memory 1 and other devices (not shown) via a memory data bus 3.

A bit error processing method according to an embodiment of the present invention will be described with reference to FIG. When the error check controller 2 detects a bit error in address N1 of memory 1 (block 101), it checks the number of bits of the bit error (block 102). If it is 2 or more bits, self-correction is difficult, so the block 10
Step 6 then generates an alarm signal and ends the bit error processing. If the number of bits in the bit error is 1, it is checked whether a bit error has occurred in an address other than the address N1 where the bit error was detected (block 103). If no bit error is detected, address N is detected in block 107.

self-corrects error bits. If a bit error is detected, it is determined whether the ten error bits are the same as address N (block 105).

If they are the same, there is a high possibility that there is a failure in the memory chip associated with that bit or a serious failure such as a failure in the data bus line, so an alarm signal is generated (block 106) to notify the operator. If they are not the same, it is likely that the failure is not serious as described above, and the error processing is then self-corrected (block 107).

It is desirable that all addresses other than the address N1 be tested in block 103, but each predetermined address may be selected and tested, and in this case, the testing time is shortened. When the memory 1 has a large capacity, it is expanded as shown in FIG. 4, and each bit is composed of a plurality of memory chips. For example, beep) 0 is a memory chip M11゜M! 1. . . . Consists of m memory chips of e Mml. Therefore, the addresses to be checked in block 103 may be only those memory chips that include address N, which has been checked for bit errors.

For example, in the case of N≦N, 52N-1, it is sufficient to check only the range from address N to address 2N-1.

Note that the specific processing for bit errors is not limited to self-correction or alarm signal generation processing, but may be other known processing. For example, an extra dummy memory chip may be prepared in advance, and when a memory chip fails, this dummy memory chip may be automatically replaced with the failed memory chip.

〔Effect of the invention〕

In summary, according to the present invention, it is possible to appropriately determine whether a bit error in a storage device is likely to lead to a serious failure, and to process the error.

[Brief explanation of drawings]

1 and 4 are plan views showing specific examples of the structure of a memory chip of a storage device to which the present invention is applied, FIG. 2 is a block diagram of the same device, and FIG. 3 is an embodiment of the present invention. 2 is a flowchart of a bit error processing method according to the present invention. l...Memory, 2...Error check controller, 3...Pass line, M,, M,, -, Mn, M,
,,Ml,. ..., Mrnn...Memory chip. Applicant's agent Kiyoshi Inomata Figure H Figure 2 Figure 3 U/ Go to Figure 4 To
01-------'---π-1

Claims (1)

[Claims] In a bit error processing method for a storage device that detects a bit error in the storage device and performs correction processing, when a bit error is detected at a certain address in the storage device, a predetermined error at a predetermined address other than the above address is detected. The storage device is characterized in that the storage device detects whether or not a bit error has occurred in the same bit as the bit in which the bit error has occurred in the address that has been received, and generates an alarm signal when a bit error has occurred in the same bit. Bit error handling method.