JPS59100948A - Communication circuit system - Google Patents

Communication circuit system

Info

Publication number
JPS59100948A
JPS59100948A JP57211872A JP21187282A JPS59100948A JP S59100948 A JPS59100948 A JP S59100948A JP 57211872 A JP57211872 A JP 57211872A JP 21187282 A JP21187282 A JP 21187282A JP S59100948 A JPS59100948 A JP S59100948A
Authority
JP
Japan
Prior art keywords
terminal
switching
signal
host processor
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57211872A
Other languages
Japanese (ja)
Inventor
Tetsushige Ihara
井原 哲茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57211872A priority Critical patent/JPS59100948A/en
Publication of JPS59100948A publication Critical patent/JPS59100948A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

PURPOSE:To share a communication circuit and to connect with switching plural terminal devices to a host processor by detecting a terminal switching signal by the host processor and connection switching device provided among plural terminal devices and discriminating the terminal device. CONSTITUTION:The data signal and the terminal indicating signal supplied from a host processor are supplied to a serial-parallel converting part SP of a terminal switching part K from a terminal T1 via a communication circuit of a single system and an MODEM M'. These signals are converted into parallel data signals and supplied to registers R1 and R2. The terminal indicating signals ESC and DCn (n=1, 2) stored in the registers R1 and R2 are detected at a detecting part F, and the terminal device to be selected is discriminated. Then switching signals are transmitted to a switching circuit J1 and a switch J2. If a display device TM1 is selected, the data signal is displayed to the device TM1 from the data signal D1 following the terminal indicating signal via the circuit J1, a register R3 and a parallel-serial converting part PS1 respectively. If a sound output device TM2 is selected, the data signal is delivered via the circuit J1, a register R4 and a parallel-serial converting part PS2.

Description

【発明の詳細な説明】 (A)  発明の技術分野 本発明はホストコンピュータと複数の端末装置を通信回
線を介して接続した通信回線7ステムに関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a communication line 7 system in which a host computer and a plurality of terminal devices are connected via a communication line.

(BJ  技術の背景 電子計鼻機の有効利用のだめに1つのポストプロセッサ
に複数の端末装置を接続し、これら端末装置との間で、
データの授受を行うことは広く行われている。
(BJ Technology Background In order to make effective use of electronic nasal meters, multiple terminal devices are connected to one post-processor, and between these terminal devices,
Exchanging data is widely practiced.

とくにファクシミリの分野では、ホストプロセッサと端
末装置とは通信回線を介して接続されておシ1通信回線
の有効利用を図ることが望まれる。
Particularly in the field of facsimile, it is desirable to connect a host processor and a terminal device via a communication line to make effective use of the communication line.

(0)  従来技術と問題点 第1図に示すように従来はホストプロセッサHに2系統
の通信回線と、これらに各々端末装置TM、、TM2 
が接続されている。
(0) Prior Art and Problems As shown in Figure 1, in the past, the host processor H has two communication lines, and these are connected to terminal devices TM, TM2, respectively.
is connected.

これら各通信回線には、通信回線アダプタA1゜A2.
モデムMI + Ml’ + M! t M、l が接
続されている。
Each of these communication lines is connected to a communication line adapter A1, A2.
Modem MI + Ml' + M! t M,l are connected.

端末装置TM、とホストプロセッサHの間のデータの授
受は、送受信されるべきデータの送受信操作開始及び停
止機能、パリティビット付与機能を有するアダプタAI
、データの変復調を行うモデムM12M1′を介して行
われる。
Data is exchanged between the terminal device TM and the host processor H using an adapter AI that has functions for starting and stopping the transmission and reception of data to be transmitted and received, and a function for adding parity bits.
, via a modem M12M1' that modulates and demodulates data.

端末装置TM、とホストプロセッサHの間のデータの授
受は同様にアダプタA1.モデムM2 + M2’を介
して行われる。
Similarly, data is exchanged between the terminal device TM and the host processor H using the adapter A1. This is done via modem M2 + M2'.

しかしこのようなシステムでは、各端末装置ごとに通信
回線を設けるため、システムが大型化し、かつ通信回線
の有効な利用が図られない欠点があった。
However, in such a system, since a communication line is provided for each terminal device, the system becomes large and the communication line cannot be used effectively.

(D)  発明の目的 本発明はかかる従来の欠点に鑑みなされたもので、通信
回線を共用して、複数の端末装置をホストコンビーータ
に切換え接続し得る通信回線システムを提供することを
目的とする。
(D) Purpose of the Invention The present invention was made in view of the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a communication line system that can share a communication line and switch and connect a plurality of terminal devices to a host converter. do.

(1)  発明の構成 そしてこの目的は本考案によれば、ホストプロセッサと
、該ホストプロセッサに通信回−を介して接続される複
数の端末装置とを備えている通信回線システムにおいて
、前記ホストプロセッサと複数の端末装置間に端末装置
接続切換装置を設け、該端末装置接続切換装置は、前記
通信回線を介して授受されるデータを格納するレジスタ
と、該レジスタに格納されるデータから端末切換用信号
を検出し、該端末切換用データによシ指定される端末装
置を判別する検出部と、該検出部の出力によシ前記回線
を切換接続する切換部とを有することを特徴とする通信
回線システムを提供することにより達成される。
(1) Structure and object of the invention According to the present invention, in a communication line system comprising a host processor and a plurality of terminal devices connected to the host processor via a communication line, the host processor A terminal device connection switching device is provided between the terminal device and the plurality of terminal devices, and the terminal device connection switching device includes a register for storing data sent and received via the communication line, and a terminal device connection switching device for terminal switching based on the data stored in the register. A communication device comprising: a detection unit that detects a signal and determines a terminal device specified by the terminal switching data; and a switching unit that switches and connects the line based on the output of the detection unit. This is achieved by providing a line system.

(F)  発明の実施例 以下図面を参照して本発明の実施例を詳述する。(F) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

82図は本発明の実施例構成図であって、第1図と同等
部分には同一符号を付した。
FIG. 82 is a configuration diagram of an embodiment of the present invention, in which parts equivalent to those in FIG. 1 are given the same reference numerals.

第2図において、Aは通信回線アダプタ、楊。In FIG. 2, A is a communication line adapter.

M′はモデム、Kは端末切換部である。M' is a modem, and K is a terminal switching section.

端末装at TMt * TMtは表示装置および音声
合成装置である。
The terminal device at TMt*TMt is a display device and a speech synthesizer.

第3図は切換部にの構成図である。FIG. 3 is a configuration diagram of the switching section.

モデムM′ を介してホストプロセッサから端子T1 
へ人力された端末指示信号およびデータ信号は、直並列
変換部spへ入力し、並列データ信号に変換される。
from the host processor via modem M' to terminal T1.
The terminal instruction signal and data signal inputted manually are input to the serial/parallel converter sp and converted into parallel data signals.

信号は第4図に示すように、端末指示信号gs。The signal is a terminal instruction signal gs as shown in FIG.

とDo、又はDC,およびデータ信号DI+D!・・・
・・Dnからなる。
and Do, or DC, and data signal DI+D! ...
...consists of Dn.

これらの信号ff1s O,DOn(n−1,2)、D
、、D2・・・・・Dmは並列に変侠されて、各々レジ
スタR1,R2に入力される。
These signals ff1s O, DOn(n-1, 2), D
, D2 . . . Dm are changed in parallel and input to registers R1 and R2, respectively.

このうちレジスタR,,,R2に端末指示信号FISe
Of these, registers R, , R2 have terminal instruction signals FISe.
.

Dom(n−1,2)が格納されると検出部Fで検出さ
れ、いずれの端末装置が選択されるべきかを判別し、切
換回路J1及び切換器J2に切換信号を送出する。
When Dom(n-1, 2) is stored, it is detected by the detection unit F, which terminal device is determined to be selected, and a switching signal is sent to the switching circuit J1 and the switching device J2.

最初に、表示装置TM、  が選択されると、切換回路
J、を経由して、まず端末指示信号に続くデータ信号D
IがレジスタR8に入力され、レジスタR1にはデータ
信号D2 が入力される。なお端末指示信号は端末切換
部Kからは出力されない。
First, when the display device TM is selected, the data signal D following the terminal instruction signal first passes through the switching circuit J.
I is input to register R8, and data signal D2 is input to register R1. Note that the terminal instruction signal is not output from the terminal switching section K.

クロック周期単位にデータ信号が++*仄端末装置側へ
転送され、並直列変換部ps1で直列信号に変換されて
端子Tt に現れる。このデータ信号は表示装置TM、
へ入力されて表示に供される。
The data signal is transferred to the terminal device side in units of clock cycles, converted into a serial signal by the parallel-to-serial converter ps1, and appears at the terminal Tt. This data signal is transmitted to the display device TM,
is input to and displayed.

他方、切換器J2はこの場合、表示装置側の端子T3と
、モデムM′側の端子T4 が接続される如く、検出部
Fの制御によシ切換えられる。従ってオペレータはホス
トプロセッサHが出力されたデータ信号による表示に応
じて、新たな要求信号をキーボードを介してホストプロ
セッサHに端子T3+切換器J2r端子′I4 を経由
して入力できる。
On the other hand, in this case, the switch J2 is switched under the control of the detector F so that the terminal T3 on the display device side and the terminal T4 on the modem M' side are connected. Accordingly, the operator can input a new request signal to the host processor H via the keyboard via the terminal T3+switcher J2r terminal 'I4 in response to the display by the data signal output from the host processor H.

ホストプロセッサHはこの端末装置側からの要求信号に
対応して新たなデータ信号を前述した操作により伝達す
る。
In response to this request signal from the terminal device side, the host processor H transmits a new data signal by the above-described operation.

このようにして、ホストプロセッサHと表示装gTM、
との間の信号の授受が行われる。
In this way, the host processor H and the display device gTM,
Signals are exchanged between the two.

なお、音声出力装置TM、とホストプロセッサHとを接
続する場合も同様の操作によって行うことができ、端末
指示信号[k30. Don(n=1 、2)として音
声出力装d’rm*を選択する信号を用いれば、レジス
タR,,R,に収納された信号は切換部J。
Note that the same operation can be used to connect the audio output device TM and the host processor H, and the terminal instruction signal [k30. If a signal for selecting the audio output device d'rm* is used as Don (n=1, 2), the signals stored in the registers R, , R, will be transferred to the switching unit J.

を介してレジスタR4+並直列変換部Pa、へ入力され
、ここで直列信号に変換されて、端子T、に現れる。
The signal is inputted to register R4+parallel-serial converter Pa through register R4, where it is converted into a serial signal and appears at terminal T.

この信号は音声出力装置TM、へ入り、音声出力される
This signal enters the audio output device TM and is output as audio.

この場合、切換器J2 は、音声装置TM、側に接続さ
れており、音声出力の終了信号が端子T6.切mdiJ
21端子T4  を経由してホストプロセッサHに伝達
される。
In this case, the switch J2 is connected to the audio device TM, and the audio output end signal is sent to the terminal T6. Cut mdiJ
The signal is transmitted to the host processor H via the 21 terminal T4.

なお、Lはクロック信号源、Nはクロック信号を受けて
、レジスタRl−R4+直並列変換回路SP。
Note that L is a clock signal source, and N is a register R1-R4+serial-to-parallel conversion circuit SP that receives the clock signal.

並直列変換回路PS、 、 PB、における指示16号
、データ信号の転送制御を行う制御部である。
Instruction No. 16 in the parallel-to-serial conversion circuits PS, PB, is a control unit that controls the transfer of data signals.

(G)  発明の詳細 な説明したよりに本発明に係る通信回緋シスデムは、ホ
ストプロセッサと端末装置との間で授受される信号によ
り、回線接続を切換え制御できるため、多数の端末装置
を同一回線を用いてホストプロセッサと接続でき、シス
テム構成が簡単なものとなる。
(G) Detailed Description of the Invention As described above, the communication line system according to the present invention can switch and control line connections by signals sent and received between the host processor and the terminal devices, so that many terminal devices can be connected to the same terminal. It can be connected to the host processor using a line, simplifying the system configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のシステム構成図、第2図は本発明の実施
例構成図、第3図は切換部の構成図、第4図は信号構成
図である。
FIG. 1 is a conventional system configuration diagram, FIG. 2 is an embodiment configuration diagram of the present invention, FIG. 3 is a configuration diagram of a switching section, and FIG. 4 is a signal configuration diagram.

Claims (1)

【特許請求の範囲】[Claims] ホストプロセッサと、該ホストプロセッサに通信回線を
介して接続される複数の端末装置6とを備えている通信
回線システムにおいて、前記ホストプロセッサと複数の
端末装置の間に端末装置接続切換装置を設け、該端末装
置接続切換装置は、前記通信回線を弁して、授受される
データを格納するレジスタと、該レジスタに格納される
データから端末切換用信号を恢出するとともに該端末切
換用データによシ指定される端末装置を判別する検出部
と、該検出部の出力により前記回線を切換接続する切換
部とを有することを特徴とする通信回線システム。
In a communication line system comprising a host processor and a plurality of terminal devices 6 connected to the host processor via a communication line, a terminal device connection switching device is provided between the host processor and the plurality of terminal devices, The terminal device connection switching device has a register that valves the communication line and stores data to be sent and received, and a terminal switching signal that is generated from the data stored in the register and a terminal switching device that uses the terminal switching data. 1. A communication line system comprising: a detection unit that determines a designated terminal device; and a switching unit that switches and connects the line based on the output of the detection unit.
JP57211872A 1982-12-02 1982-12-02 Communication circuit system Pending JPS59100948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57211872A JPS59100948A (en) 1982-12-02 1982-12-02 Communication circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57211872A JPS59100948A (en) 1982-12-02 1982-12-02 Communication circuit system

Publications (1)

Publication Number Publication Date
JPS59100948A true JPS59100948A (en) 1984-06-11

Family

ID=16613008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57211872A Pending JPS59100948A (en) 1982-12-02 1982-12-02 Communication circuit system

Country Status (1)

Country Link
JP (1) JPS59100948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61246856A (en) * 1985-03-27 1986-11-04 Fujitsu Ltd File transfer terminal device
JPS6364427A (en) * 1986-09-05 1988-03-22 Nec Corp Remote switching system for data transmitting/receiving circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61246856A (en) * 1985-03-27 1986-11-04 Fujitsu Ltd File transfer terminal device
JPS6364427A (en) * 1986-09-05 1988-03-22 Nec Corp Remote switching system for data transmitting/receiving circuit

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