JPS5899810U - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5899810U JPS5899810U JP19300281U JP19300281U JPS5899810U JP S5899810 U JPS5899810 U JP S5899810U JP 19300281 U JP19300281 U JP 19300281U JP 19300281 U JP19300281 U JP 19300281U JP S5899810 U JPS5899810 U JP S5899810U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit device
- substrate
- ferrite cores
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Coils Or Transformers For Communication (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、一般的に鉄損により生ずるコア断面における
温度分布を示す図、第２図は、コアの中央部に熱伝導性
の良好な絶縁板を挾んだ場合のコア断面における温度分
布を示す図、第３図は、本考案の一実施例の略図、第４
図は、要部の構成を示す斜視図である。
３・・・アルミナ基板、４．５・・・電源変圧器等の一
路部品、６． ７． ８・・・その他回路部品、１１ａ
。
・ ｌｌｂ・・・フェライトコア、１２・・・９＆溝、
１３・・・ボビン。Figure 1 shows the temperature distribution in the cross section of the core that generally occurs due to iron loss, and Figure 2 shows the temperature distribution in the cross section of the core when an insulating plate with good thermal conductivity is sandwiched in the center of the core. FIG. 3 is a schematic diagram of an embodiment of the present invention, and FIG.
The figure is a perspective view showing the configuration of main parts. 3...Alumina substrate, 4.5...One-way components such as power transformers, 6. 7. 8...Other circuit parts, 11a
.・llb...ferrite core, 12...9 & groove,
13...Bobbin.
Claims (1)
を挾むようにして両面からフェライトコアを重ね合わせ
、これに巻線を施してなる回路部品を具備したことを特
徴とするハイブリッド集積回路素子。1. A hybrid integrated circuit element comprising a circuit component made of a ceramic substrate having good thermal conductivity, ferrite cores stacked on both sides of the substrate so as to sandwich a part of the substrate, and a wire wound on the ferrite cores.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19300281U JPS5899810U (en) | 1981-12-28 | 1981-12-28 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19300281U JPS5899810U (en) | 1981-12-28 | 1981-12-28 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5899810U true JPS5899810U (en) | 1983-07-07 |
Family
ID=30106377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19300281U Pending JPS5899810U (en) | 1981-12-28 | 1981-12-28 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5899810U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0332408U (en) * | 1989-08-09 | 1991-03-29 |
-
1981
- 1981-12-28 JP JP19300281U patent/JPS5899810U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0332408U (en) * | 1989-08-09 | 1991-03-29 |
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