JPS5897914A - Terminal handling method of surface acoustic wave filter - Google Patents
Terminal handling method of surface acoustic wave filterInfo
- Publication number
- JPS5897914A JPS5897914A JP56197084A JP19708481A JPS5897914A JP S5897914 A JPS5897914 A JP S5897914A JP 56197084 A JP56197084 A JP 56197084A JP 19708481 A JP19708481 A JP 19708481A JP S5897914 A JPS5897914 A JP S5897914A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- plated
- bonding
- nickel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は結晶叛の表面波伝播を応用した高周波＊＠累子
に係り、特に周波数領域の拡大化に対処するフィルタチ
ップとチップ外装端子となるリードフレームあるいはキ
ャンタイプステムとの接続手段を改良した表面波フィル
タの端子処理方法に（２）従来技術と問題点
従来のＬＣフィルタを集積化、固体化した表面波フィル
タは各種の通信機器やＴＶ受像機に賞月されている。表
面波フィルタは例えば、＠１図図示の組立体を樹脂外装
構成のＳＩＰ容器（ＳｉｎｇｌｅＩｎ−１ｉｎｅ Ｐａ
ｃｋａｇ＠５’を略してＳＩＰと呼ぶ）に収めるか、又
は第２図の気密性の高い外装答＠Ｔ。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a high frequency*@resonator that applies the surface wave propagation of a crystal, and in particular to a filter chip and a chip exterior terminal that cope with the expansion of the frequency range. (2) Conventional technology and problems Surface wave filters that integrate and solidify conventional LC filters can be used in various communication devices and other devices. The award was given to the TV receiver. For example, the surface wave filter can be used in a SIP container (SingleIn-1inePa
ckag@5' is abbreviated as SIP) or in a highly airtight exterior case as shown in Figure 2.
−８に収納する。- Store in 8.
本発明は係る実装画工１￥における組立、フィルタチッ
プ２と外部リード端子との超背波ボンディング接続に係
シ、特に外部リード端子の表面処理につき提示するもの
である。The present invention relates to the assembly in the mounting process 1 and the ultrabackwave bonding connection between the filter chip 2 and the external lead terminals, and particularly to the surface treatment of the external lead terminals.
従来、外部リード端子の表面処理は、端子リード予形成
のリードフレーム１と、該フレームを担体砿とし表面に
貼着載置したフィルタチップ２の電極形成部６とのボン
ディング接続の接続強度を高くとることから全面ニッケ
ルめっきとしていた（第１図＃１ｆｅＤ。しかしながら
、表面波フィルタの適用周波数ｆ領域が３０ＭＨｚもし
くはそれ以上とな面のニッケルは端子伝播抵抗が次式の
表皮厚さハにより増大し、表面波フィルタに対する誘導
レベルが所論する。Conventionally, the surface treatment of external lead terminals has been carried out to increase the strength of the bonding connection between the lead frame 1 on which the terminal leads are preformed and the electrode forming portion 6 of the filter chip 2, which is attached to the surface of the lead frame 1 using the frame as a carrier rod. Therefore, the entire surface was nickel plated (Fig. 1 #1feD. However, the terminal propagation resistance of nickel on the surface where the surface wave filter's applicable frequency f region is 30 MHz or higher increases due to the skin thickness c in the following equation. , the induction level for the surface wave filter is discussed.
１ 式中、σは導（４、μは透磁率である。1 where σ is conductivity (4) and μ is magnetic permeability.
つまり、ニッケルはボンディング強度は高いが強磁性体
μ≧１００（μｍａｘ＝４００）であるため不都合で
ある。That is, although nickel has high bonding strength, it is inconvenient because it is a ferromagnetic material μ≧100 (μmax=400).
（３）発明の目的
端子リードの前記の表皮厚さを従来に比し１桁以下低減
させ、前記リード端子の伝播抵抗を低減することにある
。(3) An object of the invention is to reduce the skin thickness of the terminal lead by one order of magnitude or less compared to the conventional one, thereby reducing the propagation resistance of the lead terminal.
（４）発明の構成
少くともリードフレームのボンディング面ハニッケルめ
っ急がされ、前記リード端子面は銀又は銅何れかのめつ
き処理がされていることを％徴とするリード端子の処理
方法である。(4) Structure of the Invention A lead terminal processing method characterized in that at least the bonding surface of the lead frame is hard-nickel-plated, and the lead terminal surface is plated with either silver or copper. be.
（５）発明の実施例
、Ｉｔ図と第２図は、基本的累子形成完了後のフィルタ
チップとＳＩＰ端子形成のリードフレームとをボンディ
ング接続する正面図、及びＴＯ−８形キヤン用ステムに
前記同様のフィルタチップをボンディング接続する斜視
図である。(5) Embodiment of the invention, It diagram and Fig. 2 are front views showing the bonding connection between the filter chip and the lead frame for SIP terminal formation after the basic resistor formation is completed, and the stem for the TO-8 type can. It is a perspective view of bonding connection of the filter chip similar to the above.
第１図において、１は燐青銅等バネ材と打抜きしたリー
ドフレーム、２はリードフレームにダイシングされたフ
ィルタチップ、該チップ２内の３はフィルタ入力部のす
だれ状電極形成部、４は出力部をなすすだれ状ｍ極形成
部及び５は入出力間すだれ状′成極間に設ける伝送波面
の強度を一様に揃えるマルチストリッグカプラ、及び６
と７は共に前記フィルタチップに設けたボンディング電
極、６は入出力用の電極又７は接地電極である。In Fig. 1, 1 is a lead frame punched out from a spring material such as phosphor bronze, 2 is a filter chip diced into the lead frame, 3 in the chip 2 is a section for forming interdigital electrodes at the filter input section, and 4 is an output section. 5 is a multi-string coupler that uniformizes the intensity of the transmission wavefront provided between the input and output interdigital m-poles, and 6
and 7 are bonding electrodes provided on the filter chip, 6 is an input/output electrode, and 7 is a ground electrode.
図示状態にダイシングされたフィルタチップは超音波ボ
ンディング法により、前記各磁極とリードフレームの端
子リード９間を最短距離に細アルミワイヤ８が布縁式れ
る。A thin aluminum wire 8 is attached to the filter chip diced as shown in the figure by an ultrasonic bonding method in the shortest distance between each magnetic pole and the terminal lead 9 of the lead frame.
本発明は、リードフレーム１の剖紀ボンディング被５ｉ
ｉＦ部のみ限定し、強度が高いニッケルめっきを施し、
前記ボンディング被看面以外のリードフレー人聞は、電
気的にしかも高周波伝播にさいし減衰の少い透８１軍ｅ
）が１に等価な常磁性金属としての一文は鋼何れかをめ
っきすることである。The present invention provides an atomic bonding target 5i of a lead frame 1.
High-strength nickel plating is applied only to the iF part,
The lead frame other than the bonding surface is electrically conductive and has low attenuation during high frequency propagation.
) is equivalent to 1 as a paramagnetic metal is to plate any steel.
前１１派足ニッケルめっきは庁１９ｊｌ：めっき面のみ
窓めけした部分めっき装置に連続してリードフレーム成
形体１を送入すれば容易に−ＡＭｉＬ倚る０この場合、
めっき厚嘔は最小１μｌｌｌ根嵐゛あれば十分である。The previous 11th nickel plating can be done easily by feeding the lead frame molded body 1 continuously into a partial plating device in which only the plated surface is window-plated. In this case,
A minimum of 1 μl of plating thickness is sufficient.
即ち、Ｍ１図のリード端子９の上端部図示１００幅該当
部分をニッケルめっきし表向処理する。That is, the upper end portion of the lead terminal 9 shown in FIG. M1 corresponding to the width of 100 mm is nickel-plated and surface-treated.
尚、第１図中リードフレーム下方の通結部１１は前記ポ
ンディング法統、これに続く衝脂外装の成形光子ののち
切除される。In addition, the connecting portion 11 below the lead frame in FIG. 1 is cut off after the above-mentioned bonding process and the subsequent molding photon of the resin sheath.
４２図の実施ｓ、ＴＯ−８形キヤン用ステムにフィルタ
チップがダイシングされた側御において、本発明の＊部
処理は図示リード端子９の頭部」０をニッケルめっきす
ると共に、リード端子９０表向は゛に弾性かつ１％導電
嬶の一文をよ鋼１Ｌ＋１れかのめつき処４ｔ−すｒｔば
よい。In the embodiment shown in Fig. 42, in which a filter chip is diced into a stem for a TO-8 type can, the * part treatment of the present invention is to nickel plate the head ``0'' of the lead terminal 9 shown in the figure, and to nickel plate the top of the lead terminal 90. For the direction, it is sufficient to use a piece of steel that is elastic and 1% conductive, and 1L + 1 or 4t-Srt of plated steel.
囚に―ｄｉ２！Ｊ！施例第１図の端子リード９に通用し
九本発明の端子リードと従来端子リード、即ち全面ニッ
ケルめっきしたリードとを３６ＭＨｚで計測した比較を
示すと、従来品が２７０鶴Ω（抵抗値）であるのに対し
、本発明のリード端子特に前記ニッケルと銅とのめつき
処理になるリードでは前記抵抗値は６．３潟Ωとなる。Prisoner-di2! J! Example A comparison of the terminal lead of the present invention, which is applicable to the terminal lead 9 in FIG. On the other hand, the resistance value of the lead terminal of the present invention, particularly the lead plated with nickel and copper, is 6.3 Ω.
（６）発明の効果
前記本発明の端子リード処理をしたものでは、例えばＳ
ＩＰ形３６ＭＨｚ表面波フィルタについてみると、誘導
レベルが一４８ｄＢであったものが、−５４ｄＢと更に
低い誘導レベルに押えられ、併せて表面フィルタの高周
波遮断特性が改嵜される。(6) Effects of the Invention In the terminal lead treatment of the present invention, for example, S
Regarding the IP type 36 MHz surface wave filter, the induction level was reduced from 148 dB to an even lower induction level of -54 dB, and the high frequency cutoff characteristics of the surface filter were also improved.
かかる観点から本発明の実用価値は大きい。From this point of view, the present invention has great practical value.
第１図は本発明に係る対象リードフレームのボンディン
グ接続を示す正面図、及び第２図は本発明に係るフィル
タチップをボンディング接続するＴＯ−８形ステムの斜
視図である。
図中、１はリードフレーム、２はフィルタチップ、３と
４はすだれ状フィルタ１を他、６は２の電他、８はポン
ディングワイヤ、９はリード端子又は端子リード、及び
１ｏはニッケルめっき又は９の頭部である。
Ｐノ図
−ス図FIG. 1 is a front view showing bonding connection of a target lead frame according to the present invention, and FIG. 2 is a perspective view of a TO-8 type stem to which a filter chip according to the present invention is bonded. In the figure, 1 is the lead frame, 2 is the filter chip, 3 and 4 are the interdigital filters 1, 6 is the wire of 2, 8 is the bonding wire, 9 is the lead terminal or terminal lead, and 1o is the nickel plating. Or the head of 9. P diagram - space diagram
Claims (1)
ード端子予形成のリードフレーム等とを超音仮ポンディ
／グ法により接続する表面波フィルタの前、４６１３−
ド端子の表面処理において、少くともリードフレームの
ボンディング面はニッケルめっきがされ、前記リード端
子面は銀又は鋼何れかのめっき処理がされてなる表面波
フィルタの端子処理方法。In front of the surface wave filter, where the electrode of the filter chip on which the surface wave vibration element is formed and the lead frame, etc. on which the lead terminal is preformed are connected by the ultrasonic temporary bonding method, 4613-
In the surface treatment of the lead terminal, at least the bonding surface of the lead frame is plated with nickel, and the lead terminal surface is plated with either silver or steel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197084A JPS5897914A (en) | 1981-12-08 | 1981-12-08 | Terminal handling method of surface acoustic wave filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197084A JPS5897914A (en) | 1981-12-08 | 1981-12-08 | Terminal handling method of surface acoustic wave filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5897914A true JPS5897914A (en) | 1983-06-10 |
Family
ID=16368450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56197084A Pending JPS5897914A (en) | 1981-12-08 | 1981-12-08 | Terminal handling method of surface acoustic wave filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5897914A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0425691A1 (en) * | 1989-05-01 | 1991-05-08 | Sumitomo Electric Industries, Ltd. | Lead frame for semiconductor devices |
| JPH03119712A (en) * | 1989-10-02 | 1991-05-22 | Furukawa Electric Co Ltd:The | Manufacture of lead frame for piezoelectric component |
-
1981
- 1981-12-08 JP JP56197084A patent/JPS5897914A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0425691A1 (en) * | 1989-05-01 | 1991-05-08 | Sumitomo Electric Industries, Ltd. | Lead frame for semiconductor devices |
| JPH03119712A (en) * | 1989-10-02 | 1991-05-22 | Furukawa Electric Co Ltd:The | Manufacture of lead frame for piezoelectric component |
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