JPS5897863A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5897863A JPS5897863A JP19656481A JP19656481A JPS5897863A JP S5897863 A JPS5897863 A JP S5897863A JP 19656481 A JP19656481 A JP 19656481A JP 19656481 A JP19656481 A JP 19656481A JP S5897863 A JPS5897863 A JP S5897863A
- Authority
- JP
- Japan
- Prior art keywords
- region
- amorphous
- semiconductor device
- oxide film
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005204 segregation Methods 0.000 abstract description 11
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000001467 acupuncture Methods 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008521 reorganization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
一般に、半導体基板中に不純物を拡散すると、不純物拡
散によって形成された拡散層中に、そＯ不純物の偏析が
観察される。これは、基板中に拡散され九不続物が基板
内の応力分布に応じて再編成する丸めであυ、その核と
なるものは空格子点（１ａ＠ａｎ＊ｙ ）、０２、Ｃ１
重金属蝉の基板中に歪場を与えている部分と考えられる
。この丸め、偏析の発生は不規則であり、種々の大きさ
を有する偏析が共岑している。偏析は、不純−の濃度分
布Ｏ異常によるものであシ、基板結晶格子は歪んでいる
が、転′位等の大亀な結晶欠陥を伴うことはない・従９
て、偏析は半導体装置の特性上問題となるようなリーク
等の原因にはならないが、半導体装置中を流れるキャリ
アの進行を変調させ、低周波雑音源となる。Generally, when impurities are diffused into a semiconductor substrate, segregation of SO impurities is observed in the diffusion layer formed by the impurity diffusion. This is a rounding in which the nine discontinuities diffused into the substrate reorganize according to the stress distribution in the substrate, and the core is the vacancy (1a@an*y), 02, C1
This is thought to be the part that applies a strain field to the substrate of the heavy metal cicada. The occurrence of this rounding and segregation is irregular, and segregations of various sizes occur together. The segregation is due to an abnormality in the concentration distribution of impurities, and although the substrate crystal lattice is distorted, it is not accompanied by major crystal defects such as dislocations.
Although segregation does not cause problems such as leakage that may cause problems in the characteristics of the semiconductor device, it modulates the progress of carriers flowing through the semiconductor device and becomes a source of low frequency noise.
而して、従来から半導体装置の雑音を減少させるための
努力がなされている・例えば、２種類の不純物元素を同
時に拡散させて拡散層を補償する方法、Ｐによるｒツタ
リング（ｇ舎ｔｔ＠ｒｉｎｇ）を行う方法がそれで、あ
る、これらの方法は、全て結晶欠陥中不要不純物を取シ
除くための有力な方法とされている。ヒＯため−これら
の方法を採用すると無欠陥で、かつ不要不純物量が少な
く良好な低雑音素子からなる半導体装置が製造され石が
、これらの方法にも限度があ）偏析の発生を十分に抑え
ることはで亀ない問題があり九・
また、前述したように偏析Ｏ発生は、結晶中の微小な歪
場の分布及び数によって決定される。Therefore, efforts have been made to reduce the noise of semiconductor devices.For example, there is a method of simultaneously diffusing two types of impurity elements to compensate for the diffusion layer, ). All of these methods are considered effective methods for removing unnecessary impurities from crystal defects. Because of this method, it is possible to manufacture a semiconductor device that is defect-free and has a good low-noise element with a small amount of unnecessary impurities. There is a problem that cannot be suppressed. Also, as mentioned above, the occurrence of segregated O is determined by the distribution and number of minute strain fields in the crystal.
従りて、偏析の大きさ、密度、大きさのばらつきは、基
板の結晶状１ｍ、含有不要不純物量によって決定される
。この場合、偏析の発生は、拡＄歪の分散と再編成に依
存し、偏析による総歪量は拡散不純物が一定なら同量で
ある・１本発明は、かかる点に銖みてなされた−ので、
偏析の発生を阻止して良好な低雑音素子からなる半導体
装置を容易に得ることができる半導体装置の製造方法を
見出したものである・以下、本発明の実施偶について図
面を参照して説明する。Therefore, the size, density, and variation in size of segregation are determined by the crystalline 1m of the substrate and the amount of unnecessary impurities contained. In this case, the occurrence of segregation depends on the dispersion and reorganization of the expansion strain, and the total amount of strain due to segregation is the same if the diffusion impurity is constant.1 The present invention has been made with this point in mind. ,
We have discovered a method for manufacturing a semiconductor device that can easily obtain a semiconductor device made of good low-noise elements by preventing the occurrence of segregation.Hereinafter, embodiments of the present invention will be explained with reference to the drawings. .
先ず、第１図に示す如く、Ｎａ半導体基板１０表面に熱
鍼化によシ厚さ約５０００１Ｃ）＃化膜１を形成する拳
次いで、半導体基板Ｊのペース形成予定領域に対応する
酸化膜２の領域に周知Ｏ写真蝕刻法によシ慝３を開口す
る。次いで、この酸化１１３をマスクにして、電子線を
照射条件加速電圧２００に・■、電流値１ｍＡ、照射童
１０１個／−で照射し、ペース形成予定領域な非晶質化
する。この非晶質化されたペース形成予定領域Ｋｌ−ン
の不純物拡散を施し、ペース領域４を形成した。ここで
、ペース形成予定領域を非晶質化する手段どしては、電
子線の照射の他にも所定の照射条件で放射線、分子線、
Ｘ線、イオンビーム等を照射する手段を採用しても喪い
、また、ペース領域４を形成する不純物Ｏイオン注入処
理により、イオン注入条件を所定の条件に設定すること
Ｋよりて、非晶質化とペース領域４の形成とを同時に達
成するようにして必要な照射条件を設定しても良い、ま
た、ツース形成予定領域を非晶質化した後に、熱処理を
施しである程度再結晶化させてから、所定の不純物を導
入してペース領域４を形成するようにしても良い。また
、非晶質化後の不純物導入工程の前後の工程で所定濃度
のシリコンをペース形成予定領域に導入しても良い。First, as shown in FIG. 1, an oxide film 1 of approximately 50,001 C) thickness is formed on the surface of the Na semiconductor substrate 10 by thermal acupuncture, and then an oxide film 2 is formed on the semiconductor substrate J corresponding to the area where the paste is to be formed. A hole 3 is opened in the area by the well-known photolithography method. Next, using this oxidation 113 as a mask, an electron beam is irradiated under the irradiation conditions at an accelerating voltage of 200.times.2, a current value of 1 mA, and 101 irradiated particles/- to make the region where the paste is to be formed amorphous. Impurities were diffused into this amorphous paste formation area K1 to form a paste area 4. Here, in addition to electron beam irradiation, means for making the area where the pace is to be formed amorphous include radiation, molecular beam, etc. under predetermined irradiation conditions.
Even if a means of irradiating with X-rays, ion beams, etc. is adopted, the amorphous The necessary irradiation conditions may be set so as to simultaneously achieve the formation of the tooth formation and the formation of the pace region 4. Alternatively, after the tooth formation area is made amorphous, heat treatment is applied to recrystallize it to some extent. The pace region 4 may be formed by introducing a predetermined impurity. Furthermore, silicon at a predetermined concentration may be introduced into the region where the paste is to be formed in steps before and after the impurity introduction step after amorphization.
次に、同図の）に示す如く、酸化膜２を除去した後、半
導体基板１及びペース領域４の表面に新しく酸化膜１を
形成し、ペース領域４内の工（、／形成予定領域に対応
をする領域に写真蝕刻法によシｇ６を開甲する。茨いで
、ペース領域４の形成工程と同様に、酸化膜５をマスク
にしてエミッタ形成予定領域を、照射条件加速□電圧２
００１１１ｖ、電流゛値１ｍＡ１照射量１０ 個／−〇
電子縁射綜によシ非晶質化した後、リンの不純譬拡歓を
施し、ニオ、り領域７を形成する・然る後、酸化膜５に
ペース領域に通じるコンタクトホール８を開口し、この
コンタクトホール８及び＠６を介してペース領域４、エ
ミッタ領域７に夫々縁Ｕする取出電極９，１０を形成こ
のようにして製造された半導体装置７７では、４−ス領
域４及びエミッタ領域７の不純物領域は、非晶質化され
た後に所定の不純物を導入して形成されているので、偏
析の発生がｔｌとんど抑制さ汎てお）、しかも僅かに発
生し九偏析についてもその大きさ、大きさのばらつき、
及び密度がほぼ均一な４０″′ｅあるこ゛とが判りた。Next, as shown in ) in the same figure, after removing the oxide film 2, a new oxide film 1 is formed on the surfaces of the semiconductor substrate 1 and the space region 4, and a The corresponding area is opened by photolithography.Similarly to the process of forming the pace area 4, the area where the emitter is to be formed is exposed using the oxide film 5 as a mask under irradiation conditions of acceleration □voltage 2.
00111V, current value 1mA, irradiation amount 10 pieces/-〇After being made amorphous by electronic edge beams, phosphorus impurity is expanded to form a niobium-rich region 7.After that, oxidation is performed. A contact hole 8 communicating with the pace region was opened in the film 5, and lead-out electrodes 9 and 10 were formed to edge U to the pace region 4 and the emitter region 7, respectively, through the contact hole 8 and @6. In the semiconductor device 77, the impurity regions of the 4-phase region 4 and the emitter region 7 are formed by introducing predetermined impurities after being made amorphous. Furthermore, the size and variation of the size of the small amount of segregation that occurs,
It was found that the density was approximately uniform at 40'''e.
七の結果、極めて嵐好な低雑−音素子によって半導体装
置１１を構成できることが判りた。As a result of Section 7, it has been found that the semiconductor device 11 can be constructed using extremely low-noise elements.
因に、本発明方法にて製造された半導体装置１１では、
ノイズレベルは１６〜２５ ｄＢでＴｏや、歩留は約６
５慢であうたが、即晶質化処理を採用しない従来方法で
製造された半導体装置では、ノイズレベルは８〜１２
ｄＢであシ歩貿は、約９７チであることが実験的に確認
された。Incidentally, in the semiconductor device 11 manufactured by the method of the present invention,
The noise level is 16 to 25 dB and the yield is about 6.
5.Although this may sound arrogant, the noise level of semiconductor devices manufactured by conventional methods that do not use instant crystallization is 8 to 12.
It has been experimentally confirmed that the foot trade in dB is about 97 chi.
以上説明した如く、本発明に係る半導体装置の製造方法
によれば、偏析Ｏ発生を阻止して亀好瀝低雑音素子から
なる半導体装置を容易に得ることができる等顕著な効果
を奏するものである。As explained above, according to the method for manufacturing a semiconductor device according to the present invention, it is possible to prevent the generation of segregated O and to easily obtain a semiconductor device made of a low-noise Kameyoshi element. be.
第１図乃至第３図は、本発明に係る半導体装置の製造方
法を工程順に示す説明図である。
１・・・半導体基板、２・・・酸化膜、Ｓ・−窓、４・
・・ペース領域、Ｓ−・・酸化膜、６・・・窓１．ｒ・
・・二建ツタ領域、１・・・コンタクトホール、９ ｅ
Ｊ Ｏ・・・取出電極、】１・・・半導体装置、 ゛1 to 3 are explanatory diagrams showing the method of manufacturing a semiconductor device according to the present invention in order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, S-window, 4...
...Pace region, S-...Oxide film, 6...Window 1. r・
... Niken ivy area, 1... Contact hole, 9 e
JO...Extraction electrode, ]1...Semiconductor device, ゛
Claims (1)
程と、非晶質化された前記所定領域に所望導電［０不純
物を導入して不純物領域を潜成する工程とを具備するこ
とを特徴とする半導体装置の製造方法、・1. A step of performing an amorphous treatment on a predetermined region of a semiconductor substrate of 1 conductivity, and a step of introducing a desired conductivity [0] impurity into the amorphous predetermined region to form an impurity region latently. A method for manufacturing a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19656481A JPS5897863A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19656481A JPS5897863A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5897863A true JPS5897863A (en) | 1983-06-10 |
Family
ID=16359825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19656481A Pending JPS5897863A (en) | 1981-12-07 | 1981-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5897863A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004075274A1 (en) * | 2003-02-19 | 2004-09-02 | Matsushita Electric Industrial Co., Ltd. | Method for introducing impurities |
| US7759254B2 (en) | 2003-08-25 | 2010-07-20 | Panasonic Corporation | Method for forming impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device |
| US7858479B2 (en) | 2004-05-14 | 2010-12-28 | Panasonic Corporation | Method and apparatus of fabricating semiconductor device |
| US7981779B2 (en) | 2003-10-09 | 2011-07-19 | Panasonic Corporation | Method for making junction and processed material formed using the same |
| JP2013107788A (en) * | 2011-11-18 | 2013-06-06 | Central Research Institute Of Electric Power Industry | Method for manufacturing silicon carbide wafer, silicon carbide wafer, silicon carbide semiconductor element, and power converting device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648168A (en) * | 1979-09-28 | 1981-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor integrated circuit unit and its preparation |
-
1981
- 1981-12-07 JP JP19656481A patent/JPS5897863A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5648168A (en) * | 1979-09-28 | 1981-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor integrated circuit unit and its preparation |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004075274A1 (en) * | 2003-02-19 | 2004-09-02 | Matsushita Electric Industrial Co., Ltd. | Method for introducing impurities |
| US7618883B2 (en) | 2003-02-19 | 2009-11-17 | Panasonic Corporation | Method for introducing impurities and apparatus for introducing impurities |
| US7696072B2 (en) | 2003-02-19 | 2010-04-13 | Panasonic Corporation | Method for introduction impurities and apparatus for introducing impurities |
| US7709362B2 (en) | 2003-02-19 | 2010-05-04 | Panasonic Corporation | Method for introducing impurities and apparatus for introducing impurities |
| US7741199B2 (en) | 2003-02-19 | 2010-06-22 | Panasonic Corporation | Method for introducing impurities and apparatus for introducing impurities |
| US8222128B2 (en) | 2003-02-19 | 2012-07-17 | Panasonic Corporation | Method for introducing impurities and apparatus for introducing impurities |
| US7759254B2 (en) | 2003-08-25 | 2010-07-20 | Panasonic Corporation | Method for forming impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device |
| US7981779B2 (en) | 2003-10-09 | 2011-07-19 | Panasonic Corporation | Method for making junction and processed material formed using the same |
| US7858479B2 (en) | 2004-05-14 | 2010-12-28 | Panasonic Corporation | Method and apparatus of fabricating semiconductor device |
| JP2013107788A (en) * | 2011-11-18 | 2013-06-06 | Central Research Institute Of Electric Power Industry | Method for manufacturing silicon carbide wafer, silicon carbide wafer, silicon carbide semiconductor element, and power converting device |
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