JPS5896342A - Data transfer device - Google Patents

Abstract

PURPOSE:To disuse a signal cable, by superposing data to the current or a supply line for electric power supplied from a copying machine body to its attachment. CONSTITUTION:Transmission and reception parts 20 and 30 provided to a copying machine body 11 and its attachment 18 have microcomputers respectively, and those microcomputers perform series-parallel convesion and parallel-series conversion of data. Then, a line 41 is the power supply line of a power source from the copying machine body 11 to its attachment 18 and high frequency components of an FS-modulated signal outputted from transmitting unit on the transmission and reception part side 20 are superposed to the current on the power source supply line 41 after being passed through a capacitor 42 and then supplied to the receiving unit on the transmission and reception part side 30 through a capacitor 43. Consequently, a signal cable and a connector for coupling it are omitted.

Description

[Detailed Description of the Invention] This relates to a data transfer device that exchanges data with each other.Generally, in a copying machine that improves operability and precisely controls copy quality, it is used to connect the copying machine main body, sorter, and input sensor. There is a need for a data transfer device that exchanges various data with an additional device equipped with such devices. As shown in the first factor, Hinoki's conventional data transfer device includes a central processing unit (CPU) /J, I10 controller /
3. Output driver/4t, input interface/.
t, CPU power supply circuit/6 and additional device power supply circuit/
〇Additional device/rK having 2 is sequence controller lid, input interface JOA, output)” driver 27A.

Output load J. 2A and an input sensor 231f, and for example, a flat cable consisting of a number of connection cables corresponding to various signals is used for mutual data transfer.

(Input interface 7 8th/! of input device main body // and input interface 7 8th λθAH of additional device However, in any case, as the number of signal types to be transferred increases, the number of connector bins also increases, which not only increases the cost of connectors and cables, but also reduces the reliability of the equipment. In addition, there is a data transfer device called Universal Async Receiver Transmitter (υART) that can perform serial transfer at a transmission speed of 10 to -0K (bits/second), but The connectors on the 7-rat cable are too expensive, and the UART
Although it has versatility, there are many points that make it unsuitable as a data transfer device between the main body of a copying machine and its attached devices.

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a copying machine main body and an additional device thereof with microcomputers for serial data transfer, and to supply a power supply line from the copying machine main body to the additional device. An object of the present invention is to provide a data transfer device that can eliminate signal cables by superimposing data on a signal.

The present invention will be described in detail below with reference to the drawings.0@3 to 5 and 2 show an example of the configuration of the main part of the data transfer device according to the present invention, and FIG. The output signal of the unit shown in the figure is shown. In Figures 3 and VC, 20 is a transmitting/receiving unit for the main body of the copying machine, 3θ is a transmitting/receiving unit for an additional device, and 2/ and 3/ are data transfer units that perform serial/parallel conversion and parallel/serial conversion of 9 data, respectively. microcomputer,
2-32 master/slave selector switch,
By turning on or off one of the switches 32 and 32, one of the transmitting/receiving sections 30 and 30 can be switched to the master side and the other to the slave side. 23-2≦ and 33-36 are amplifiers.

Transmission unit for 27 and 32 modulation, 2! And 3!
0 is a receiving unit for demodulation, that is, a transmitting unit 22 and 776′i, and as shown in FIG. It consists of a modulation circuit, and the mark part and the space part of the serial digital data that is the input signal are changed to frequencies r1 and f2 by switching the switch 3! ! On the other hand, as shown in the wJZ diagram, the receiving units ♂ and 3/ are connected to a 7-axis locked loop (PLL) circuit aO that converts the FS-modulated input signal into digital data, and other bass It has a Kuimachi router LPF and a waveform shaping circuit WSC.

In FIG. 9, da/ is a power supply line for the power supplied from the copying machine main body 1/ to its additional device /l, and this power supply Ii! 6412. N-fold high-frequency data FS-modulated into data and serially transfer the data. The phantom is a coupling capacitor, and this capacitor 4tλ and ￥j VC, ' is supplied as a source, and the transmitting/receiving unit is 2 and λr and 32 and 3? The 0-dac that performs high-frequency coupling between the
Power supply II! The frequency components superimposed on the power supply of the data transfer device are removed by this filter circuit before the power is supplied to the sequence controller. Microcomputer, 2/R/Boat “θ”
The data output from the bin is supplied to the transmitting unit 27 via the antenna terminal ANT■. The high frequency component of the FiS modulated signal output from the transmitting unit 27 is superimposed on the power supply m&/ through the capacitor λ. Next, the high frequency component is supplied to the slave receiving unit 3 via the power supply line and the capacitor 3. The receiving unit 3
The serial digital data recovered at t is transferred to the "/" pin V of the R/board of the slave side microcomputer 31.
To explain further, this data transfer device includes compatible transmitting/receiving sections 20 and 30 in the main body of the copying machine and in the additional device. The transmitter/receiver section λθ, 30 is mounted on 7 printed circuit boards, each with a microcomputer tacho/, 3
/ and interface (2).

Microcomputer 2/, 3/(l, data pile parallel conversion and parallel-serial conversion with row 9 functions, R & Ho)
Master/slave settings are made using the switches 22 and 3λ connected to the master/slave settings. As shown in Figure 9.

Transmitting/receiving unit for copying machine body - Microcomputer 2/
is the master, and the microcomputer 3/ for transmitting/receiving s3θ for the additional device is the slave.The microphone c+computer 21, 3/ has a power terminal Vcc, a ground terminal VSS, and control terminals FIT, EX, and X, and a power terminal VccVcQ. When the source is supplied, the control terminal R
A reset signal is supplied to T to initialize the system, and the ratio control terminals EX and XK are
#0 that is connected and oscillates a clock pulse of, for example, -MHz.
By the way, microcomputer 2/.

Examples of J/ include ROM (read-only memory) and FIAM (random access memory).
A microprocessor housed in a step can be applied.

In this data transfer device, when data is supplied from the main body of the copying machine to the input terminal IN/ consisting of terminals P//3 to P/2 of the transmitting/receiving section 20, the data is transferred to the multiplier.
23.2 is amplified and sent to the microcomputer-27 via the R co-boat, R3 port, and each terminal of the boat.
reads the data, converts it to serial data, and sends it from R/ to the antenna terminal ANT■, transmitting unit, 22. This transmitting/receiving section 30fl, which is transmitted to the transmitter s3θ via the coupling capacitor '42, the II source supply running/and the coupling capacitor 3, etc. The microcomputer 31 receives the serial data and inputs it to the R/boat of the microcomputer 3/ through the antenna terminal ANT■, converts the serial data back into differential data, and converts the serial data back into differential data. The signal is supplied to the amplifiers 33 and 3da through each terminal of the amplifiers 33 and 3da. And amplifier 33,3
DA amplifies the parallel data and connects it to terminal P20/~P,2
/2 to the output terminal OUT 2.

Similarly, when the transmitter/receiver 30 on the slave side transmits data to the transmitter/receiver 20 on the master side, Vc is an amplifier jJ. -, 36, microcomputer 3/, antenna terminal ANT■, transmitting unit 3
2. Coupling capacitor 4t3. Power supply line 4t/and receiving coupling capacitor &-2 (W Unino), 2J'.

Antenna terminal ANT■, microcomputer 2/.

The terminals P/θ/~P are connected via amplifiers 2j and 2g, respectively.
//λ can be transferred to the output terminal OUT/. In this case, the microcomputer 37c performs parallel-serial conversion of data, and the microcomputer 37-2 performs serial-parallel conversion of data.
, 3θ can perform all bidirectional data transfer via the power supply ll14t71.

Figure 2 shows an example of a communication format applied to the data transfer device shown in Figure 2. However, it only shows the signal component of the power supply and does not show the F8 modulated high frequency component itself. No (see Figure 5). As shown in the figure, the microcomputers 2/ and 3/jfl can transfer the data of the / frame by executing the // steps ① to ②. Step ■.

In ■, the master side microcomputer 2/
The microcomputer 3 on the slave side performs synchronized control of the transfer lock. Therefore, microcomputer a
In step O, when the transmission line is in the oven, bit O of the / frame changes from "/"' to "
By reaching θ″, start step ■ and TASK
/as? Transfer lock I (with period TM consisting of bits)
During this period, the microcomputer 37 activates TASK- at the rising edge of the θ bit, and transmits the period TM of the transfer pulse sent from the master side to the bit θ~ 7
The r-th measurement is performed, the average value T8 f of the lock cycle is determined by calculation, and the bit? The microcomputer 2/c then checks whether the transfer lock period TM and the average value TS supplied through the antenna terminal ANT■ are dirty. ←If TST&fl, communication with the microcomputer 3/ is not possible, so at step ■ bit/≦, the antenna terminal ANT■t“
θ" to inform the microcomputer 3/ and start over from the initial state. However, if TM = TS,
Microcomputer 27ha, step ■ bit/7
i"01 and starts executing TASK4t. The microcomputer λ/c starts counting transfer locks from bit/2 in step (2). Therefore, from this bit/2 to bit data, the period of each bit is TM. :
'rs.

In the next steps ■ and ■, the microcomputer 2
Run TASKJ on /, and first bit/? ～Contains 2 bits of serial data to the antenna terminal ANT■
and ANT (2) to the microcomputer 3/, and then transmits a check bit consisting of 3 bits 30 to 3- in step (2). Among these check bits, bits 30u and 414 may be used as parity bits, but in this embodiment, bits 3 and 3 are set to ``θ'''' and bits 3 and 4, respectively, so as to set the previous bit and the two's complement.
Bit 37 in the 0 check bit that clearly distinguishes θ is set as gvcx in the data, and in this embodiment, the second bit of the 72-bit data, bitco! The check bit of 0 pit 3.2 is set to "7'" which is the same value as "θ" to represent the final bit, and at the end of this bit 3.2, the "/" VC is set and the check bit is set to "7'". At 33, the antenna terminal ANT■ is opened.

The microcomputer// is in step 1,
While TASKJ i is being executed, the microcomputer 3/ executes TASK(i(
Execute. In this way, the microcomputer 2
/ converts the parallel data supplied to the terminals P//3 to P/ of the transmitting/receiving unit-0 into serial data, sends it to the power supply line / via the antenna terminal ANT■, and sends it to the microcomputer. 3/C: Receive the serial data through the antenna terminal ANT■, convert it to parallel data again, and supply it to the terminals P20/~-272 of the transmitting/receiving section 3θ. Therefore, the input terminal IN of the transmitting/receiving section J The data supplied to the terminals P//, 2 to P/ at / is
The corresponding terminal PλO of the output terminal 0UT- of the transmitting/receiving section 30
/~P2/-, respectively.

By the way, in step (2), the microcomputers 2/ and 3/ prepare to change the transmission/reception mode and change the data transmission direction. In step 1, the microcomputer 3/ on the slave side sets bit 3 to "θ" and starts counting transfer locks in order to start transmitting data. Since the microcomputer J/f-j has already synchronized the transfer lock in steps ■ and ■, the 72-bit serial data (bits 3!~g) is sent to the antenna at the transfer lock period TM in step ■. The signal can be modulated by FE3 from the terminal ANT■ by the transmitting unit 32, sent through the entire coupling capacitor 3, and sequentially transmitted to the -r microcomputer computer. Also, in step [phase], the microcomputer 3/q sends the 3-bit check pit (bits 32 to 3) to the microcomputer λl in the same way as in step (2).Thus, the microcomputer 3/q sends the data. During the period in which the microcomputer 2/2 executes TASKj to receive the data, the microcomputer 2/2 executes TASK& to receive the data.
The data supplied twice can be supplied to corresponding terminals P10/ to P//2 of the output terminal OUT/ of the transmitter/receiver section 20, respectively. In step 0, both microcomputers 2/ and jl open the antenna terminal ANT■ and become TASKO waiting for the start of step ■ of the frame in which the next data transfer is to be performed.

Figure 99 is a block diagram showing the configuration of the main parts of the microcomputer-/e3/Fi, the control storage section j/, and the RAM (
The ROM (read-only memory) of the control memory section j/ is necessary for controlling microinstruction and data transfer lock cycles, etc. remembers information. decoder ocr
H. The data read from the ROM is decoded, and the program counter PC determines the ROM O address tm. In addition, stack STK is, for example, LIFO (last
It is a set of registers used in the form (in first out).

Next, the RAM section j2 consists of a plurality of memory areas, the addresses of which are specified by the X and Y address registers. Among the plurality of memory areas, RAM/ stores data supplied to input terminal IN/ or input terminal IN-2;
This is the output terminal OUT / or the output terminal OUT, l
Stores data to be supplied to. And RAM J is
This is a memory area that stores serial manual data transmitted from the other party's computer to the R/Boat via the antenna terminal ANT■.In addition to this, there is also a RAM section! / is an interrupt counter that increments by +l when there is a timer interrupt, transfer lock period TM f: memory area to store, measured transfer lock period TSt - memory area to store and input/output data management number. There is a memory area for storing data.

Next, the operation of this data transfer apparatus will be explained with reference to the main program chart 70 in FIG. 1θ and the subroutine flowchart in FIGS.

When power is supplied to the microcomputer tacho/, 3/ and initialization is performed by a reset signal, the main program shown in FIG. 1θ is started.

First, in step 61, the RAM is cleared, and in the next step 42, the subroutine "IODATA" is executed.
is executed ◇This subroutine "IODATA" causes the microcomputers 2/ and J/ to read the input information of the input terminals IN/, IN, and 2 into the RAM/, and transfer the information to the output terminals OUT/ and OUT from the RAM.
, 2 is a routine that supplies output information read from . At step d3, the H and RAMK transfer lock period TM is set and an interrupt counter is activated.

As described above, the transfer lock period TM is written in the ROM and determines the serial data transmission method. Each time a timer interrupt occurs, the interrupt counter increments its contents by 10/, and in step 6, the microcomputer 2/
, j/ are respectively 9 masters or slaves. Then, since the microcomputer tacho/ is the master and the microcomputer 3/ is the slave, the process moves to the next step, and in step t4t, the subroutine "T" is executed.
ASK/”, and in step 6g the subroutine “TAS
K? Execute ″″. Therefore, microcomputer 2
/f-1% First, the transfer lock pulse is sent to the transmission line using t bits from bit O to bit 2 with the period TM, and the microcomputer 3/ measures the transfer lock period ([ (See step C in the figure) 0 Next, the microcomputer 31 processes bits l to bits/! based on the measured transfer lock period T8. The microcomputer 27 receives the transfer lock pulse *x over the period of time (see step C in FIG. 2).

In this way, the microcomputers 2/, j/
Synchronous control of the transfer lock cycle is performed, and as a result, if the clock cycle TM is 'rS, mutual communication is possible.The determination is made in the subroutine of step 62.
Ii: RROR'''', clock period TM~T
When it becomes 8, "/"' is input to the error flag register.0 Check whether this error 7 lag is "/" at step 6? If the error flag is "/", the process moves to step 69, resets the error flag register, and repeats the process at each step.
Returning to step 9, if error 9/ is "O", control is transferred to the next step 2θ.

Here, if the error flag is /IIK, the microcomputer-2/r
t, drop the transmission line to "θ"" and notify the microcomputer 3/Vc ◇However, even if an abnormality occurs in the microcomputer 3/ and the transfer lock cycle cannot be measured, the subroutine "ΣRROR" will detect it. Then, the error 7 lag register becomes "/1" and the transmission line becomes "θ".

Now, in step 70, it is determined again whether the microcomputer 31 is a master or a slave, and the microcomputer 31 on the master side is subroutine "
TASK4t” Vf-Execute in steps 21 and 2,
At the same time, the slave side microcomputer 13/l
X, f 7 #-JF-y“TA8Ka”,”T
ASK3' is executed in step 2J, 2 das. That is, the microcomputer 2/ first sets the transmission line to "0" in step (2) in FIG. is transferred, and 3 check bits are transferred in bits 30 to 3-. At this time, the microcomputer 3/ enters a data receiving operation in step (2), and in steps (2) and (2), reads the entire /- bit serial data and 3-bit check pit.

In this way, the microcomputer 2/cass routine "TASK3" is executed, and the microcomputer 3
/ executes the subroutine "TA8Kg" 2 - r 〇 Then, after the transmission line is opened due to the step in Figure R, the microcomputer 3/ is set to bit 3.
Steps involving data transmission over 4t-data
The subroutine ``TASKj'' of the phase] is executed, and at the same time the microcomputer co/c executes the subroutine ``TASKj''.
When the microcomputers -/, 3/ finish the subroutines "TASK4t-, TASKJ" in steps 72 and 7&, respectively, the control returns to step 6.2 for the next data transfer.
Moved to nine.

The steps of the main program are as described above, but each subroutine will be explained in turn. First, in the subroutine "IODATA", the microcomputers 2/ and J/ execute data according to the data management numbers θ~//. , input data is loaded into RAM/, and output data is read from RAM-. Therefore, as shown at 70-Tayat in Figure 1/, when the blue ten "IODATA" is called, the data management number is cleared in step t/,
In steps /2 to r6, RAM / [input data is taken in, step! After the management number is cleared again in Step 7, the output data is read from Stellar 7J'/~92TE RAM 2. That is, in step /,2, for example, the data management numbers "θ" to "/" assigned to the input terminals P//j to P/2 of the copying machine main body transmitting/receiving section -〇 (Fig. 3) are respectively assigned. /“In response to K, checking of input data is performed. For example, the data management number “
The input data is written to the location of RAM / corresponding to the input terminal "θIIK" of θ1. In the next step!!, the data management number is incremented by 10l, and the data management number is set to "θ
``'' changes to ``/'', so the check in step!6 as to whether the management number is ``/co1'' becomes ``NO'', and the control returns to step /-. Similarly, the input data is stored in RAM/KJ! according to the data management number. 1
2 is entered and the data management number becomes "Remove/Co", the check for step?≦ is checked with "YES", so control is transferred to step V.

Step ♂r~In the tacho, the output data read from the RAM-2 according to the data management number is distributed, for example, to the output terminals P/θ/~P// of the transmitter/receiver 20, but the control is substantially the same from step ♂2 to /, so the explanation thereof will be omitted.In step 63 of the main program, c.
The lock period TM is set and the interrupt counter is enabled.0 When there is a timer interrupt, the interrupt routine shown in Figure 1 is called and steps 10/-103 are executed. It will be executed. That is, each time there is an interrupt, the contents of the interrupt counter are incremented by 1, and when the interrupt counter overflows, the error flag register is set. Then, subroutine "TASK/"f is executed. FIGS. 73 to 76 show the subroutine "T".
This is a flowchart of ASK/′″. Subroutine “
By executing TASK/", the microcomputer 27c, the antenna terminal ANT, and the transmission line via the controller have a period TM consisting of repetitions of "01" and "l'".
After sending out the transfer lock pulse, the period T8 of the transfer lock pulse returned from the microcomputer 31 is measured.The l-bit transfer lock pulse consisting of 0 bits θ to 2 is processed in step 104t-iao.
This is done by alternately setting the I antenna terminal ANT■ and subroutine "CNT CLR".
Ru.

Here, the subroutine "CNT CLR" executes % steps /j4t, /3! as shown in the 14th figure.
The transfer lock period TM is controlled to be constant by clearing the interrupt counter and checking whether the contents of the interrupt counter match the period TM (set in RAM K).

Steps /-/~/ko of subroutine "TASK/" In this case, the slave microprocessor 3/ returns the message. To measure the period T82 of the bit transfer lock pulse, the microprocessor on the master side')f2/f
lf blue ten “MEASURR: 0”, “MEAS
URE /” are executed alternately.

181, /! Figure tl t7'ru f:y“
MIQ80RK O” (7) 70-chart, the contents of the error flag register are checked at step /jt, and if it is '/', it is a return, but 'θ
", the interrupt counter is cleared in step 732. Next, in step /3/, the antenna terminal ANT■
A check is made to see if is "7'", but the contents of the interrupt counter are transferred to the antenna terminal ANT in advance so that the initial value is "/"', and the lock period TM is one time. A check is made to see if the interrupt counter is below 12xTM, and control is returned to step/jtlc described above. Therefore, within the period TS in the trench where the antenna terminal ANT■ falls from "/" to "θ", the control goes step/3/→step/3→step/31→step/3... It loops and repeats over and over again. However, at some point, antenna terminal A
NT■K "θ" is transmitted, and the antenna terminal ANT■ is "OK". At that time, proceed to step /410,
Interrupt counter contents RA as total measurement clock period TS
M is stored in the corresponding area of antenna terminal AN.
The period TS where T■ becomes /" can be measured.

Also, as mentioned above, step/31 → step/3 →
Step Ill→Step/j? Even while it is looping, the interrupt routine is taking asynchronous K, and the interrupt counter is incremented each time, but the antenna terminal ANT continues to be "O" K. If not, the interrupt counter will eventually count a count value of 2 x TM.0 This indicates a communication failure, so set an error flag in the error flag register at step /ri/, Control is returned to the main program. however,
As long as the bit/no 1llJ is fixed, the antenna terminal ANT■
Since the fall from "7m to "oh" is an operation that only detects "shi", the measurement result is not adopted. The subroutine "MEASURICi", as shown in FIG. In addition to the limb condition being reversed, the subroutine “MEAE
3URE o" is the same as 0. Thus, when the return lock period measurement consisting of r bits of bits r~/4t is performed, the subroutine "TA
The interrupt counter is cleared in steps / and 2 of SK/'', and the error flag register is checked again in the next step /30.As a result, the contents of the error flag register are ``/'' and antf Control is returned to the main program, but its contents are “θ′
”, it moves to step /3/.Step /3/
, the average value of the measurement clock period TS is calculated, but here, the approximate value is calculated by majority vote and the average value of the measurement clock period TS is calculated.
The transfer lock TM that has already been stored in the 3 controllers is rewritten. In the next step /33, the contents of the interrupt counter and the transfer lock TM are compared.
l Continue counting in the interrupt counter until they match, at which point control is returned to the main program.

In parallel with the above-mentioned subroutine "TASK/", the microcomputer 37 on the slave side executes the subroutine "TASK/".
Execute TASK, 2″″. Figure m72 shows the flowchart 69, and steps /4t1 to /j7 for measuring the period TM of the transfer lock pulse sent from the master side and processing the measurement results are the subroutine "TASK/-" step /2/to /33 and t
! E is the same and also based on the measurement transfer lock period, the step of sending the clock pulse back to mask-@/! Since r~/73 is exactly the same as step /θri~/20 of the subroutine "TASK/"'', the measured value itself is 0 without i!#, and the measurement of the lock TM transferred to the bit is After completion, since bit 2 is "/", the interrupt counter is cleared at the rising edge in step /!3. Therefore, the measurement of the transfer lock period TM is performed for bits θ to g. , steps /!3 to /!7 are executed during the period of bit 7.

In addition, step/4t! ~/j2 subroutine "MliASURE o", "MEASU
RE / ” 11 1- is shown in Figure 1 and 70- Step of Tayat shown in Figure 76 9, Step /! l~
The 14th subroutine "CTRCLR" in /23
The first step consists of the steps in the flowchart shown in the figure. The figure is a flowchart of the subroutine "ERROR" in step 67 during the main program's busy time. This subroutine "F, RROR" is executed after the microphone has finished, and is the bit/4 of the communication format (in Figure 2). This is a routine that determines the value of step (■). Referring to 70-dayat in the first diagram, the interrupt counter is cleared in step/2,
Step/2! A comparison is made to see if the contents of the interrupt counter and the transfer lock period TM match.
If they match, transfer to the antenna terminal AN in step 6 to indicate that the lock has been synchronized.
T■ is set to "/1". However, if they do not match, it is checked in step /2 whether the error flag register is set to "/". As a result, the error flag is set to "/1". If it is 7M, step /2/
After setting antenna terminal ANT■ or "O"', step/2 to control! ◇However,
If the error 7 lag is "θ", the antenna terminal ANT■ is set to "II" in step /7, and the step /7 is set to "III".
At step 10, a check is made again to see if the antenna terminal ANT■ is "/". The reason for this is that the antenna terminal ANτ■ is checked on the master or slave side to indicate an abnormality.
This is because there is a possibility that θ' may be changed to "θ'" at any time, and it is necessary to check this.

At step //θ, antenna terminal ANT■ is “/”
If so, the control is step/7! , or if not, set the error flag register to "/" in step /J'/ and step /J'/! control is returned to. In this way, the subroutine “ERROR”
In the subroutine "l'AsK/",
“TASKJ” checks whether the error 7 lag register is set, and if the error flag is “/
“, the antenna terminal ANT■ is set to “θ
0 set to 1 Also, if the error flag is not set to 7M, an error transmission from the other party is detected and the antenna terminal ANT is set to N due to an error in the other party.
If set to 0'', set the error flag register to M.
/''', wait until the bit /≦ is completed, and when the contents of the interrupt counter and the transfer lock period TM match, set the antenna terminal ANT■ to "/"K and return to the main program. This step is executed.

The M/ri diagram and the 2θ diagram are flowcharts of the subroutine “TASKj” of step 2/ of the main program.
In this subroutine "TASKJ", data is transferred to the slave microcomputer 3/.

First? Referring to the flowchart in the figure, step/1
2. At #j, the antenna terminal ANT■ is set to "θ" and the subroutine "CTN CLR'" is executed, and "O" of bit/7 is sent out. In the next step /74t, /cobit data consisting of bits /♂ to -ta is transferred, and FIG.

[At step ≦− of K main program, RA
Since the data to be transferred is stored in M/K, the data is read out and serially transferred in accordance with the data management number in the subroutine "DATA OUT". As shown in Figure 2θ, step/
The data management number is cleared in step 6, and steps 792~
/9 corresponds to the specified data management number -7RAM /
Read the data stored in the location of
Then, depending on whether the data is "om" or "/1", the antenna terminal ANT2 is set to "θ1" or "7'".

The period of the allocated /bit is controlled by the subroutine “CNT CLR” (74th
(see figure), then ST20 1.20
The data management number is incremented at /. Next, when the transfer of the data corresponding to the data management numbers "θ'" to "//"' is completed, it is detected in step 202, so the subroutine "DATA OUT" is executed.
” is completed, and the K:F control is transferred to step /11 of the subroutine “TASKj”.As mentioned above, the K check bit consists of 3 bits, bits 3θ to 32, and the check bit of step /r! to 1rtB is completed. This is a companion bit that determines the value of bit 3θ, which is the first bit.In step /Fj, it is checked whether bit kota is "/', child ANT■ is set to "O'", and '
If O''', step //7 connects the antenna terminal ANT■
is set to "/". Here, step/! The subroutine “CNT CLR” of r is the step l? Similarly, the step regarding the λ-th bit of the 0 check bit, which is a subroutine that controls the transfer period of the / bit, is
It is almost the same as ri~/tsuta-, step//l~/II, but bit-! A routine is executed in which the value of is set as the value of bit 3/. When the antenna terminal ANT■ is set to "om" in step /3 and the subroutine "CNT CLR'" is executed in step /94t, bit 32, which is the third bit of the check bit, is sent to the transmission line. In the final step 191 of the zero subroutine “TASK3″′, the antenna terminal ANT■ is “/
``K is set.

Are Figures 21 and 11 steps of the main program? - is a flowchart of the passable routine "TASK4t". In this subroutine "TASK am", serial data transferred from the slave side is received and stored in RAM j K, and after checking whether there is a transfer error of the data, if there is no space for transfer, it is stored in RAM j. A step of transferring the stored data to RAM J is performed.

Referring to the flowchart in FIG. 27, the interrupt counter is first cleared in step-03, and the contents of the interrupt counter match the transfer lock period TM times the transfer lock period TM at steps θ and 2θ. A check is made to see if the antenna terminal ANT is set to "/".

If the slave side does not start data transfer even if the transfer lock period TM is twice, the terminal antenna terminal AN
If T■ does not fall to "θ''', the master microcomputer 2/ returns control to the main program without doing anything. In this way, when there is no data transfer from the slave side, RAMj to RA
M, 2K Not performed for transfer of input data.

Shikashi, Stepco θ! , the antenna terminal AMT
When it is detected that (2) has become "θ", the transfer cycle starts from that point, and the subroutine "CNT CLR" is executed in step J04.

Then, when a period corresponding to bit 3 has elapsed, the transferred data starts to be captured, but the transfer lock cycle T
Sampling data at the midpoint of M? The typing is adjusted in step 207 in order to
is executed. This subroutine “DATA IN”
As shown in Figure 2, according to the data management number,
step 22 in which input data is read into RAM j;
Consists of 4t S-230.

Therefore, in step 224t, the data management number is cleared, and in step 2λj-JJ7, the friend data transferred to the antenna terminal ANT■ is stored in the location of I(AMj) determined by the predetermined data management number. At the 0th step here, the subroutine "CNT CLR' is executed to control the period corresponding to the transfer lock period TM. Further, in the step coater, the data management number is inflated) (+ / ) is 0 Then, the stepco 30 checks whether the data management number has reached "/2"K, and if it is less than '/2"K, step 2co! The control is returned to "/" and the control is transferred to the subroutine "TASK4t". At this time, in the subroutine "TASKg",
Sampling is performed at the midpoint of 4t7 (see Figure 1), and this bit 4t7 ij is the first bit of the J bit check bit, and its value is 0, which is set in a complementary relationship with the bit black value. , in steps λ09 to 2/3, the check is performed, and if the pit is 7 or "θ" in step 2θ, it is checked in step IO whether bit at is "/"'. As a result, if bit 4t6 is “Ok”, there is no complement relationship with the value of ttd2, so the step code/
At λ, the check flag register is set, and then control is passed to the f 7 f a/s subroutine.
CNT CLR" K will be transferred. However, if the bit data is "/", the control will be transferred to StepCo1 as is.
To be transferred to 3 (Naru0 Matomo-Pitgame 2 is “/l”
If pit game g is "/11, then step -〇?
, , 2// is detected and the flag register is set, but if bit 4t7 is "/" and bit 6 is "O1", control is passed directly from step 20 to step λ73 from 2/l. .

Next step co/ri~2/? At Fi, a check is made to see if the first bit of the check bits, bitgell and bitdako, are the same. Sara K, step-
The third bit of the check bit, the pit getter, is checked to see if it is "/". If it is "/", it is set in the check miss flag register or step 2, but if it is "θ", it is set in the control. is step-2
Moved to 7. Finally, in step λ-/, it is checked whether the check miss 7 lag register is "/", and it is checked whether there is an error 9 during data transfer.Then, the check miss flag register must be "7". For example, data in RAM j is written to RAM-, but
If it is checked, the flag register will be reset and the control will be returned to the main program.The data in RAM j will not be written to RAM-. The master information subroutines "TASKJ" and "TASK4t" have been mainly explained with reference to the figure and the second λ diagram.
''' (Step 7 of the main program) K is almost the same, so its explanation will be omitted.

As described above, according to the present invention, the copying machine main body and its attached device are each provided with a microcomputer that performs serial-to-parallel conversion and parallel-to-serial conversion of data, and (1) the data is FS-modulated and transmitted from the copying machine main body to the additional device. By superimposing the signal coupler on the power supply line supplied to the power source, the conventional signal couple and the connector connecting it can be omitted, and a highly reliable serial data transfer device can be provided. Moreover, since the present invention has a simple configuration, it can be easily applied to existing photographic habits.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a conventional data transfer device, FIG. 3 is a block diagram showing an example of a data transfer device according to the present invention, and FIG. , No. ! The figure is a block diagram of the main part of the transmitting unit in Figure D, Figure 6 is a signal waveform diagram of the unit in Figure 5,
The figure is a block diagram of the main part of the receiving unit in Figure D, and Figure 1F.
Fig. 3 is a signal waveform diagram showing the unification format of the device; gg-2-Figure is a flowchart of a subroutine.
10 controller, /g...output driver, /! ...Input interface, /≦...CPU power supply circuit, /2...Additional device power supply circuit, /? ...Additional device, /ri...Sequence controller, λθA...Input interface, -/A...Output driver 1.2.2A...Output load. θ... Transmission/reception unit for copying machine body, KO/... Master side microcomputer, -2, J
λ...Master/slave changeover switch, 23~λg
, 33-36...Amplifier, 22...Master a+
Transmitting unit 1.2/... Master IJjl Receiving unit, 30... Transmitting/receiving section for additional device, 3/... Slave side microcomputer, 37...
・Slave side transmitting unit, 3/...slave side receiving unit, 3/...switch, riθ...PLL (phase lock 19 circuit,
Da/...power supply line, goo, da3...coupling capacitor, daμ...filter circuit, j/v/control storage section, jλ/
...l' (AM (unwanted access memory) section, j3... performance logic unit, j4t... accumulator, DCR... decoder,
ROM...Read-only memory, Patent applicant Canon Co., Ltd. Figure 5 Figure 6 Figure 9 Figure 18

Claims (1)

[Claims] A microcomputer having a program for serial-parallel conversion and parallel-serial conversion of data is provided in the main body of the copying machine and its additional device, respectively, and the data is connected to a power supply line supplied from the main body of the copying machine to the additional device. A data transfer device 0 characterized in that data is serially transferred between the copying machine main body and the additional device by superimposing