JPS5895985A - Controller for output voltage of inverter - Google Patents

Abstract

PURPOSE:To suppress the variation in the output voltage upon variation of a load by providing an auxiliary set input forming circuit which regulates the set voltage value in response to the output of a comparator. CONSTITUTION:When a load current abruptly increases, the lower limit set value does not rapidly follow up the variation for the variation in the output voltage of a rectifier 8 upon abrupt increase of the load current. Accordingly, the output voltage of the rectifier 8 introduced to a comparator 13 exceeds the upper limit set value from a voltage dividing resistor 15. In this manner, the comparator 13 is operated to operate a monostable circuit 17. In the meantime, a constant voltage having the opposite polarity to the polarity of the output of the circuit 17 is presented at the output terminal of a comparison amplifier 19, is produced by the voltage dividing resistor 20, and is introduced as an auxiliarily set input DELTAV to a voltage regulator. Thus, the set voltage value is enhanced, thereby enhancing the output voltage of the inverter and suppressing the abnormal decrease in the output voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter output voltage control device, and an object thereof is to suppress output voltage fluctuations due to load fluctuations.

FIG. 1 shows a general configuration example of an inverter output voltage control device equipped with such an output fluctuation suppressing means. Reference numeral 1 denotes an inverter made of a semiconductor such as a thyristor or a transistor, and its output voltage is controlled by a voltage regulator 3 via a pulse phase control section 2. The voltage regulator 3 receives a voltage setting value r from a setting device (not shown) and a transformer 4.
．． Output voltage detection value V, taken out via rectifier S and filter, ! A control signal for the pulse phase control section 2 is generated by applying, for example, proportional-integral calculation to the deviation of :.

The voltage control loop configured in this way allows high n*
+c'It pressure is maintained at the set value. However, if the load changes suddenly and greatly, the voltage control system cannot follow it immediately, and as a result, a fairly large voltage control deviation occurs in a transient manner. In order to suppress this, the detected current value taken out via the current transformer 7 and rectifier 8 is differentiated by a differentiating circuit 9, and this is led to the voltage regulator 3 as an auxiliary setting input. For example, when the load current suddenly increases,
In order to suppress the abnormal transient drop in the output voltage, the differential circuit 9 applies supplementary setting power to the voltage cylinder 3 to temporarily increase the voltage setting value. Conversely, in response to a sudden decrease in load current, an auxiliary setting input is provided to the voltage regulator 3 to temporarily increase the voltage setting value. In this way, transient output voltage fluctuations can be effectively suppressed.

However, when the inverter 2 is a single-phase inverter, the current detector led from the differential circuit 9 to the differential circuit 9 has a much larger ripple than that of a three-phase inverter. , differential circuit 9
will operate in the same way as when there is a sudden change in current, which will have an adverse effect on the voltage control system. If a ripple-absorbing filter is inserted into the output section of the rectifier 8 in order to avoid this, the filter time constant becomes so large that the transient fluctuation μ control of the output voltage due to load fluctuations cannot be fully exerted.

It is an object of the present invention to prevent transient output fluctuations from occurring without the above-mentioned problems even when the waveform obtained by rectifying the output of an output current detection converter has large ripples (especially in the case of a single-phase inverter). The objective is to provide a device that can suppress this.

This object is achieved according to the invention by the features described in the claims.

The following is a circuit diagram showing essential parts of the device of the present invention shown in FIG. 2.

FIG. 2 shows a circuit part used according to the invention to replace the inverter 9 shown in FIG. 1, in which the output of the rectifier 8 of FIG. on the other hand through filters 11 and 12 respectively to comparator 13.
, 14.

The time constants of filters 11, 12 are not chosen so large that response delays become a problem. Peak value hold circuit 10
The output voltage of is applied to the voltage dividing resistor 15.16.
The output voltage of the L converter 8 is divided by the voltage divider 15 in the comparator 13.
The output voltage is compared with the upper limit set value from the voltage divider 16, and compared with the lower limit set value from the voltage divider 16 in the comparator 14.

The outputs of comparators 13 and 14 are each monostable circuit 1
I am led to 7.18. The monostable circuits 17, 18 operate for a certain period of time when the comparators 13, 14 are activated.

The outputs of the cross-bank stabilizing circuits 17 and 18 are differentially input to the comparator amplifier 19. The output of the comparison amplifier 19 is gain-adjusted by a voltage dividing resistor 20 and inputted to the voltage regulator 3 as an auxiliary setting manual power ΔV.

The discharge time constant of the peak value hold circuit between the hold capacitor and the voltage divider resistor 15, 16 remains sufficiently large so as to slowly track the peak value of the inverter output current. The upper and lower limits of the output voltage of the rectifier 8 are set by both voltage dividing resistors 15 and 16. /(-In the case of evening, the zero point is traced back every half cycle, so the filter 1 raises the lower level so that the comparator 14 does not respond at this time.
2 is provided. The filter 12 may be replaced by means such as a limiter circuit, which increases the output voltage of the rectifier 8 to a lower level so that the comparator 14 does not respond under normal operating conditions. On the other hand, the manual filter 11 of the comparator 13 that performs the comparison with the upper limit value or an element having an equivalent function can be omitted.

By doing as described above, in a steady state or slow fluctuation of the load, the output voltage of the rectifier 8 is set each time by the voltage dividing resistor 15, 16, and is within the lower limit value. , the outputs of Combare 413.14 are all zero, and the output is monostable w&17.

18 is not activated, and the output of comparison amplifier 19 is also zero.

When the load current i increases rapidly, the resulting change in the output voltage of the rectifier 'a8 is obtained from the voltage dividing resistor 15 and 16 via the peak value hold circuit.

Since the lower limit set value does not immediately follow the change, the output voltage of the rectifier wh8 guided to the comparator 13 exceeds the upper limit set value from the voltage dividing resistor 15. This causes the comparator 13 to operate and the monostable circuit 17 to operate. On the other hand, the output of the comparator 14 does not change, so the output of the monostable circuit 18 is at zero potential. Therefore, while the monostable circuit 17 is operating, a constant voltage having a polarity opposite to the output polarity of the monostable circuit 17 appears at the output terminal of the comparison amplifier 19. This voltage is taken out with a gain adjusted in advance by the voltage dividing resistor 20, and is led to the voltage regulator 3 in FIG. 1 as an auxiliary setting manual power Δ■.

This means that the voltage setting value for the voltage regulator 3 has been increased, and the voltage node 1s3 acts on the inverter 1 via the pulse phase control unit 2 to increase the output voltage. As a result, a transient abnormal drop in the output voltage of the inverter due to a sudden increase in load current is suppressed. The supplementary setting manual power Δ■ is when the upper and lower limit values catch up to correspond to the output voltage of the rectifier 8 according to a time constant determined by the capacitor chamber of the peak value hold circuit 10 and the resistance value of the voltage dividing resistor 15.16. The comparator 13 returns to its original state. Conversely, when the load current suddenly decreases, the comparator 14 operates and operates the monostable circuit 18, so the comparison amplifier 19
generates an output voltage with a polarity opposite to that in the case of a rapid increase in load current, and this output voltage is taken out as an auxiliary setting manual power ΔV via a voltage dividing resistor 20 and applied to the voltage cylinder 3. In this case, the auxiliary setting manual power ΔV has the effect of lowering the voltage setting value equivalently. This suppresses a transient abnormal rise in the inverter output voltage due to a sudden decrease in load.

Furthermore, when the load current is at a low level, even if the load current suddenly changes, it will not have any effect on the inverter output voltage, so when the load current is at a low level, the supplementary setting human power ΔV
It is advisable to add a means to forcibly keep it at zero. This avoids the risk of overcompensation. Such means include, for example, a switch element that monitors the output voltage of the peak value hold circuit 1o and blocks the transmission of the auxiliary setting manual power Δ■ to the regulator 3 while the output voltage is below a predetermined limit value. Good for use.

As described above, according to the present invention, it is possible to configure an inverter output voltage fluctuation suppressing circuit that is applicable even when the inverter is a single-phase inverter and the shaped waveform of the output current has a large lip.

[Brief explanation of drawings]

1 is a circuit diagram showing an example of a conventional device, and FIG. 2 is a circuit diagram showing a main part of an embodiment of the device of the present invention. 1... Inverter, 2... Pulse phase control means, 3
...Voltage-cylindrical device, 7...Current transformer, 8...Rectifier,
10... Peak value hold circuit, 12... Filter, 13.14... Comparison circuit, 15.16... Voltage dividing circuit, 17-2o... Complementary setting input forming circuit. Talent 1 2nd mouth

Claims (1)

[Claims] 1) A current transformer that detects the inverter output current in an inverter output range suppression @ device equipped with a voltage cylinder that acts on the pulse phase control means of the inverter in order to match the detected output voltage value of the inverter with the voltage setting value. A rectifier that rectifies the output of this current transformer, a peak value hold circuit to which the output of this rectifier is guided, and the output voltage of this peak value hold circuit is divided by two coefficients to determine the upper limit and lower limit. A voltage dividing circuit for setting a value, a comparison circuit for comparing each of the upper limit value and lower limit value from this voltage dividing circuit with the output voltage of the rectifier, and a circuit portion for comparing the lower limit value of the comparison circuit. Level adjusting means such as a filter for raising the lower level of the rectifier output voltage led thereto; and an auxiliary setting input forming circuit for providing the voltage regulator with an auxiliary setting input having a polarity that increases the voltage setting value and equivalently lowers the voltage setting value when the voltage falls below the lower limit value. Features: Inverter output voltage control device