JPS589579A - Circuit for controlling reversible power conversion - Google Patents

Circuit for controlling reversible power conversion

Info

Publication number
JPS589579A
JPS589579A JP56106029A JP10602981A JPS589579A JP S589579 A JPS589579 A JP S589579A JP 56106029 A JP56106029 A JP 56106029A JP 10602981 A JP10602981 A JP 10602981A JP S589579 A JPS589579 A JP S589579A
Authority
JP
Japan
Prior art keywords
circuit
power
gates
closed
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56106029A
Other languages
Japanese (ja)
Inventor
Keiji Maeda
前田 啓二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56106029A priority Critical patent/JPS589579A/en
Publication of JPS589579A publication Critical patent/JPS589579A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/162Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
    • H02M7/1623Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To obtain highly reliable control operation by connecting gates which are opened and closed in response to the respective output signals of multiplexed detecting circuit in series, and performing switching based on the conditions that all gates are opened or closed. CONSTITUTION:A reversible power converter TH is provided between an AC bus line AL and the reversible input and output of the power, and selectively operates either of a thyristor circuit THF or THR based on the transmitting direction of the power. The transmitting direction of the multiplexed power is detected by power transmitting direction detecting circuits DCD1 and DCD2. The zero current state of the DC bus line of the thyristor circuits detected by zero current detecting circuit ZCD1 and ZCD2. A flip flop circuit is operated by both detector circuits, and a plurality of the gates B1-B4 are opened and closed by the outputs. Only when it is detected that the gates B1 and B2 and B3 and B4, which are connected in series, are all opened or closed by a detector DET, the outputs which supply the gate signals are generated.

Description

【発明の詳細な説明】 との発明は、交流母線と、この交流母線に対して電力の
可逆的な出入力を行う!Ri置との間に挿入され次第1
および第2のサイリスタ回路のい□ずれか一方な電力の
転送方向に対応して選択的に動作させる電力可逆変換制
御回路に関するものである。
[Detailed Description of the Invention] The invention includes an AC bus and reversible input/output of power to the AC bus! As soon as it is inserted between the Ri position 1
The present invention also relates to a reversible power conversion control circuit that selectively operates the second thyristor circuit in accordance with one of the power transfer directions.

従来、この種の□回路として第1図に示すものかあった
。第1図において、電力可逆変換装置THは、3相の交
流母線ALK変圧器TR’&介し工接続され、交流母線
ALから直流機Mへ電力l転送する第1のサイリスタ回
路THFと、前記とは逆方向へ電力な転送ブ、る第2の
サイリスタ回路THRとを有し、グートイa号分配回路
CDから(れぞねゲート信号GF 、GRか供給される
ようになつ用い る。−力、電力可逆変換装@THの直流母線P$Pよび
N間には、七の間の電圧を検出ブる電圧センtvSが接
続され、この電圧センサ■Sと韮列に、リアクトルL訃
よび電流センfsH’i介して1流機Mが接続1t1z
いる。電流センサSHは、これを通して流むる電流な検
出するkめのものである。1六零電流検出回路ZCDは
、ゲートパルス発住回路GPG、電圧センサvSをよび
電流センサSI(の出力信号の各出力により、直流母#
P。
Conventionally, this type of □ circuit was shown in FIG. 1. In FIG. 1, the reversible power converter TH includes a three-phase AC bus ALK transformer TR' and a first thyristor circuit THF that is connected via an intermediary and transfers power from the AC bus AL to the DC machine M; has a second thyristor circuit THR that transfers power in the reverse direction, and is used so that the gate signals GF and GR are supplied from the gate distribution circuit CD. A voltage sensor tvS that detects the voltage between 7 is connected between the DC buses P and N of the reversible converter @TH, and a reactor L and a current sensor fsH are connected in parallel with this voltage sensor S. 1st class machine M is connected via 'i 1t1z
There is. The current sensor SH is the kth one that detects the current flowing through it. The zero current detection circuit ZCD detects the DC bus # by the output signals of the gate pulse generation circuit GPG, the voltage sensor vS, and the current sensor SI.
P.

NK電流が存在しカいことを検出する。DCDは電力の
転送方向を検出する回路である。
Detects the presence of NK current. DCD is a circuit that detects the direction of power transfer.

第2図にゲート信号分配回路GDの詳細な示t。FIG. 2 shows a detailed diagram of the gate signal distribution circuit GD.

この回路は、零電流検出回路ZCDの出力がrlJレベ
ルであることを条件に、電、力転送方同検出回路DCD
の出力に応じて、91女はQを出力するD−フリップフ
ロップと、この出力に応じてゲート48号GPをGF’
!穴はGRとして出力するAND回路C,Dとによって
構成されている。第3図は第1図および第2図の回路の
各部の動作波形を示すもので、第3図(a)は電圧セン
サvSの出力波形、(b)はゲートパルス発注回路GP
Gの出力波形、(e)は電流センサSHの出力波形、(
d)は電力転送方向検出回路DCDの出力波形、(、)
は零電流検出回路ZCDの出力波形、(f)はD−7リ
ツプフロツプのQ出力波形、(2))ねゲート信号GF
の波形、そして(荀はグートイ9月GRの波形1七わそ
れ示す。この波形かられかるように、ゲート信号GPt
j、零電流検出回路ZCDの出力がrlJであることを
条件に、電力転送方向検出回路DCDの出力に応じて、
サイリスタ回路THFま大はT HRl/(供給される
。このようが動作により、循環電流なしでサイリスタ回
路THFおよびTHR間の切換えが行わ4る。
This circuit detects current and force transfer detection circuit DCD on the condition that the output of zero current detection circuit ZCD is at rlJ level.
In response to the output of , the 91st woman connects a D-flip-flop that outputs Q, and in response to this output, gate No. 48 GP is connected to GF'.
! The hole is constituted by AND circuits C and D which output as GR. Figure 3 shows the operating waveforms of each part of the circuits in Figures 1 and 2. Figure 3 (a) is the output waveform of the voltage sensor vS, and (b) is the output waveform of the gate pulse ordering circuit GP.
(e) is the output waveform of current sensor SH, (
d) is the output waveform of the power transfer direction detection circuit DCD, (,)
is the output waveform of the zero current detection circuit ZCD, (f) is the Q output waveform of the D-7 lip-flop, and (2)) is the gate signal GF.
and (Xun shows the waveform 17 of Gutoi September GR. As can be seen from this waveform, the gate signal GPt
j, depending on the output of the power transfer direction detection circuit DCD, on the condition that the output of the zero current detection circuit ZCD is rlJ,
The thyristor circuit THF is supplied with THRl/(.This operation results in switching between the thyristor circuits THF and THR without circulating current.

しかし上記のような従来の回路では、零電流検出回MZ
CDの出力が故障等によりrlJK変化し大場合、ある
いは第2図中のAND回路C,Dが故障してQ、Q出力
をともに「1」と判断するように働いた場合、主回路電
流が零でない(でもかかわらず、ゲート信号の切換えが
実行さねたり、ヤイリスタ回路THF訃よびTHRの両
方にゲート信号が供給されてし1うなどの欠点があり大
However, in the conventional circuit as described above, the zero current detection circuit MZ
If the CD output changes significantly due to a failure or the like, or if AND circuits C and D in Figure 2 fail and work so that both Q and Q outputs are judged as "1", the main circuit current (Nevertheless, there are major drawbacks such as the gate signal switching not being executed and the gate signal being supplied to both the iris register circuit THF and THR.)

この発明は、前記のような従来回路の欠点を除去する大
めになさf1πもので、電力可逆変換装置のサイリスタ
回路間で切換えを行う際に、多重化さt′I六検六回出
回路れぞれの出力信号にし穴かつて開閉するゲートを直
列に接続し、各ゲートがブベて閉もしくは開であること
を榮件に切換えな実行することにより、信頼性の高い制
御動作が得られるようにし大電力可逆変換制御回Mを提
供することを目的としている。
This invention eliminates the drawbacks of the conventional circuit as described above, and is designed to provide a multiplexed t'I six-detection six-output circuit when switching between thyristor circuits of a reversible power converter. Highly reliable control operation can be obtained by connecting gates that open and close in series with each output signal, and switching between each gate depending on whether it is closed or open. The object of the present invention is to provide a high-power reversible conversion control circuit M in this manner.

以下にこの発明の一実施例を第4図について説明する。An embodiment of the present invention will be described below with reference to FIG.

この例では2重化し大場合を示しているか、3重もしく
はそわ以上に多重化し大場合も同様トナル。第4図Kl
lて、ZCDl 、ZCD2は第2図KZCDで示し穴
ものと同一機能を有する相互に独立し六零電汗検出回路
、DCDI 、DCD2は第2図のDCDと同一機能を
有する電力転送方向検出口121をそれぞね示す。ま大
B1.B2゜B3.B4は、信号線BIG、B2G、B
3G。
In this example, the case where the signal is doubled and large is shown, or the case where the signal is tripled or multiplexed to a large extent is also shown. Figure 4 Kl
In addition, ZCD1 and ZCD2 are mutually independent six-zero electric perspiration detection circuits having the same functions as the one shown in FIG. 2 KZCD, and DCDI and DCD2 are power transfer direction detection ports having the same functions as the DCD in FIG. 121 respectively. Madai B1. B2゜B3. B4 is the signal line BIG, B2G, B
3G.

B2Oを通してrlJの信号か供給され六ときに開(導
通)となるゲート、R1−R6は固足抵抗である。抵抗
R1〜R4tiゲートB1〜B4に七ねそれ並列に接続
され、1大抵抗R5Fi抵抗R1゜R2と、抵抗R6は
抵抗R3,R4とそれぞt′L厘列に接続されて抵抗回
12Iを構成し、各抵抗回路は、バイアス回路BIAS
により用足の電圧の印加を受けている。を大nE’rt
i個号線GFおよびGR間の電位を検出する電位検出回
路である。
The gates R1-R6 are fixed-leg resistors that are opened (conductive) when the rlJ signal is supplied through B2O. Resistors R1 to R4ti are connected in parallel to gates B1 to B4, one large resistor R5Fi is connected to resistor R1゜R2, and resistor R6 is connected to resistors R3 and R4 in series t'L, respectively, to form a resistor circuit 12I. and each resistor circuit has a bias circuit BIAS.
The voltage of the foot is applied. The big nE'rt
This is a potential detection circuit that detects the potential between i-numbered lines GF and GR.

零電位検出回路ZCD1 、ZCD2、電力転送方同検
出回NDCD1 、DCD2、シよび2組のD−フリッ
プフロップが正常に動作し、信号線BaO上の信−1’
!Qが「l」であれば、@旧線BIG訃よびB4C上の
信号は「0」、信月線BJG上の信号はrlJとなり、
シ穴がってゲートB3 、B4は開とがる。このため2
477回路BIASから抵抗R6の両端間に用足の電圧
が印加さね、伯−@線GP上の電位な零電位とすると、
信号線GF上の電位は零電位である。一方、グー)B1
 、B2は閉で69、バイアス回12iBIAsの出力
電圧を−EBとすると、信号線GR上には、 で表わさねる電位が現わ4る。すなわち制御回路か正常
に動作している場合、信号線GFをよびGRのうち、い
ず汎か一方の電位は零であ)、マ大他方の電位は で足する値となる。
The zero potential detection circuits ZCD1, ZCD2, power transfer detection circuits NDCD1, DCD2, and two sets of D-flip-flops operate normally, and the signal -1' on the signal line BaO is
! If Q is "l", the signal on the old lines BIG and B4C will be "0", the signal on the Shingetsu line BJG will be rlJ,
Gates B3 and B4 open as the holes open. For this reason 2
Assuming that no voltage is applied between the ends of the resistor R6 from the 477 circuit BIAS, and the potential is zero, which is the potential on the line GP,
The potential on the signal line GF is zero potential. On the other hand, Goo) B1
, B2 is closed and 69, and the output voltage of the bias circuit 12iBIAs is -EB, a potential expressed as follows appears on the signal line GR. That is, when the control circuit is operating normally, the potential of one of the signal lines GF and GR is zero (zero), and the potential of the other one is the sum of the two.

一方、前述の回路に何らかの故障が生じ、相互に直列に
接続されている2つのゲートのうちの一方だけが開(1
には閉)となるように動作し穴とする0例としてゲー)
B3か開、ゲートB4が閉とηつ穴場合を想足すると、
信号線GFの電位はとな夛、正常な場合の電位と比較す
ると、の関係になる。ブなわち上記の故障時には、信号
線CFの電位ね正常時よりも高くなる。
On the other hand, some kind of failure occurs in the circuit described above, and only one of the two gates connected in series opens (1
(For example, game)
If we consider the case where B3 is open and gate B4 is closed, we have two holes:
When comparing the potential of the signal line GF with the potential in a normal case, the relationship is as follows. In other words, when the above-mentioned failure occurs, the potential of the signal line CF becomes higher than when it is normal.

検出回路DETね、信号iGF$>よびGRの電位を検
出し、 で足めらする範囲内にβの値があるときに出力信号を発
生する。βの値が上記の帥四内にあるということは、相
互Km列に接続さネタゲートがともに開−」は閉)の状
態にはないことを意味するので、βの値を検出すること
によって、グートイ9月分配回路G D K 48月を
供!@フる回路を含む範囲の誤動作を検出ブることがで
きる。検出回路DETの出力信号は、信号線GSK送出
され、ゲートパルス発生回路GPGを直ちに停止させる
ために使用される。
The detection circuit DET detects the potentials of the signals iGF$> and GR, and generates an output signal when the value of β is within the range determined by . If the value of β is within the above range, it means that the gates connected to each other in Km columns are not in the open state (closed), so by detecting the value of β, , Good Toy September distribution circuit G D K 48 months provided! It is possible to detect malfunctions in a range that includes circuits. The output signal of the detection circuit DET is sent to the signal line GSK and is used to immediately stop the gate pulse generation circuit GPG.

以上のようにこの発明では、−t−nそれが独立し六零
電流検出回路および電流転送方向検出回路の出力で駆動
される独立しπD−フリップフロップ回路な設け、相互
に直列に接続さ−1172:複数のダートに各D−フリ
ップフロップ回路のQ出力訃よびQ出力′ft用足の関
係にし六がって七の11で、あるいけ反転して供給して
いる。名ゲートと各D−フリツプフロツプの出力との関
係は、正常時には相互に直列に接続され大ゲートがすべ
て開1穴は閉に7ffiるが、異常時Kiゲートの一部
か開1六は閉で、残りがその逆の状態となるように設足
さねている。このゲートの開閉状態は検出回路によって
検出され、正常状態にあるときのみ、選択さtπ側のサ
イリスタ回路にゲートパルスが供給される。し六がって
多重化さfiff回路の一部だけ方誤動作しても、サイ
リスタ回路へのゲート信号の供給は直ちに停止され、信
頼性の高い制御が行える効果がある。
As described above, in the present invention, an independent πD flip-flop circuit is provided, which is independently driven by the outputs of the zero current detection circuit and the current transfer direction detection circuit, and is connected in series with each other. 1172: A plurality of darts are inverted and supplied in accordance with the relationship between the Q output of each D-flip-flop circuit and the Q output 'ft. The relationship between the main gate and the output of each D-flip-flop is that during normal operation, they are connected in series and all the large gates are open and the first hole is closed, but when an abnormality occurs, some of the large gates are open and the first hole is closed. , the rest are set up so that the opposite situation occurs. The open/close state of this gate is detected by a detection circuit, and a gate pulse is supplied to the selected thyristor circuit on the tπ side only when the gate is in a normal state. Even if only a part of the multiplexed Fiff circuit malfunctions, the supply of the gate signal to the thyristor circuit is immediately stopped, resulting in highly reliable control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電力可逆変換制御回路のブロック図、第
2図はそのゲート信号分配回路のブロック図、第3図は
七の動作波形図、第4図はこの発明の一実施例による電
力可逆変換制御回路のゲート信号分配回路のブロック図
である。 TH・・・電力司逆変換装回、THF 、THR・・・
サイリスク回路、AL・・・交流母線、TR・・・変圧
器、M・・・直流機、■S・・・電圧センサ、SH−・
・電流センサ、GD・・・ゲート信号分配回路、P、N
・・・直流母線、ZCD・・・零電流検出回路、GPG
・・・ゲートパルス発生回路、DCD・・・電力転送方
間検出回路。 な訃、図中同−符月は同−又は相当部分を示す〇代理人
   葛 野 伯 −(ほか1名)第1図 ≦3図 手続補正書(自発) 昭和56年12月16日 2、発明の名称 電力可逆変換制御回路 3、補正をする者 事件との関係   特許出願人 代表者片由仁へ部 4、代理人 、(’+) 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容 (1)明細書第6頁第2行に「零電位検出回路」とある
のを「零電流検出回路」と補正する。 (2)明細書第6頁第10行に「GP上の電位を零電位
とすると」とあるのを「GP上の電位を正電位とすると
」と補正する。 (3)明細書第6頁第11行に「電位は零電位である。 」とあるのを「電位は正電位である。」と補正する。 (4)明細書第6頁第14行に (5)明細書第6頁末行に とあるのを と補正する。 (6)明細書第7頁第5行に「ゲー)B3が開、ゲー)
B4が閉」とあるのを[ゲー)B4が開、ゲートB3が
閉」と補正する。 (7)明細書第7頁第7行に (8)明11iBtIIk第7頁第9行にとあるのを と補正する。 (9)明細書第7頁第14行に とあるのを と補正する。
FIG. 1 is a block diagram of a conventional power reversible conversion control circuit, FIG. 2 is a block diagram of its gate signal distribution circuit, FIG. 3 is a diagram of operation waveforms, and FIG. 4 is a power supply according to an embodiment of the present invention. FIG. 3 is a block diagram of a gate signal distribution circuit of the reversible conversion control circuit. TH...Power converter circuit, THF, THR...
Cyrisk circuit, AL...AC bus, TR...transformer, M...DC machine, ■S...voltage sensor, SH-...
・Current sensor, GD...Gate signal distribution circuit, P, N
...DC bus, ZCD...zero current detection circuit, GPG
...Gate pulse generation circuit, DCD...Power transfer method detection circuit. 〇Representative: Haku Kuzuno (and 1 other person) Written amendment to procedures for Figures 1≦3 (voluntary) December 16, 1982 2, Name of the invention: Reversible power conversion control circuit 3. Relationship with the person making the amendment: Patent applicant representative Kata Yuhito Department 4: Agent ('+) 5. Detailed description of the invention in the specification to be amended Column 6, Contents of correction (1) In the second line of page 6 of the specification, the phrase "zero potential detection circuit" is corrected to "zero current detection circuit." (2) On page 6, line 10 of the specification, the statement "assuming the potential on GP is zero potential" is corrected to "assuming the potential on GP is positive potential". (3) In the 11th line of page 6 of the specification, the statement "The potential is zero potential" is corrected to "The potential is positive potential." (4) On page 6, line 14 of the specification. (5) On the last line of page 6 of the specification. (6) On page 7, line 5 of the specification, “Game) B3 is open, Game)
The phrase "B4 is closed" is corrected to "[game] B4 is open and gate B3 is closed." (7) In the specification, page 7, line 7, (8) Ming11iBtIIk, page 7, line 9 is corrected. (9) The statement on page 7, line 14 of the specification is amended as follows.

Claims (1)

【特許請求の範囲】[Claims] 交流母線と、この交流母線に対して電力の可逆的な出入
力を行う装置との間1挿入さh+第1および第2のサイ
リスタ回路のい□ずれか一方を電力の転送方向に応じて
選択的に動作させる電力可逆変換装置に訃いて、多重化
され′大電力の転送方向を検出する電力転送方向検出回
路と、上記サイリスタ回路の直流母線の零電流状態i検
出する零電流検出回路と、上記電力転送方向検出回路お
よび零電流検出回路の出力で駆動されるフリップ7μツ
ブ回路と、この7リツプフロツプ回路の出力で開閉する
複数のゲートと、相互に直列に接続され六ゲートがすべ
て開または閉であることを検出している間だけ、上記サ
イリスタ回路のいすtか一方にゲート信−@を供給する
ための出力を発生する検出回路とを備えた電力可逆変換
制御回路。
1 is inserted between the AC bus and a device that performs reversible input/output of power to the AC bus, and one of the first and second thyristor circuits is selected depending on the direction of power transfer. a power transfer direction detection circuit that is multiplexed and detects the direction of transfer of high power, and a zero current detection circuit that detects the zero current state of the DC bus of the thyristor circuit; A flip 7μ tube circuit driven by the output of the power transfer direction detection circuit and zero current detection circuit, and a plurality of gates that are opened and closed by the output of the 7 flip-flop circuit are connected in series with each other so that all six gates are open or closed. and a detection circuit that generates an output for supplying a gate signal -@ to one of the thyristor circuits only while detecting that the thyristor circuit is in the thyristor circuit.
JP56106029A 1981-07-06 1981-07-06 Circuit for controlling reversible power conversion Pending JPS589579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56106029A JPS589579A (en) 1981-07-06 1981-07-06 Circuit for controlling reversible power conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56106029A JPS589579A (en) 1981-07-06 1981-07-06 Circuit for controlling reversible power conversion

Publications (1)

Publication Number Publication Date
JPS589579A true JPS589579A (en) 1983-01-19

Family

ID=14423206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56106029A Pending JPS589579A (en) 1981-07-06 1981-07-06 Circuit for controlling reversible power conversion

Country Status (1)

Country Link
JP (1) JPS589579A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62177031U (en) * 1986-01-22 1987-11-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62177031U (en) * 1986-01-22 1987-11-10

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