JPS589577A - Method for judging fault in plurality of power source devices - Google Patents

Abstract

PURPOSE:To judge the fault in the power source device, by comparing the absolute values of unbalanced currents and the average values of outputs, and detecting the fact that the differences has a specified polarity and exceeds a specified value. CONSTITUTION:When the power source device INV1 fails, a fault current I11 is applied on the power source device INV1. The unbalanced component expressed by i11=I11/k is detected by a current detector CUD1. Meanwhile said fault current I11 flows to the other power source devices. The unbalanced current -i11/(n-1) are detected by current detectors UCD2-UCDn. Therefore the values expressed by¦ri11¦=Vo2 and Vo2/(n-1) are outputted to absolute value detectors ACD1 and ACD2-ACDn. The average output value voltages Vo2.2/(n-1) of said values are applied between bus lines B3 and B4. Then voltages expressed by Vo2{1-2/(n-11>0 and no2}-1/(n-1)<0 are detected across output resistors R1 and R2-Rn. Therefore the fault is judged by detecting the difference.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure determination method in a system in which a plurality of power supply devices, particularly inverter devices, are operated in parallel.

In general, in a so-called parallel operation system where multiple power supplies are operated in parallel to supply power to a common load, if a failure occurs, that power supply is disconnected from the power supply system, and the remaining power supplies supply power to the load. By continuing to do so, the reliability of power supply can be improved. Therefore, a failure detection device that detects a failure in each of a plurality of power supply devices is extremely important for the reliability of a parallel operation system.

However, in the case of each power supply device, particularly an inverter device, a very large number of component parts are used to construct the circuit, making it difficult to detect all faults that may exist over a wide range. From this point of view, a method is typically used to represent the failure detection of an inverter device by detecting a failure in the oscillator circuit, failure detection in the logic control circuit, and commutation failure detection in the inverter circuit, but since these circuits operate logically, failure detection is difficult. This is effective because it is relatively easy to operate and is the main circuit part of the invar devices operated in parallel. However, as a matter of course, such conventional methods were effective only for failures in the circuit section.

In other words, the output voltage detection control circuit and unbalanced current detection control circuit, which are other important factors for failure in an inverter device, which is an example of a power supply device, and are also important factors for failure in a general power supply P3 device. Failures in so-called analog control circuits such as circuits, failures in inverter transformers and AC filter circuits, failures in forward conversion circuits and DC smoothing circuits, failures in battery connection circuits and their detection circuits, and failures in connection parts within or between these circuits. It is almost powerless against breakdowns. Even if an attempt is made to improve the reliability of the parallel operation system by detecting failures in power supply devices that exist over a wide range, the failure detection device will be expensive and complicated, which will further reduce the reliability of the failure detection device. As a result, it becomes something that cannot be put into practical use.

In view of the above-mentioned points, the present invention provides a device that effectively expands the failure detection function by detecting failures over a wide range of power supplies in a parallel operation system by quickly and reliably determining the number ζ using an extremely simple configuration. It provides a method to achieve this. The present invention will be explained below with reference to the drawings. Figure 1 is a main control system diagram showing a specific example according to the present invention.
An example of application in a single-phase power supply parallel operation system is shown. In the figure, INV, , INV2.・・・・・・
INvn is the parallel power supply unit, W is the load,
UCDl, UCD2. ---UCDn is a current detection circuit, ACDl.

ACD2. ...ACDn is an absolute value detection circuit, R
1, R2,...Rn is the output resistance, 0CD1.0
CD2. . . . 0CDn indicates a current detector, and SCW indicates a signal common connection portion. Here is the current detection circuit UCD1
．． UCD2.・・・・・・UCDn is each current transformer C
T11+CT21 * ""...CTnl and its secondary resistance R11+ R21+ """ RHL and further the current transformer CT12sCT22+ which is a signal current detector
...Comprised of CTn2, absolute value detection circuit C
D1. People CD21......People CDn each have a rectifier RP1゜RFfi,...RFn and its output resistance R12+R21m...Bn! It becomes more.

The circuit configuration shown in Figure 1 of Figure 4 consists of a system in which the power outputs of power supplies INV1 to INvn are commonly connected to supply power to a load W, and current transformers CTII to c'
The signals are connected from the output terminal of rn through the current transformers c'r12 to CTn2 to the buses B, , and Bg at the signal common connection part SCW, and the outputs of the absolute value detection circuits CD1 to CDn are used for current detection. The output resistors R1 to Rn, which generate the signals OCD and 0CDn#, are commonly connected to the bus lines N31 and B4 at the signal common connection portion SCW.

Now, in such a configuration, the output current of each power supply device is
, 'X2...in, and assuming that the load current is to, equation (1) holds true.

t, +t2+・・・・・・・・・+in fable to
・・・・・・(1) Also, the current that each power supply unit shares equally under normal conditions is (Io/
%). Here, current transformer CT11 * CT23 +
. . . If the current transformation ratio of CTnl is k, the secondary current 'L1+''l+ . . . is expressed by equation (2).

i, = (i, /k) chi■ (I2/Fc)...
...Lux (in/k)... (2) Therefore, L112+...L, W (io/k)...
...(3). Also, the voltage between the bus bar “1 + J” is 101
, the resistance values of the secondary resistors R11 to Rnl, and the current transformer C11
l,2~C'l'n! Primary 6 Therefore, (9-0, /B) - (to/k), therefore, as shown in equation (6), current transformers CT11 to CTn
The current '11~Lml flowing through lI is the difference between the vector current X1~1 which is output by each power supply device and the vector current (i6/n) that each power supply device should share in normal operation, that is, the unbalanced current. This indicates that

Here, the resistance values of the output resistors Rts to Rn11 are determined.
7, and the circuit resistance value is the same r, the absolute value lr"ll I~l from the absolute value detection circuit CD1~ACDn
rLEll 1 will be detected. Furthermore, this detection output serves as an output resistor R1 to Rn that acts as a calculation resistor.
Since they are commonly connected through the bus, if the resistance values of these IL1 are equal, the voltage 'ox between the bus lines B51B4 is (
7), and the average value is obtained.

Therefore, the difference between the unbalanced current of each power supply device and their average value, that is, (lL
ll+-'+12) + (l'1ll-'111)*
A detection voltage of """(1'5l-Voz) is generated. This means that the detection voltage for the failed power supply has positive polarity, and the detection voltage for other healthy power supplies has negative polarity. From this, it is possible to specifically determine that the current detectors 0CD1 to 0CDn are malfunctioning when the detected voltage input has positive polarity and exceeds a specified value.

Next, an example of the failure determination will be described in detail. When a failure occurs in the power supply device INV1, the power supply device INV.

Assuming that the fault current "Ill" is added to the current (I67'n) that should be shared in the normal state, the current detection circuit UCD
An unbalanced amount ('ss - Ill/k) is detected by l. On the other hand, since the fault current Ill is shunted to the other healthy power supply devices INV2 to INvn, these current detection circuits UCD2 to UCDn have (-
111/(fL-1)・kwa-A1. /(?L-1
)) unbalanced current will be detected. Therefore, the absolute value detection circuit ACD1 has (lr'1tl-'ozL
Absolute value detection circuit ACD, ~ person CDn (lrLsx/
(?L-1)l-'am/(TLl)) are output, and the voltage of the average value of these outputs (Voz
・2/(%-t)) is given between the busbars BB r 84 and becomes Ruco. From this, the output resistance is 11 (
total-2/(''-1))>O)+R2~Rn has ('ox(-1/(?L-t))<0) null IE pressure detected tL, tVJ, that is, failure occurrence A positive polarity detection voltage can only be obtained from the power supply INVl, and the current detector 0CD1 only needs to determine its polarity and determine a failure when it exceeds a predetermined value, so it is fast and reliable. 1ζ
This makes it possible to detect failures.

9. Such an embodiment is equipped with a means for detecting the absolute value of the unbalanced current of each power supply device operated in parallel, and also obtains the difference between the output of each absolute value detection means and the average value of these outputs. This is an example of an inverter device parallel operation system that has the requirements of the present invention, and it is easy to use this embodiment as an addition to the conventional fault detection method that performs logical operations as described above. Although this embodiment shows a specific example to facilitate understanding of the present invention, the present invention does not have the configuration shown in FIG. It is clear that this applies even if

As described above, according to the present invention, it is possible to provide an exceptional method that can realize a device with a simple configuration that can quickly and reliably detect a wide range of failures in power supply devices in a parallel operation system.

[Brief explanation of the drawing]

FIG. 1 is a main control system diagram showing a specific example of the present invention. INV, -INVn...Power supply device, W...
...Load, UCDI~IG UCDn...Current detection circuit, person CD1~person cD
n...Song absolute value detection circuit SR1~Rn...Surface resistance,
0CD1~ocDn...Current detector. Patent applicant Toyo Denki Seizo Co., Ltd. Representative Atsushi Doi

Claims (1)

[Claims] A parallel operation system in which a plurality of power supply devices are commonly connected to a load to supply power, comprising an absolute value detection means for detecting the absolute value of each unbalanced current of the plurality of power supply devices, the absolute value of the balanced current for each year. and these output average values are compared, and when the difference has a specific polarity and exceeds a predetermined value, the power supply is determined to be in failure. Discrimination method.