JPS5895671U - Two-tier stacked electronic circuit package - Google Patents
Two-tier stacked electronic circuit packageInfo
- Publication number
- JPS5895671U JPS5895671U JP1981192103U JP19210381U JPS5895671U JP S5895671 U JPS5895671 U JP S5895671U JP 1981192103 U JP1981192103 U JP 1981192103U JP 19210381 U JP19210381 U JP 19210381U JP S5895671 U JPS5895671 U JP S5895671U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- package
- circuit board
- packages
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の電子回路パッケージの斜視図、第２図は
その両プリント基板結合要領を示す正面図、第３図乃至
第５図は本考案に係る２段重ね電子回路パッケージの実
施例を示すもので、第３図はその組立状態を示す斜視図
、第４図は両型子回路パッケージ展開状態を示す斜視図
、第５図は面電子回路パッケージ結合要領を示す正面図
である。
図中、１１は２段重ね電子回路パッケージ、１２．１３
は電子回路パッケージ、１４．１８は電子部品、１５．
１９は接栓部（接続部）、１６゜２０はプリント基板、
１７．２１はコネクタ（接続部）、２２Ａ、２２Ｂ、２
２Ｃは帯状接続部材、２３はスペーサ、２４はねじであ
る。
第１図
第２図Fig. 1 is a perspective view of a conventional electronic circuit package, Fig. 2 is a front view showing how to connect both printed circuit boards, and Figs. 3 to 5 show an embodiment of a two-tiered electronic circuit package according to the present invention. FIG. 3 is a perspective view showing the assembled state, FIG. 4 is a perspective view showing the double-mold circuit package in an expanded state, and FIG. 5 is a front view showing how to connect the surface electronic circuit package. In the figure, 11 is a two-tiered electronic circuit package, 12.13
14.18 is an electronic component; 15. is an electronic circuit package; 14.18 is an electronic component;
19 is the plug part (connection part), 16°20 is the printed circuit board,
17.21 is the connector (connection part), 22A, 22B, 2
2C is a strip-shaped connecting member, 23 is a spacer, and 24 is a screw. Figure 1 Figure 2
Claims (1)
し他端に外部ケーブルと接続するための第２の接続部を
有するプリント基板に複数個の電子部品を搭載してなる
２枚の電子回路パッケージを、一方のパッケージのプリ
ント基板の部品面と他方のパッケージのプリント基板の
半田面とを所定の距離を介し対向させてパッケージ実装
用シェルフのレールに容易に適合するようにルーズな状
態で結合し、前記両プリント基板の対向面間を、該各プ
リント基板の同一側の側端から順次内側に入った位置で
それぞれ複数枚の可撓性を有する帯状接続部材により接
続して構成され、前記各接続部材の長さは、前記両型子
回路パッケージ結合時に該両パッケージ間で重なって折
れ曲りかつ該両パッケージ展開時に展開が容易に行われ
るように設定されたことを特徴とする２段重ね電子回路
パッケージ。Two pieces of printed circuit board with multiple electronic components mounted on a printed circuit board that has a first connection part for connecting to the backboard at one end and a second connection part for connecting to an external cable at the other end. The electronic circuit package is placed in a loose state so that the component side of the printed circuit board of one package and the solder side of the printed circuit board of the other package face each other at a predetermined distance so that it can easily fit onto the rails of the package mounting shelf. and the opposing surfaces of both printed circuit boards are connected by a plurality of flexible strip-shaped connecting members at positions successively inward from the same side edge of each printed circuit board. 2. The length of each of the connecting members is set so that the two packages are overlapped and bent when the two mold child circuit packages are coupled, and the two packages are easily unfolded when the two packages are unfolded. Stacked electronic circuit package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981192103U JPS5895671U (en) | 1981-12-22 | 1981-12-22 | Two-tier stacked electronic circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981192103U JPS5895671U (en) | 1981-12-22 | 1981-12-22 | Two-tier stacked electronic circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5895671U true JPS5895671U (en) | 1983-06-29 |
Family
ID=30105529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981192103U Pending JPS5895671U (en) | 1981-12-22 | 1981-12-22 | Two-tier stacked electronic circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895671U (en) |
-
1981
- 1981-12-22 JP JP1981192103U patent/JPS5895671U/en active Pending
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