JPS589566B2 - Atsuyoku Atsouchi - Google Patents

Atsuyoku Atsouchi

Info

Publication number
JPS589566B2
JPS589566B2 JP8014675A JP8014675A JPS589566B2 JP S589566 B2 JPS589566 B2 JP S589566B2 JP 8014675 A JP8014675 A JP 8014675A JP 8014675 A JP8014675 A JP 8014675A JP S589566 B2 JPS589566 B2 JP S589566B2
Authority
JP
Japan
Prior art keywords
varistor
disk
electrodes
terminal
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8014675A
Other languages
Japanese (ja)
Other versions
JPS5124742A (en
Inventor
フランソワ・デイデイア・マーツズロフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of JPS5124742A publication Critical patent/JPS5124742A/en
Publication of JPS589566B2 publication Critical patent/JPS589566B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/102Varistor boundary, e.g. surface layers

Description

【発明の詳細な説明】 この発明はバリスタ型電圧サージ保護装置に関する。[Detailed description of the invention] The present invention relates to a varistor type voltage surge protection device.

更に具体的に云えば、この発明は多相電気回路で過渡電
圧tこ対する保護を行なう多重端子の多結晶バリスク装
置に関する。
More specifically, the present invention relates to a multi-terminal polycrystalline varisque device for providing protection against transient voltages in multiphase electrical circuits.

この発明は1972年9月19Blこ付与された米国特
許第3693053号1こ記載される発明に関係を有す
る。
This invention is related to the invention described in US Pat. No. 3,693,053, issued September 19, 1972.

現在製造される基本的な多結晶バリスタ装置は、酸化亜
鉛を主成分とし、他の金属酸化物並びにハロゲン化物か
ら成る群から選ばれた多数の少量成分を含む焼結セラミ
ック円板で構成される。
The basic polycrystalline varistor device currently manufactured consists of a sintered ceramic disk containing zinc oxide as the main component and a number of minor components selected from the group consisting of other metal oxides as well as halides. .

焼結円板の向い合う主面の各々に電極が適用さね、各々
の電極に導線を取付けて2端子バリスタ装置とする。
Electrodes are applied to each of the opposing main surfaces of the sintered disk, and a conductive wire is attached to each electrode to form a two-terminal varistor device.

この装置をプラスチック材料にカプセル封じするのが普
通である。
It is common to encapsulate this device in a plastic material.

前掲米国特許には、多結晶バリスク材科の焼結した本体
に複数個の突起を設け、各々の突起の主面に電極を適用
した形の多重端子金属酸化物バリスク多相過渡電圧抑圧
装置に記載されている。
The aforementioned U.S. patent describes a multi-terminal metal oxide varisk multiphase transient voltage suppression device in which a plurality of protrusions are provided on a sintered body made of polycrystalline balisk material, and an electrode is applied to the main surface of each protrusion. Are listed.

この発明の特徴は、多相電気回路で電圧サージを抑圧す
る多重端子多結晶バリスタ装置として、現在、2端子形
バリスタ装置の製造に用いられている生産装置を用いて
低廉1こ且つ効率よく製造することが出来るように、略
円板形にしたバリスタ装置を提供することである。
A feature of this invention is that it can be manufactured inexpensively and efficiently using production equipment currently used for manufacturing two-terminal varistor devices as a multi-terminal polycrystalline varistor device that suppresses voltage surges in a multi-phase electric circuit. It is an object of the present invention to provide a varistor device having a substantially disk shape so that it is possible to do so.

この発明の別の目的は、それから出て来る全ての電気導
線が同一平面内Eこ取付けらねていること{こより、電
気装置に容易1こ且つ能率的に取付けられるこの種の多
重端子バリスタ装置を提供することである。
Another object of the invention is that all the electrical conductors coming out of it are mounted in the same plane (this makes this type of multi-terminal varistor device easy and efficient to install in electrical equipment). The goal is to provide the following.

この発明の別の目的は、簡単でまとまりのよい形である
為、電気装置]こ容易に且つ能率的に取付けられ、然も
望ましくない電気的な接触を防ぐようにカプセル封じし
たこの種の多重端子バリスタ装置を提供することである
Another object of the invention is that it is of simple and compact form so that electrical equipment can be easily and efficiently installed, yet encapsulated to prevent unwanted electrical contact. An object of the present invention is to provide a terminal varistor device.

簡単に云うと、この発明の1実施例では、1対の向い合
う主面を持つ多結晶バリスク材料の円板の一力の主面に
複数個の溝を設け、溝の間に複数個のランドを限定する
Briefly, in one embodiment of the present invention, a disk of polycrystalline balrisk material having a pair of opposing major surfaces is provided with a plurality of grooves on one major surface, and a plurality of grooves between the grooves. Limited land.

複数個の電極をランド上に配置し、それを電気回路に接
続する導線を設ける。
A plurality of electrodes are placed on the land, and a conductive wire is provided to connect the electrodes to an electric circuit.

円板の反対側の面、即ち溝を設けてない面に電極を設け
、装置のバリスク電圧をこえる電圧が装置の任意の2本
の導線に接続された線路の間に現われる時、この電極が
電流を通すように作用する.この発明の新規な特徴は、
特許請求の範囲に具体的に記載してあるが、この発明並
びにその他の目的及び利点は、以下の説明から更によく
理解されよう。
An electrode is provided on the opposite side of the disk, i.e. on the non-grooved side, so that when a voltage exceeding the balisk voltage of the device appears between the lines connected to any two conductors of the device, this electrode It acts to conduct current. The novel features of this invention are:
While particularly pointed out in the claims, the invention, as well as other objects and advantages, will be better understood from the following description.

第1図はこの発明の1実施例1こよる4端子形バリスタ
装置の平面図で、多結晶バリスク材科の円板10で構成
される。
FIG. 1 is a plan view of a four-terminal varistor device according to a first embodiment of the present invention, which is composed of a disc 10 made of polycrystalline varistor material.

円板10の面からその厚さの一部分tこわたり溝11.
12が伸びている。
From the surface of the disk 10, a portion of its thickness t is broken into a groove 11.
12 is growing.

溝11.12は完成された焼結円板に対する切削作業に
よって形成してもよいし、成いは円板10のプレス作業
に、十字形の突起を持つラムを用いて形成してもよい。
The grooves 11, 12 may be formed by cutting the finished sintered disk, or they may be formed by pressing the disk 10 using a ram with a cross-shaped projection.

形が簡単な場合、多結晶バリスタのバリスタとしての特
性の一様性がすぐれているから、大形の大電力装置の場
合には切削作業の刀が好ましい。
When the shape is simple, the polycrystalline varistor has excellent uniformity of characteristics as a varistor, so a cutting knife is preferable for large-sized, high-power devices.

小形装置の場合、円板に溝11及び12をプレス作業で
形成するのが、大量生産の点で経済的1こ好ましい。
In the case of a small device, it is economical and preferable to form the grooves 11 and 12 in the disk by pressing, from the point of view of mass production.

小形で低電力の装置の場合でも、少量しか生産しない時
、切削作業によって溝11.12を形成するのが経済的
に有利であることがある。
Even in the case of small, low-power devices, it may be economically advantageous to form the grooves 11, 12 by cutting operations when only small quantities are produced.

この場合、2端子形バリスク装置を製造する生産作業で
プレスされた円板の一部分を取出し、それに溝をつけて
比較的少量の多重端子形装置にすることか出来る。
In this case, a portion of the disk pressed in a production operation for making two-terminal balisk devices can be taken and grooved to form relatively small quantities of multi-terminal devices.

溝11.12の間にランド13,14,15,16が形
成される。
Lands 13, 14, 15, 16 are formed between the grooves 11.12.

ランド13,14,15.16には夫々電極17,18
,19,20が適用される。
Electrodes 17, 18 are provided on lands 13, 14, 15, and 16, respectively.
, 19, 20 apply.

この電極は、例えば、塗装、めっき、スパッタリング又
は印刷により、ランドの上面に導電材料を適用すること
によって設けることが出来る。
This electrode can be provided by applying a conductive material to the top surface of the land, for example by painting, plating, sputtering or printing.

各々の電極に夫々導線21 ,22,23.24をつけ
る。
Conductive wires 21, 22, 23, and 24 are attached to each electrode, respectively.

これははんだ付けで取付けるのが有利である。溝11.
12がバリスタの円板10の面Eにわたり、電極17,
18,19,20を電気的に隔離する。
This is advantageously mounted by soldering. Groove 11.
12 extends over the surface E of the disc 10 of the varistor, and the electrodes 17,
18, 19, and 20 are electrically isolated.

正常の定常状態の動作状態では、バリスタ材科の抵抗値
が数千メグオーム程度に極めて高く、電極の間で円板1
0には殆んど全く電流が流れない。
Under normal steady-state operating conditions, the resistance of the varistor material is extremely high, on the order of several thousand megohms, and the disc 1 between the electrodes is
At zero, almost no current flows.

然し、過渡状態によってこのバリスタ電圧をこえると、
バリスタ材料か1オーム未満と云う程度のごく小さい抵
抗値を持ち、過渡状態のエネルギーがバリスタ材科を介
して分略され、これを接続した回路を保護する。
However, if this varistor voltage is exceeded due to a transient condition,
The varistor material has a very small resistance of less than 1 ohm, and transient energy is split through the varistor material, protecting the circuitry to which it is connected.

装置のバリスタ電圧は、バリスタ材科の組成並びに電極
間の距離の関数である。
The varistor voltage of the device is a function of the composition of the varistor material as well as the distance between the electrodes.

溝11.12は、バリスタ電流が電極の間の表面ではな
く、円板10のバルク内を通るように保証する作用があ
る。
The grooves 11.12 serve to ensure that the varistor current passes within the bulk of the disk 10 and not through the surface between the electrodes.

第2図は第1図の多重端子多結晶バリスタの側面図で、
円板10、溝11をはさむランド15及び16、並びに
その上に設けられた電極19,20を第1図と同じよう
に示している。
Figure 2 is a side view of the multi-terminal polycrystalline varistor shown in Figure 1.
The disk 10, the lands 15 and 16 sandwiching the groove 11, and the electrodes 19 and 20 provided thereon are shown in the same manner as in FIG.

更に第2図は、円板10の反対側、即ち溝を設けない面
に配置された電極25を示すと共に、電極19,20の
間の表面導電通路を防止する溝11の作用を例示してい
る。
FIG. 2 further shows the electrode 25 disposed on the opposite side of the disk 10, ie, on the non-grooved side, and illustrates the effect of the groove 11 in preventing surface conductive paths between the electrodes 19, 20. There is.

バリスタのバリスタ電圧は電極の間の距離の関数であり
、バリスタ電圧が一層低いバリスタと並列になっている
バリスタには、電流が流れないから、溝11の寸法は、
電極19,20の間の表面導通通路が、バリスタのバル
クを通る導電通路より一層長く、その為バリスタ電圧が
一層高くなるように選ばれる。
Since the varistor voltage of a varistor is a function of the distance between the electrodes, and no current flows through a varistor in parallel with a varistor with a lower varistor voltage, the dimensions of the groove 11 are:
The surface conduction path between electrodes 19, 20 is chosen to be longer than the conduction path through the bulk of the varistor, so that the varistor voltage is higher.

例えば、3相4線式電気回路に使うこの発明のバリスタ
装置では、面11a,1lb及び11cの長さの合計は
、円板10の厚さの2.3倍に等しいか又はそれより大
きくなるように選ばれる。
For example, in the varistor device of the present invention used in a three-phase four-wire electric circuit, the sum of the lengths of surfaces 11a, 1lb and 11c is equal to or greater than 2.3 times the thickness of disk 10. are selected as such.

この為、装置のバリスタ電圧をこえる電圧スパイクが電
極19.20の間に発生した時、電極19から円板10
の厚さを通って電極25に達し、それれら再び円板10
の厚さを通って電極20に至る導電通路が、装置の表面
を横切る電極19.20の間の導電通路よりも優先して
出来上がる。
For this reason, when a voltage spike exceeding the varistor voltage of the device occurs between electrodes 19 and 20,
through the thickness of the disk 10 to reach the electrodes 25, which are again connected to the disk 10.
The conductive path through the thickness to the electrode 20 is created in preference to the conductive path between the electrodes 19, 20 across the surface of the device.

第2図は、この発明の多重端子形多結晶バリスタ装置が
プラスチック材科26にカプセル封じさ・れることを断
面図で示している。
FIG. 2 shows in cross-section the multiterminal polycrystalline varistor device of the present invention encapsulated in a plastic material 26.

電気導線21乃至24がカプセル封じ材料26を通抜け
、保護しようとする電気回路に接続出来るようになって
いる。
Electrical leads 21-24 are threaded through the encapsulating material 26 so that they can be connected to the electrical circuit to be protected.

カプセル封じ材料26は、この発明の装置に対し普通の
機械的な保護作用を持つと共に、誤って電極25に電気
的な接触が生じることがないようにする。
Encapsulation material 26 provides the usual mechanical protection for the device of the invention and prevents accidental electrical contact from being made to electrode 25.

この為、カプセル封じ材料26を使うと、電極25に電
気的な接触が起らないように注意しなくても、この発明
の多重端子形多結晶バリスタ装置を電気装置に取付ける
ことが出来るので、;取付けが簡単になる。
Therefore, by using the encapsulating material 26, the multi-terminal polycrystalline varistor device of the present invention can be installed in an electrical device without having to take care to avoid electrical contact with the electrodes 25. ;Easy installation.

この発明の多重端子形多結晶バリスタ装置をこ於ける電
極25の作用は、円板の厚さの2倍として足められる装
置のバリスタ電圧を設定すること、並び1こバリスクの
導電通路が電極17,18,19,20の区域によって
限定されたバルク通路であることを保証することである
The function of the electrodes 25 in the multi-terminal polycrystalline varistor device of this invention is to set the varistor voltage of the device, which is taken as twice the thickness of the disk, and to ensure that the conductive path of the varistor is connected to the electrodes. 17, 18, 19, 20 to ensure that the bulk passage is defined by the areas 17, 18, 19, 20.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の1実施例による多重端子形多結晶バ
リスタ装置の平面図、第2図は第1図の多重端子形多結
晶バリスタ装置の側面図で、カプセル封じ材料を断面で
示してある。 主な符号の説明、10:バリスタ材料の円板、11,1
2:溝、13,14,15.16:ランド、17,18
,19,20:電極、21,22,23.24:導線、
25:第2面の電極。
FIG. 1 is a plan view of a multi-terminal polycrystalline varistor device according to an embodiment of the present invention, and FIG. 2 is a side view of the multi-terminal polycrystalline varistor device of FIG. 1, showing the encapsulating material in cross section. be. Explanation of main symbols, 10: Varistor material disc, 11, 1
2: Groove, 13, 14, 15. 16: Land, 17, 18
, 19, 20: electrode, 21, 22, 23. 24: conducting wire,
25: Electrode on the second surface.

Claims (1)

【特許請求の範囲】[Claims] 1 1対の向い合う面を持つ多結晶バリスタ材料の円板
と、該円板の第1の面から円板の厚さの一部分にわたっ
て伸びている複数個の溝と、該溝の間で前記第1の面上
に配置された複数個の電極と複数個の電極回路に接続す
る手段と、第2の面に配置された電極とを有する多相過
渡電圧抑圧装置2 特許請求の範囲1に記載した多相過
渡電圧抑圧装置に於で、各々の溝が前記第1の面に2つ
の縁を持つと共に該縁の間に少さくとも1つの面を持ち
、前記面に沿った縁の間の最短距離が円板の厚さより大
きい多相過渡電圧抑圧装置。
1 a disk of polycrystalline varistor material having a pair of opposing surfaces, a plurality of grooves extending from a first side of the disk over a portion of the thickness of the disk; A multiphase transient voltage suppression device 2 comprising a plurality of electrodes arranged on a first surface, means for connecting to a plurality of electrode circuits, and an electrode arranged on a second surface. In the described multiphase transient voltage suppression device, each groove has two edges on said first surface and at least one surface between said edges, and said groove has at least one surface between said edges; A multiphase transient voltage suppression device whose shortest distance is greater than the thickness of the disk.
JP8014675A 1974-07-01 1975-06-30 Atsuyoku Atsouchi Expired JPS589566B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US48492374A 1974-07-01 1974-07-01

Publications (2)

Publication Number Publication Date
JPS5124742A JPS5124742A (en) 1976-02-28
JPS589566B2 true JPS589566B2 (en) 1983-02-22

Family

ID=23926201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8014675A Expired JPS589566B2 (en) 1974-07-01 1975-06-30 Atsuyoku Atsouchi

Country Status (4)

Country Link
JP (1) JPS589566B2 (en)
DE (1) DE2528090C2 (en)
GB (1) GB1508327A (en)
NL (1) NL182598C (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485452U (en) * 1977-11-29 1979-06-16
US4212045A (en) * 1978-12-22 1980-07-08 General Electric Company Multi-terminal varistor configuration
GB2044531B (en) 1979-02-09 1983-05-25 Tdk Electronics Co Ltd Non-linear resistance elements and method for manufacturing same
US4371860A (en) * 1979-06-18 1983-02-01 General Electric Company Solderable varistor
FR2475791A1 (en) * 1980-02-12 1981-08-14 Thomson Csf NON-LINEAR CERAMIC RESISTANCE WITH LOW THRESHOLD VOLTAGE AND METHOD OF MANUFACTURING THE SAME
DE3140802A1 (en) * 1981-10-14 1983-05-26 AEG-Telefunken Nachrichtentechnik GmbH, 7150 Backnang Multi-electrode varistor
GB8418779D0 (en) * 1984-07-24 1984-08-30 Bowthorpe Emp Ltd Electrical surge protection
US4785276A (en) * 1986-09-26 1988-11-15 General Electric Company Voltage multiplier varistor
SE527949C2 (en) 2004-12-22 2006-07-18 Abb Research Ltd Method of producing a varistor
EP1946336A1 (en) * 2005-10-19 2008-07-23 Littelfuse Ireland Development Company Limited A varistor and production method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2501322A (en) * 1946-11-07 1950-03-21 Westinghouse Electric Corp Moisture-resistant lightning arrester valve block
BE572049A (en) * 1957-12-03 1900-01-01
US2935712A (en) * 1958-02-04 1960-05-03 Victory Engineering Corp Multi-terminal non-linear resistors
US2989713A (en) * 1959-05-11 1961-06-20 Bell Telephone Labor Inc Semiconductor resistance element
US3195091A (en) * 1963-05-13 1965-07-13 Automatic Elect Lab Non-linear resistance devices
US3768058A (en) * 1971-07-22 1973-10-23 Gen Electric Metal oxide varistor with laterally spaced electrodes
US3742419A (en) * 1971-09-30 1973-06-26 Gen Electric Integral sensor for monitoring a metal oxide varistor
US3693053A (en) * 1971-10-29 1972-09-19 Gen Electric Metal oxide varistor polyphase transient voltage suppression

Also Published As

Publication number Publication date
NL182598B (en) 1987-11-02
DE2528090C2 (en) 1985-06-05
GB1508327A (en) 1978-04-19
NL182598C (en) 1988-04-05
NL7507645A (en) 1976-01-05
JPS5124742A (en) 1976-02-28
DE2528090A1 (en) 1976-01-22

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