JPS5895477A - Transmission method for picture data - Google Patents

Abstract

PURPOSE:To obtain good interpolated samples, by devising the shuffling method so that errors occur hardly in samples around an erroneous sample even if a relatively large burst error occurs. CONSTITUTION:The television signal from an input terminal 1 is supplied to an encoder 3 through an A/D converter 2. Each data from the encoder 3 is supplied to a converter 4, and data obtained from the converter 4 is inputted to a shuffler 5. In this shuffler 5, preshuffling and main shuffling for every one line are performed. Data is shuffled with a certain regularity by this shuffling. Shuffled data is supplied to a VTR 7 through a PS converter 6. Data from the VTR 7 is restored to the original television signal through the reverse operation.

Description

DETAILED DESCRIPTION OF THE INVENTION A digital VTR is known that converts a television signal into a digital signal, records it on a magnetic tape, and reproduces it. In the case of this digital VTR, bit errors that can be corrected are corrected using parity, etc., but data that cannot be corrected is corrected by using surrounding samples, noting that television signals have a strong correlation. An interpolated sample is created using the interpolated sample, and corrections are made using the interpolated sample.

For example, as shown in Figure 1, three horizontal lines '1m'
Since the sample bn on the center line 12 of 2m'3 is incorrect, when correcting this, in view of the horizontal correlation of the Eirin signal, the sample bH-1 adjacent to the sample bn on the center line i2 should be corrected. *bn+1 is used, and in consideration of the vertical correlation of the video signal, samples bnK and spatially adjacent samples in and Cn on lines l1 and 1s adjacent to this central line l2 are used to obtain an interpolated sample bn as follows. is prepared, and this sample bn1 is replaced with sample bn.

By the way, in general, errors that occur in a transmission system when transmitting a digital signal include random errors and burst errors. As the name suggests, the former is an error that occurs at discrete points in time, and the latter is an error that occurs continuously over time.

If the error is a random error, a good interpolated sample bn will be obtained because the samples around the sample bn where the above error has occurred are not erroneous, but if a burst error occurs, in the above example , the samples around the sample bn where the error has occurred also become erroneous, making it impossible to use these samples for interpolation, making it virtually impossible to correct the error.

Particularly in the case of digital VTRs, the latter of the above two errors, the burst error, often occurs due to dust or scratches adhering to the magnetic tape. For this reason, digital VT
In R, image data is not recorded directly in chronological order, but is recorded in advance through a process called shuffling, which causes the information to be recorded on the tape to vary over time. In this way, even if a burst error occurs in the reproduced signal,
By performing deshutting to return the data to the original time series in the reproduction system, it is possible to make it appear as if a burst error has been converted into a random error. Therefore, in this case, since the samples surrounding the erroneous sample are hardly erroneous, it is possible to perform error correction by using the surrounding samples to obtain interpolated samples.

By the way, there are various shuffling methods mentioned above, but in a shuffling method that causes data to vary completely randomly, when the burst error becomes relatively large, it is difficult to use the shuffling method that is used to create interpolated samples in error correction. Some of the samples surrounding the sample may contain errors. This error may be a burst error in another part, or, oh yes, it may also be a burst error.

When the number is 5, good interpolation samples cannot be obtained, and the effect of error correction is substantially reduced.

In view of the above points, this invention devises a shuffling method so that even if a relatively large burst error occurs, the samples surrounding the erroneous sample are samples with almost no errors. be.

In other words, in this invention, shuffling does not cause data to vary completely randomly, but rather is a busy turtle that causes data to vary with a certain regularity.

In this invention, shuffling consists of pre-shuffling and main shuffling, and the data that has been pre-shuffled is subjected to main shuffling.

Main shuffling is based on considering the allowable burst error size, and when a burst error occurs within this size, if the burst error is returned to the original time series by deshuffling, the burst error will be resolved as shown in Figure 2. This is a shuffling method that causes samples with errors to line up vertically on the playback screen. In this case, for the purpose of shuffling, it goes without saying that the horizontal sample string is set to 5 so that samples with errors are not consecutive.

In FIG. 2, Ll, 112, L3, L4, La... indicate horizontal lines, and the circles and crosses indicate samples.The circles and circles indicate samples without errors,
Samples with errors are marked.

Preshifting is a process that cyclically shifts the sample string of data by several samples every ym (#) horizontal line. For example, for odd lines, the sample string is left as is, and for even lines, the sample string is shifted, for example, to the left or right. Cyclically shifted by Kk samples in either direction.

For example, by pre-shuffling, the sample rows of every other line L2, L4, Ll, etc. are shifted by 4 samples to the right, and the remaining every other line Lw,
The sample strings La, Ls, . . . are t in the original state.

When reproducing data that has undergone pre-shuffling and main shuffling as described above, if only deshutting is performed on the main shuffling first, samples with errors caused by the 51C burst error as shown in FIG. 1i! However, in this state, every other line L! , L4, Ll, etc. are not in their original state. Therefore, if we further perform deshutting on the pre-shutfling, that is, if we shift them to the left by 4 samples and return them to the original sample rows, they will appear on the playback screen. Then, as shown in FIG. 3, the erroneous samples are not lined up in the vertical direction of the screen, and all the samples around the erroneous samples are samples without errors.

Therefore, in error correction, good interpolation samples are always obtained, and good error correction is possible.

Next, an example in which the method of the present invention is applied to a digital VTR will be explained with reference to the drawings.

Figure 4 is a system diagram of an example of a digital VTR.
1) The television signal through A-D converter 121K
Supplied. In this A-D converter (21), the effective video information of the television signal, i.e., the television signal excluding the vertical synchronization signal, horizontal synchronization signal and burst signal, is sampled at a sampling frequency of 4f, c ('SC is the color printing carrier frequency). For example, each sampling value is 8
The data is converted into bit PCM image data, and this is obtained in 8-bit parallel form from the A/D converter +21.

That is, each sample value is represented as an 8-bit word. This 8-bit parallel data word is then supplied to encoder (3)K.

In this encoder (3), a plurality of data words are converted into a pull signal, and a parity word and a check word for error correction are added to each block.

Each word from this encoder (3) is converted into a converter (4).
) K is supplied.

In this converter (4), an 8-bit data word is
Converted to a 0-bit word. In this case, out of all 10-bit words, or 1024 words, 5 "
A set of IO bitwords consisting of "0" and 5 rlJs is used for switching. This conversion process is performed because the DC component cannot be regenerated with a normal VT)l.

The lO bit word obtained from this converter (4) is subjected to pre-shuffling for each line and main shuffling for the pre-shuffled word in the shuffler (5) as described above.

Pre-shifting and main shifting will be explained in more detail.

In this case, the number of samples per horizontal line is, for example, 768 samples, taking into consideration the effective horizontal video area (excluding the horizontal blanking period), and the main shuffling is an i combination of 10 lines of data. I will explain about it.

Figure 7 is a system diagram of an example of Shuffler (5), (b)
is a pre-shuffle circuit, and (200) is a main shuffle circuit.

First, the preshuffle circuit (2) will be explained.

In the pre-shutful circuit (2), two RAMs (
IolA) (102A) and latch circuit (103A) (
104A) (10!5A) (106A), two FLAM (IOIB) (102B) and a latch circuit (103B) (104B) (105B) (1
06B). The purpose of providing these two systems is to ensure that when one system is in the write state, the other system is in the read state, since RAM cannot be written and read at the same time. Switching between reading and writing is performed every 1 horizontal 247 minutes.

Furthermore, the reason why two RAMs are provided is that the access time for writing and reading is extremely short in this example, and it is currently difficult to process with one RAM.

(107) is a latch circuit for the leads from the converter (4), and (108) is a latch circuit for returning the array of every two words to the array of every one word.

Also, (109) is a write address counter, (11
0) is a read address counter whose count value is incremented every l word. The write address data and read address data from these are sent to the *1 system AtnRAM (IOIA) (102A)K through gate circuits (112A) (113A), and to the second system B RAM through gate circuits (112B) (113B).
(IOIB) (102B)K are supplied respectively, but since the write address data is shifted in a sample cyclic manner every 247 horizontal minutes, it is sent to the gate ( B)
11 (112A) and H (112B) k supplied rel. A signal that inverts the state every horizontal line is supplied from the terminal (114) to the conversion circuit (nl), so that the write address data is changed every horizontal line.

In this case, the lower 1 bit of the count output of the counters (109) (110) is used as a select signal for the RAM 211, the upper 9 bits are used for addressing each RAM, and the upper 9 bits are used for the conversion circuit. (111) is converted as described above.

In addition, gate circuits (112A) (113A) are recommended (112
B) (113B) is controlled for each horizontal line by the write/read switching signal 8wRk from the terminal (US). That is, for example, 1 when the signal ~I is at a low level.
In the horizontal period, the gate circuit (112A) and the gate circuit (1j3B) are turned on, and l'tAM of the first system A
Write address data is supplied to (IOIA) (102A), and this system A is placed in the write state, while
The second system Bf) RAM (IOIB) (102B)K is supplied with read address data, and this system B is placed in a read state. Then, in the next horizontal period when the signal - becomes high level, the first system A is in the read state, and the second system B is in the read state.
is switched to write state.

In this case, preshuffling is performed as follows.

First, number the samples 1. 5 is the line number indicating which line out of 10 lines which is the unit of the main shuffle circuit, and J is the sample number indicating which sample among the lines, each sample is 81. 1 (1=0.1.2...9.j=0.1.
2...767), the pre-shuffle circuit converts j as follows.

In other words, when l-0, 2, 4, 6, and 8, the sample arrangement of each of these lines cannot be achieved at all.

Then, when l=1.3, 5, 7.9, that is, for each of these lines, the sample array is cyclically shifted k times to the right. In this case, the value of k is an integer of 1 or more, but the value is determined as appropriate by experiment or simulation.

For example, the case of =4 will be explained. Convert j to 1
To shift every horizontal line, k is concrete K)! R.O.
M (11m) K! -)te,)tAM(IOIA)(10
2A) or (IOIB) (102B) to control the address.

1=0°2,4.6. - For the sample of the 8th line, Teha, kttyfyyl (10
9) When the same book as the output is obtained and the two RAMs are considered as one RAM, each sample from the 0th to the 67th on each line above is the 1st
The data is written to the RAM of system A or the RAM of second system B from address O to address 767.

On the other hand, for the samples of i=1.3, 5, and 7.9th lines, 763
(for each sample up to the (767-4)th) tAM
(considering two RAMs as one) from address 4 to 76
The address data specifying address 7 is from the 794th to the 7th address.
For samples up to the 67th, address data specifying RAM addresses O to 3 is obtained, and the 5th
As shown in FIG. 5, samples for one line are cyclically shifted by four samples to the right and then written to the RAMK.

In addition, Fig. 5 M and B are each one line of image gI.
It shows the column of I samples, and the number shown in the frame shows the value of j.

In this way, the RA of system A of 111E1 or system B of vote 2
The 1247 minutes of samples written in the MK are sequentially read out from address 0 of each RAM in the next horizontal period. That is, %2 words are latched by the latch circuits (105A) (106) or (105B) (106B)K, and this is returned to a 1-element 1-word unit array by the latch circuit (108)K.

The image data pre-shuffled in this manner is supplied to the main shuffle circuit (2''00)K.

This main shuffle circuit (200) also has two memory systems, C and D, for the same reason as stated in the explanation for the pre-shuffle circuit (11). In the original, the number of RAM is 4, and these 4 ORAMs can handle 10 lines of 768 samples per line, that is, 7680 samples.
The sample is shuffled. In other words, the first system C
and the second system, read and write are differentially switched to each other every 10 lines.

Ill's system C has 4 RAMs (20IC) (202C
X203C) (204C and its input side latch circuit (
205C (208C) and its output side latch circuit (
209C) to (212C). The second system D similarly has four RAMs (2,0ID) to (204D),
It has latch circuits (205D) to (208D) and latch circuits (209D) to (21jD).

(213) is a latch circuit that latches the data word from the preshuffle circuit (2), and (214) is a latch circuit that returns the array of 4 words each to the original array of 1 word each.

Also, (215) is a write address counter, (21
6) is a read address counter. Counter (2)
15) Address conversion as described below for main shuffling is performed by the path (217)K, and this is transferred to the four RAAIs (2
01C) to (204C) are supplied to the four RAMs (2) of the second system through the gate circuit (218D).
01D) to (204D)k are supplied.

10,000, the read address data from the counter (216) is directly transmitted to the four RAMs (201C) to (204C)k of the first system C through the gate circuit (219C), and then to the second system D through the gate circuit (219D). RAM (20
1D) to (204D).

Each gate circuit (218C) (219C) and (2180
) (2190) is switched every 10 line periods by the switching signal from the terminal (220). When write address data is supplied to the RAM of one system, the RAM of the other system is switched. is supplied with read address data.

In this example, the write address is converted by the address crossing circuit (217) as follows.

First, serial numbers are assigned to 5 tel samples of 10 lines that have been preshuffled, and these are Sntted. In other words, n=0.1.2...7679, n=76
Convert as 8×i+j.

Next, the value h thus obtained is further subjected to the following conversion.

The above n is expressed in binary. This is the count output when samples for 10 lines are sequentially counted by the counter (215), and is Qo as 1, for example, 16 bits.

Scratch, Q2. ...Represented by Qlg.

The lower 2 bits QO and Ql of this count output are 4 R
This is the AM select signal.

The address data of each RAM is its upper 11 bits φ~Q
12 is used. Then, Address Intersection II (21
7), set the RAM address bits from AO to A1o.
Then, convert as follows.

When the write address data is converted as shown in
.

7680 data samples S0 to S7679 are written as shown in FIG. In other words, RAM (201C
) ~ (204C) - After sash pulls 8o ~ S3 are written to each address 0, RAM (2GIC) ~ (204C)
Samples 84 to S1 are written to each address 1024,
The next four samples 8s to 81t are placed at addresses 512K, the next samples 81z to aIS are placed at addresses 1536, and so on, and 7680 samples are regularly distributed and written into the four RAMKs.

Read from RAM (20IC) or (201D)
The processing is performed sequentially starting from address 00 of the primary KRAM (202C) or (202D), and so on.

In this case, the number of samples is 7680=4×15×1
28, but the memory capacity is 4X204g-819
2 and 81.992-4X16X12, no word is written in the part of the address that is a multiple of 160. Therefore, when reading, addresses that are multiples of 16 are skipped.

FIG. 8 shows successive samples when the above-described main shuffling is performed when k=0 for pre-shuffling, that is, for a group of samples that are not pre-shuffled. FIG. 8 is an example of 756 consecutive samples, where the last three digits indicate the sample number for each line, and the first digit indicates the line number.

From Figure 8, we can see that if all of the 756 samples mentioned above are erroneous due to a burst error such as a scratch on the tape (burst errors of this size are common), the erroneous samples can be played back and restored. If you change it back to , you can see that they are lined up vertically on the screen.

That is, the first sample (1oot) (2001) (3001) (40
01) is included in these 756 samples.

The data words shuffled as described above are supplied to the parallel-to-serial converter (6) to convert the data to the 10-bit VTR (7).
) K is supplied and recorded.

When playing back the VTR (7), the data is first converted back into 10-bit parallel data by the serial-parallel converter (8)k. Then, this 10-bit parallel data is subjected to an array conversion inverse to the main shuffling in the digital shuffler (9). After the sucsiple sequence is arranged in the order of I, an array conversion inverse to pre-shuffling is performed to restore the original sample array.

The resulting 10-bit parallel data word is applied to a converter trout which converts the 10-bit word back into an 8-bit word. The 8-bit parallel data word obtained from this converter αQ is supplied to a decoder and a collector, and error correction is performed using a parity word and a check word. An interpolated sample is formed by k, and error correction is performed by replacing the sample with the interpolated sample.

The error corrected and corrected data is fed to a D-to-me converter and converted into the original analog television signal.

As described above, in this invention, when a burst error occurs in the main shuffling, a method is intentionally adopted in which the samples in which the error occurs are arranged vertically on the playback screen. Previously, by performing preshuffling that cyclically shifts the button sample row by several samples for each horizontal line, it is possible to prevent incorrect samples from being lined up vertically on the playback screen even due to burst errors. It disappears. Therefore, in error correction, good interpolation samples can always be obtained using the samples of the preceding and succeeding lines using vertical correlation.

Furthermore, the configurations of the preshuffle circuit and the main shuffle circuit are simple. In particular, in the case of the above example, the address crossing circuit of the main shuffle circuit is characterized in that it is only necessary to wire the output lines of the counter and the address lines of the RAM to intersect with each other as described above.

Note that the present invention is not limited to the case where it is applied to the recording system of the digital VTR described above, but can also be applied to iii* by other transmission means.
Of course, this method can also be applied when data is transmitted.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining an example of a method for obtaining interpolated samples for error correction, Figures 2 and 3 are diagrams for explaining a shuffle method according to the present invention. A system diagram of an example when the method of the invention is applied to a digital VTR, FIG. 5 is a diagram for explaining an example of a pre-shuffle, FIG. 6 is a diagram for explaining an example of a main shuffle, and FIG. 117 is a diagram of a shuffle circuit. Diagram IN8, which is a system diagram showing an example of the configuration, is a diagram showing an example of a sample of the output after shuffle when only main shuffle is performed without performing preshuffle. Procedural amendment January 13, 1939 1, Indication of the case, Showa S/2008 Patent Application No. 18811-2, Name of the invention Image data transmission a2F method 3, Person making the amendment Address of the patent applicant related to the case No. 6-7-35, Kitashinyo, Tokyo Parts Ward Name (218
) Sony Corporation Representative Director Norio Ohga 6, Number of inventions increased by amendment (1) In the specification, 2] [1111Kr in 4th line "3 books"
Subscribe to the TV program "In the Apocalypse". (2) Same, 5] Line 110 [The main shuffling is -
Main shuffling in a new embodiment of the invention: For example, ]k correction. (3) Same, lI]i 4th and 5th line "Encoder (3)"
At the end of each, [parity generation circuit (3) Ic is corrected]. (4) Same page, lines 8 to 18 “Added...
[Added ``k'' to ``sh7r (4) k supplied. This shuffler (4) k: is corrected. (5) Same, 9th line, 9th line, "shaft-(5) J to r-shaft-(4)" k is corrected. Similarly, for the 9-line, 18-row fRAM, add ``In case of real-time shuffle data'' before ``.''. (7) Oka, 1G shoulder 7th line [word from converter (4)] to "word from parity generation circuit (3)" k
correct. Ibid., 13] 11th line ``Written.'' In the lab, ``In the example, the first system A and the second system B are each the second OR
AM (IOIA) (102A) and RAM (101B8
102B), and each RAM (IOIA) (10
2A) (IolB) (102B) are written from address O to address 383, respectively. ” to join. (9) Same, 18m, lines 113 to 15, ``Next k...the fist will be made.'' is corrected as follows. [fKKRAM (203C) Alui)t, (203D)
, (-#) Next 11c8 M (2020) or (20
2D), the last ICRAM (204C) or (204
D) IIK to do,” Ordo, 19 Shin lines 7 and 11,
In each of the 18 lines, ``Correct 756J by r2000JK.'' In the same line, insert the following sentence before the last line ``Parallel-serial converter''. "Converter (4) K is supplied. This converter (4)
) converts an 8-bit data word into a 10-bit word. In this case, all combinations of 10-bit words, i.e. 5 rOJ and 5 out of 1024
A 10-bit word of 1's is used for the conversion. The 10-bit word obtained from this converter (4) is then ``a'', 20 lines 5-6, ``and...
Correct ``...Shatsufura (9)'' to the following 5. “This parallel 10-bit data word is
1 and changed to the original 8-bit code, then the digital signal 7 is supplied to the digital signal 7 (IK). Then, this 8-bit parallel data is converted to the digital signal 7 (IK).
IQJ a3 Same, same Jio line ~ 13th line [Thus...and] is corrected to ``This data word is'' k. In the A4 drawing, Figure 4 is corrected as shown in the attached sheet. that's all

Claims (1)

[Claims] Pre-shuttle image data for each horizontal line,
This is a method of main shuffling and transmitting the preshuffled image data, and the preshuffling is a method of transmitting k sample sequences of image data every horizontal line.
(k is an integer greater than or equal to 1) This is a process of cyclically shifting samples. When a burst error occurs in the image data transmitted without pre-shuffling, the main shuffle is a process in which the sample with the error is A method of transmitting image data in which shuffling is arranged almost vertically on the playback screen.