JPS5895444A - Sn ratio improving circuit - Google Patents

Sn ratio improving circuit

Info

Publication number
JPS5895444A
JPS5895444A JP19408681A JP19408681A JPS5895444A JP S5895444 A JPS5895444 A JP S5895444A JP 19408681 A JP19408681 A JP 19408681A JP 19408681 A JP19408681 A JP 19408681A JP S5895444 A JPS5895444 A JP S5895444A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
mpx
stereo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19408681A
Other languages
Japanese (ja)
Other versions
JPS6313619B2 (en
Inventor
Kiyoshi Otani
清 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP19408681A priority Critical patent/JPS5895444A/en
Publication of JPS5895444A publication Critical patent/JPS5895444A/en
Publication of JPS6313619B2 publication Critical patent/JPS6313619B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/1646Circuits adapted for the reception of stereophonic signals

Abstract

PURPOSE:To improve the SN ratio of the output signal of a stereo multiplex (MPX) circuit, by controlling the MPX circuit in accordance with the level of a noise signal included in an FM demodulation signal. CONSTITUTION:The demodulation signal of an FM broadcast wave received through a front end 2, IF amplifier 3, and demodulating circuit 4 is separated to left and right signals by an MPX circuit 5, and these signals are applied to speakers 8 and 9 through an amplifier 67. The MPX circuit 5 is controlled by a subcarrier, which a PLL circuit 10 consisting of a phase comparator 11, a low pass filter 12, a voltage control oscillator 13, and frequency dividers 14 and 15 generates on a basis of a pilot signal obtained from a band pass filter 16, to perform the separating operation. Noise components of 15-23kHz appearing in the output of the phase comparator 11 are applied to the MPX circuit 5 through an amplifier 17, a rectifier 18, and a control signal generator 19 to control a stereo separation degree adjusting circuit and a high-band component attenuating circuit included in this circuit 5, thereby improving the SN ratio of the output signal.

Description

【発明の詳細な説明】 本発明は、a1々の妨害雑音、特に変調の浅い妨害倍9
による同一チャンネル妨害に対して、効果的に聴感上の
SR比を改轡し得る8H比改譬回路を提供せんとするも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to the interference noise of a1, especially the interference multiplier 9 with shallow modulation.
It is an object of the present invention to provide an 8H ratio modification circuit that can effectively modify the perceptual SR ratio in response to co-channel interference caused by the 8H ratio modification circuit.

従来、受信信号の電界強度を検出し、該電界強度に応じ
て、ステレオMPX(マルチプレックス)回路の分離度
を1整したり、I¥ilεステレオMPX回路の入力側
もしくは出力tillに得られる高域成分を減衰させた
りして、Sol比を改讐する方法が公知である。この方
法は、[界強度が低下した状態においては効果があるが
、電界強度に対応せず受信条件に応じて発生するマルチ
パス妨害、隣接チャンネル妨害、同一チャンネル妨害等
には全く効果のないものであった。
Conventionally, the electric field strength of a received signal is detected, and depending on the electric field strength, the degree of separation of a stereo MPX (multiplex) circuit is adjusted to 1, or the degree of separation obtained at the input side or output till of the stereo MPX circuit is adjusted. A method of modifying the Sol ratio by attenuating the frequency components is known. This method is effective when the field strength is reduced, but is completely ineffective against multipath interference, adjacent channel interference, co-channel interference, etc. that do not correspond to the field strength and occur depending on the reception conditions. Met.

また、従来、FM復調回路の出力信号中の高域(例えば
75ICHg以上)雑音成分を検出し、それに応じてス
テレオ分離度を1整したり、高域成分を減衰させたりす
る方法も公知である。この方法は、マルチパス妨害や、
隣接チャンネル妨害に対しても有効であるが、変調が浅
く周波&2変移の少い妨害信号に起因する同一チャンネ
ル妨害に対しては、効力が無かった。
Furthermore, there is also a conventionally known method of detecting high-frequency (for example, 75 ICHg or higher) noise components in the output signal of an FM demodulation circuit, and adjusting the degree of stereo separation to 1 or attenuating the high-frequency components accordingly. . This method prevents multipath interference and
Although it is effective against adjacent channel interference, it is not effective against co-channel interference caused by interference signals with shallow modulation and small frequency & 2 shift.

本発明は、上述の点に鑑み成されたもので、以下実施例
に基弓き図面を参照しながら説明する。
The present invention has been made in view of the above-mentioned points, and will be described in the following embodiments with reference to basic drawings.

第1図は、FM復調回路の出力信号中に含まれる同一チ
ャンネル妨害に起因して発生Tる雑汁のスペクトルを示
すものである。第1図の場合は、無変調の希望信号に対
して、 4QKBz程度の周波数変移を有する妨害信号
が混入したときの同一チャンネル妨害により生じる雑音
を示Tものである。第2図は1本発明の一実施例を示T
もので、(1)はアンテナ、(2)はFMフロントエン
ド、(3)は工r(中間周波ン増幅回路、(4)はFM
復調回路、(5)はステレオMPX回路、(6)は左信
号増幅回路、(7;は右信号増幅回路、(8)は左スピ
ーカ、及び(9)は右スピーカである。また、aaは1
位相比較器Uυ、低域通過フィルタ兼直流増幅器a3.
電圧制御発振器α3.第1分周器α4及び第2分周滞日
から成るステレオMP1回路(5)の為のデプキャ57
信号を発生するPLL回路、(leハ1rrJ記FM復
調回路]4)と約f P L L回lil!叫の位相比
較器Iとの間に挿入された19に翼2な中心筒波数とす
る帯域通過フィルタ、αDはfiO記PLLI回路−の
位相比較器αυの出力信号を増幅する帯域増幅器、aa
は該帯域増幅器110の出力信号を検流Tる整流回路及
びU]は該整流回路(18の出力信号に応じた直流側N
信号を発生する制御gi号発生卸路である。
FIG. 1 shows the spectrum of miscellaneous noise generated due to co-channel interference contained in the output signal of the FM demodulation circuit. The case of FIG. 1 shows the noise caused by co-channel interference when an interference signal having a frequency shift of about 4QKBz is mixed with an unmodulated desired signal. Figure 2 shows an embodiment of the present invention.
(1) is the antenna, (2) is the FM front end, (3) is the intermediate frequency amplifier circuit, and (4) is the FM front end.
demodulation circuit, (5) is a stereo MPX circuit, (6) is a left signal amplification circuit, (7; is a right signal amplification circuit, (8) is a left speaker, and (9) is a right speaker. Also, aa is 1
Phase comparator Uυ, low-pass filter/DC amplifier a3.
Voltage controlled oscillator α3. Digital filter 57 for the stereo MP1 circuit (5) consisting of the first frequency divider α4 and the second frequency divider
The PLL circuit that generates the signal (FM demodulation circuit 4) and about f PLL times lil! A band pass filter with a center cylinder wave number of 19 and 2 is inserted between the phase comparator I and αD is a band amplifier that amplifies the output signal of the phase comparator αυ of the PLLI circuit described in fiO, aa
is a rectifier circuit that galvanizes the output signal of the band amplifier 110, and U] is a rectifier circuit that galvanizes the output signal of the band amplifier 110;
This is a control gi generation output path that generates a signal.

アンテナillに受信された値引は、フロントエンド(
2)で工F信号に変換され、工F増幅回路(3)で増幅
された後、1Mui調回路(4)で復調される。そし’
CsFMuLm出力は、スFL/1M P X1gMf
5Jt’PLL回路薗のW11分周器α尋から得られる
33KHz夛グキャリア倍号の作用により左右のステレ
オ侶廿に分離され、左ステレオ@号は、左信号増幅回路
(6)で増幅され、右ステレオ信号は右信号増幅回路(
7)で増幅された後、それぞれ左右スピーカ(8)及び
(9)に印加される。
Discounts received on the antennaill are sent to the front end (
2), the signal is converted into an F signal, amplified by the F amplification circuit (3), and then demodulated by the 1Mui modulation circuit (4). stop'
CsFMuLm output is FL/1M P X1gMf
The left and right stereo signals are separated by the action of the 33KHz multiplication carrier multiplier obtained from the W11 frequency divider α-hiro of the 5Jt'PLL circuit, and the left stereo signal is amplified by the left signal amplification circuit (6). The right stereo signal is processed by the right signal amplification circuit (
After being amplified by step 7), the signal is applied to left and right speakers (8) and (9), respectively.

PLLb路■の位相比較器αυの第1入力端子には% 
rw復!i!!回路(4)の出力信号が帯域通過フィル
タ(leな介して印加される。また助記位相比較アOD
の第2入力端子には、電圧制御発振器αJの発振出力(
76Ki1m )’!−第1及び第2分周e、a舎及び
ctsテ分周して得られる19KF1sのgi号が印加
される。位相比較器αυの第1及び第2入力端子に前述
の如き入力信号が印加されると、その位相差にに5じた
信号が前記位相比較1uucD出力に生じる。この位相
差に応じた信号は、低域通過フィルタ兼直流m幅器13
で増幅された後、1!圧制却発振器[13に印加され、
該電圧制御発振器0の出力信号が正しく76■zとなシ
、第1分w4器cI4の出力がFM復調回路(4)の出
力信号と正しく同期する様に作用する。
The first input terminal of the phase comparator αυ of PLL b path ■ has %.
rw revenge! i! ! The output signal of the circuit (4) is applied through a bandpass filter (LE).
The second input terminal of is connected to the oscillation output (
76Ki1m)'! - The gi number of 19KF1s obtained by the first and second frequency divisions e, a and cts is applied. When the aforementioned input signals are applied to the first and second input terminals of the phase comparator αυ, a signal equal to the phase difference by 5 is generated at the output of the phase comparator 1uucD. A signal corresponding to this phase difference is transmitted to a low-pass filter/DC m-width filter 13.
After being amplified with 1! applied to the suppression oscillator [13,
The output signal of the voltage controlled oscillator 0 is correctly 76z, and the output of the first divider w4 cI4 is correctly synchronized with the output signal of the FM demodulation circuit (4).

この時、バンドパスフィルタrLBの出力に19に11
zステレオパイロツト信号とともに雑音が生じると。
At this time, the output of the bandpass filter rLB is 19 to 11.
zWhen noise occurs along with the stereo pilot signal.

前記ステレオパイロット信号の瞬時位相が雑音によシ変
化し、第2分周器1151からの19KHz侶づとの闇
に位相差な生じる。雑音が生じ、それによりて位相差が
生じると1位相比較器αυの出力には。
The instantaneous phase of the stereo pilot signal changes due to noise, resulting in a phase difference between the 19 KHz signal and the second frequency divider 1151. When noise occurs and a phase difference occurs, the output of the phase comparator αυ is:

位相波に応じた交流信号が発生する。この交流信号は、
帯域増幅器ll’bで増幅され、整流回路賭で整流され
る。従って整流回路αδの出力端子には、雑音の状態に
応じた直流出力が得られ、これがステレオmpxl路(
5)中に含まれるステレオ分離度調整回路や18+域成
分減衰回路を制御する制御信号発生回路(11に印加さ
れることによシ、ステレオMPX回’Jl、(5)にお
けるBH比の同上が達成される。
An alternating current signal is generated according to the phase wave. This AC signal is
It is amplified by the band amplifier ll'b and rectified by the rectifier circuit. Therefore, at the output terminal of the rectifier circuit αδ, a DC output corresponding to the noise state is obtained, and this is transmitted to the stereo mpxl path (
5) By being applied to the control signal generation circuit (11) that controls the stereo separation degree adjustment circuit and the 18+ range component attenuation circuit included therein, the BH ratio in (5) is achieved.

miJ記スデステレオ分離度回路は、例えば第6図に示
す如きものであり、左右ステレオ信号がそれぞれ得られ
る左倍号路(7)と右倍廿路c!vとの闇に。
The miJ stereo separation degree circuit is as shown in FIG. 6, for example, and has a left double path (7) and a right double path c! from which left and right stereo signals are obtained, respectively. In the darkness with v.

可変抵抗のを操入し、該可変抵抗@の値を前記制御信号
発生回路α9からの制卸信号に応じて動作する駆動回路
(ハ)で変化させるものである。このステレオ分離度調
整回路を使用することによシ、信号中の雑音が増大し、
整流回路賭の出力が大になうたとき、ステレオ分離度を
悪化させ、モノラルに近すけていき8W比を同上させる
ことか出来る。
A variable resistor is operated, and the value of the variable resistor @ is changed by a drive circuit (c) that operates in response to a control signal from the control signal generating circuit α9. By using this stereo separation degree adjustment circuit, the noise in the signal increases,
When the output of the rectifier circuit becomes large, it is possible to worsen the stereo separation, move it closer to monaural, and increase the 8W ratio.

その時、ステレオ分離度は、整流回路G8の出力レベル
に対応するので、8N比の改讐は、雑音量に対応して行
なわれる。
At this time, since the degree of stereo separation corresponds to the output level of the rectifier circuit G8, the modification of the 8N ratio is performed in accordance with the amount of noise.

前記高域成分減衰回路は、例えば第4図に示す如きもの
であり、左右ステレオ信号がそれぞれ得られる左右信号
路Q4及び(ハ)に、第1及び第2低域通過フィルタ弼
及び@を挿入し、該W!J1及び第2低域通過フィルタ
の及び□□□の高域信号の減衰量を制il!Il信号発
生回W!!σ9からの制御信号に応じて動作する駆動回
路奏で変化させるものである。高域信号の減衰量は、整
流回sueの出力信号に応じて。
The high-frequency component attenuation circuit is, for example, as shown in FIG. 4, and first and second low-pass filters \ and @ are inserted into the left and right signal paths Q4 and (c) from which left and right stereo signals are obtained, respectively. Yes, that W! Control the amount of attenuation of high-frequency signals of J1 and the second low-pass filter and □□□! Il signal generation times W! ! The performance is changed by a drive circuit that operates in response to a control signal from σ9. The amount of attenuation of the high frequency signal depends on the output signal of the rectifier circuit.

すなわち、信号中の雑音量に応じて変化させることが出
来、8H比の改醤が雑音量に応じて連続的に達成出来る
That is, it can be changed according to the amount of noise in the signal, and the 8H ratio can be changed continuously according to the amount of noise.

第5図は、本発明の別の実施例な示すものである。第5
図においては、第2図の如く位相比較器1υの出力信号
を増幅し、整流するのではなく、第2分5419から得
られる19111m信号をパルスカウント検波すること
によシ、雑音を検出し、それを整流して制御信号を発生
する点に特徴を何する。
FIG. 5 shows another embodiment of the invention. Fifth
In the figure, instead of amplifying and rectifying the output signal of the phase comparator 1υ as shown in Figure 2, the noise is detected by pulse count detection of the 19111m signal obtained from the second minute 5419. What makes it special is that it rectifies it and generates a control signal.

尚、第5図において、第2図と同一の[2J路ブロツク
には同一の図番な付し、説明を省略Tる。
In FIG. 5, the same figure number is not given to the [2J road block that is the same as in FIG. 2, and the explanation is omitted.

第2分周器αSの出力に得られる19区1g信号は。The 19-section 1g signal obtained at the output of the second frequency divider αS is as follows.

帯域通過フィルタ161&介して位相比較器Iの第1入
力端子に印加される入力信号が雑音により位相変mt受
ける為に、雑音の発生時に厳密には191Hzから正負
にわずか異る周波数を有している。
Since the input signal applied to the first input terminal of the phase comparator I via the bandpass filter 161 undergoes a phase change mt due to noise, strictly speaking, it has a frequency slightly different from 191 Hz in positive and negative directions when noise occurs. There is.

その為、第2分周器+151の出力口すを、単安定マル
チバイブレータ(支)と積分回路(至)とから成るパル
スカウント検波器6Dによシ検波丁れば、検波出力とし
て、19KIIgを中心として正及び負に変化する周波
数IC応じた信号が得られ、これを帯域増幅器αDで増
幅し喪後整流回路[18で整流Tれば、雑音に応じた直
流出力が発生し、該直流出力を制御信号発生回路0に印
加することによシ、出力端子□□□に制御l]倍信号発
生Tる。この制#倍づを、第2図の場合と同様に、ステ
レオMPx回路(5)に印加すれば、ステレオ分離度の
調整及び高域減衰の副1にな行うことが出来、8N比の
向上を吐ることが出来る。
Therefore, if the output of the second frequency divider +151 is detected by a pulse count detector 6D consisting of a monostable multivibrator (support) and an integrating circuit (end), the detected output will be 19KIIg. A signal corresponding to the frequency IC that changes positively and negatively around the center is obtained, and this is amplified by the band amplifier αD and then rectified by the rectifier circuit [18], a DC output corresponding to the noise is generated, and the DC output is By applying this to the control signal generation circuit 0, a control signal T is generated at the output terminal □□□. If this control signal is applied to the stereo MPx circuit (5) in the same way as in the case of Fig. 2, it is possible to adjust the degree of stereo separation and perform secondary attenuation of high frequencies, improving the 8N ratio. can vomit.

信8に混入Tる雑音は、信号の電界強度に対応する雑音
、マルチパスに起因する雑音、隣接チャンネル妨害に起
因する雑音、同一チャンネル妨害に起因する雑音等多々
あるが1本発明に係る聴感上の81比を改善するSN比
改善回路は、これら丁べてに有効である。特に1本発明
に係るSN比改改善路は、同一チャンネル妨害のうち、
従来は全く対処出来なかりた7R繊の浅い妨W信号によ
る同一チャンネル妨害(第1図の如く雑音が発生する〕
に対しても、大きな効果を発挿することが出来るという
大きな利点を有するので、地理的近接点に同一チャンネ
ル放送局が存在する地域間の?麗ステレオ受信機に利用
して多大な効果がある。
There are many types of noise mixed into the signal 8, such as noise corresponding to the electric field strength of the signal, noise caused by multipath, noise caused by adjacent channel interference, and noise caused by co-channel interference. The above SN ratio improvement circuit that improves the 81 ratio is effective for all of these. In particular, the SN ratio improvement method according to one aspect of the present invention eliminates co-channel interference.
Same channel interference due to shallow jamming signal of 7R fiber, which could not be dealt with in the past (noise occurs as shown in Figure 1)
It has the great advantage of being able to generate a large effect even between regions where broadcasting stations of the same channel exist at geographically close points. It has a great effect when used in a beautiful stereo receiver.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、同一チャンネル妨害による雑音を示す特性図
、第2図は本発明の一実施例を示す回路ブロック図、第
5図及び第4図はその具体回路例な示す回路ブロック図
、第5図は本発明の別の実施例を示す回路ブロック図で
ある。 生な図番の説明 (5)・・・ステレオMP!回路、−・・・PI、L回
路、αD・・・位相比較ti、ne・・・帯域通過フィ
ルタ、αD・・・帯域増幅器、(181・・・整流回路
、叫・・・制御信号発生回路。 第1図 (KHz3 第3図
FIG. 1 is a characteristic diagram showing noise due to co-channel interference, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, FIGS. 5 and 4 are circuit block diagrams showing specific circuit examples thereof, and FIG. FIG. 5 is a circuit block diagram showing another embodiment of the present invention. Explanation of raw drawing numbers (5)...Stereo MP! Circuit, -... PI, L circuit, αD... Phase comparison ti, ne... Bandpass filter, αD... Bandwidth amplifier, (181... Rectifier circuit, Control signal generation circuit Figure 1 (KHz3 Figure 3

Claims (1)

【特許請求の範囲】[Claims] (IIFM復調回路の出力中の15KIIgから25K
Hz迄の帯域に含まれる雑音成分を検出し、Fk雑音成
分に応じて?麗復蘭回路の出力を左右ステレオ信号に分
離する為のステレオマルチプレックス回路を制御し、そ
れによりて@記ステレオマルチプレックス回路の出力信
号の81比な改讐する様に成したことを特徴上する87
1比改譬回路。
(From 15KIIg to 25K during the output of the IIFM demodulation circuit)
Detects noise components included in the band up to Hz, and detects them depending on the Fk noise component. The feature is that the stereo multiplex circuit for separating the output of the Reifuran circuit into left and right stereo signals is controlled, thereby improving the 81 ratio of the output signal of the stereo multiplex circuit. do87
1 ratio conversion circuit.
JP19408681A 1981-12-01 1981-12-01 Sn ratio improving circuit Granted JPS5895444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19408681A JPS5895444A (en) 1981-12-01 1981-12-01 Sn ratio improving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19408681A JPS5895444A (en) 1981-12-01 1981-12-01 Sn ratio improving circuit

Publications (2)

Publication Number Publication Date
JPS5895444A true JPS5895444A (en) 1983-06-07
JPS6313619B2 JPS6313619B2 (en) 1988-03-26

Family

ID=16318717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19408681A Granted JPS5895444A (en) 1981-12-01 1981-12-01 Sn ratio improving circuit

Country Status (1)

Country Link
JP (1) JPS5895444A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393842A2 (en) * 1989-04-20 1990-10-24 Delco Electronics Corporation Closed-loop audio attenuator
EP0405541A2 (en) * 1989-06-30 1991-01-02 Pioneer Electronic Corporation Noise suppression apparatus for FM receiver
US5027402A (en) * 1989-12-22 1991-06-25 Allegro Microsystems, Inc. Blend-on-noise stereo decoder

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03111167A (en) * 1989-09-22 1991-05-10 O S G Kk Manufacture of rolled die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS452727Y1 (en) * 1965-09-09 1970-02-05
JPS5859249U (en) * 1981-10-16 1983-04-21 富士通テン株式会社 PLL stereo demodulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS452727Y1 (en) * 1965-09-09 1970-02-05
JPS5859249U (en) * 1981-10-16 1983-04-21 富士通テン株式会社 PLL stereo demodulator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393842A2 (en) * 1989-04-20 1990-10-24 Delco Electronics Corporation Closed-loop audio attenuator
EP0405541A2 (en) * 1989-06-30 1991-01-02 Pioneer Electronic Corporation Noise suppression apparatus for FM receiver
US5027402A (en) * 1989-12-22 1991-06-25 Allegro Microsystems, Inc. Blend-on-noise stereo decoder

Also Published As

Publication number Publication date
JPS6313619B2 (en) 1988-03-26

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