JPS589457A - Transmitting circuit of pulse signal - Google Patents

Abstract

PURPOSE:To suppress the current flowing to a closed loop between the windings, by turning on a switch circuit provided in the closed loop when no pulse signal exists, and turning off the switch circuit provided between the middle point of the winding and a voltage source. CONSTITUTION:The switch circuits 26 and 27 plus the matched resistances 32 and 33 are provided to two closed loops respectively. A switch circuit 31 is set between the middle point of the winding of a transformer circuit 23 and a voltage source 25. When ''0'' of a bipolar signal is transmitted, both circuits 26 and 27 are closed with the circuit 31 opened. In this case the termination is carried out by the winding of the circuit 23 and the resistances 32 and 33 to realize the matching of impedance with the load ZL of a load circuit 24. At the same time, the supply of current to the closed loop is discontinued by opening the circuit 31. Thus the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse signal sending circuit, and in particular to a pulse signal sending circuit that maintains constant output impedance regardless of the presence or absence of a signal and uses low power when no signal is present. It is related to.

In recent years, PCM transmission has been rapidly put into practical use.

The PCM transmission currently being carried out is of a type in which a signal sending circuit 1 and a signal receiving circuit 2 are coupled by a pair of lines 3, as shown in FIG. This is what is called inter-office transmission, and is being transmitted over a newly laid line. Therefore, as shown in FIG. Even if impedance matching is not achieved in the circuit, the occurrence of secondary reflection, which will be described later, is not a problem, and no consideration is given to the negative effects on the receiving side caused by branching of the line.

However, the transmission line between subscribers and stations has a problem unique to subscriber systems in that it is difficult to predict where subscribers will appear in the future. The track is laid as a branched track as shown in Figure 2.

In FIG. 2, a pair of lines 3 are shown branching off to lines 4.6°9 at contact points where they are connected to lines 5 and 7°8, respectively.

FIG. 3 shows a state in which a subscriber appears on the line shown in FIG. 2 and the signal sending circuit and signal receiving circuit are connected. In FIG. 3, the opposite side of the line 4.6.9 connected to the lines 3, 5, 7.8 to which the subscriber is not tangential is normally an open end, causing signal reflection. Therefore, from the viewpoint of signal transmission between the signal sending circuit 1 and the signal receiving circuit 2, the line 4.6.9 having an open end is connected to the signal receiving circuit from the signal sending circuit 1 in FIG. 3 as shown in FIG. The loss peak fM + fM in the frequency characteristics of the line leading to 2.
,... will occur. It is known that there is a relationship between the first peak fM1 and the open end speed), and as the length of the line with the open end becomes longer, the frequency of fMI becomes lower.
Since fHI enters the transmission band, it becomes difficult to equalize the lines in the signal receiving circuit 2. Furthermore, when the number of lines having open ends increases, the losses of the lines having open ends are added together, and the peak loss is large, making equalization difficult. Here, in the MM equalization in the signal receiving circuit 2, a method of equalization is normally used to minimize code amount interference on the time axis. At this time, the influence of the open-ended line on code amount interference appears as a sub-response with the same polarity as the main response, as shown in Figure 5, so line equalization is performed to minimize this sub-response. become.

On the other hand, if the signal sending circuit 1 is of a well-matched type,
The line 8 to which the signal sending circuit 1 is connected operates as a line that newly has an open end and causes secondary reflection of the reflected component of the signal by another line that has an open end.

Therefore, since (3) a new line with an open end is added to the line from the signal sending circuit 1 to the signal receiving circuit 2, the # line etc. in the signal receiving circuit 2 will increase the peak loss. It becomes even more difficult to

Therefore, in order to reduce the difficulty of line equalization in the signal receiving circuit 2, the signal sending port Ml needs to be of a type that allows impedance matching without signal reflection.

FIG. 6 shows a conventional example. Further, FIG. 7 is a time chart of signals at corresponding locations in the conventional example shown in FIG.

In Figure 6, circuits 11 and 12 are D-type flip-flops, circuit 13 is a NAND gate, and circuits 14 and 15 are AN
D gate, circuit 16.17 is inverter gate, circuit 1
8.19 is a switching transistor, circuit 20.21
is a resistor, the circuit 22 is a matching resistor, the circuit 23 is an output transformer having a midpoint to which the circuit 22 is connected in order to form a switching type output circuit using a single power supply, and the circuit 24 is a load.

In FIG. 7, signals (a) and (b) are inputs to the circuit 11, signal (a) is input data, and signal (in the middle) is a clock (4). Signal (C) is the output of the circuit 11 and is obtained by sampling signal (a) with signal (b). signal (d
) is the output of the circuit 13, which is obtained by NANDing the signal (C) and the inverted signal of the signal Φ) by the circuit 16,
The 0'' level of signal (d) corresponds to the logic f!11 of signal (a). Signals (e) and (f) indicate that signal (d) is connected to circuit 1.
This is the output frequency divided by 2. Signal (g) t (h
) is the output of the circuit 14.15, and the logic 1 of the signal (a) appears alternately in the signals (g) t (h).

This circuit consists of a signal (
g), middle), the circuits 18 and 19 turn ON'' only when the logic is 1, and then the circuit 24 is turned on through the circuit 23.
Then, a cabaihole signal is supplied as shown in signal 0) in FIG. In the conventional example of FIG. 6, the problem of matching the load of the output circuit is that the circuit 18't or 19 is 'ON'.
Only when the load ZL of the circuit 24 is reduced by the resistance R of the circuit 22
However, in the absence of a pulse signal, matching cannot be achieved. Furthermore, this will be explained using an equivalent circuit.

FIG. 8 is an equivalent circuit of the output circuit portion of the embodiment shown in FIG.

In FIG. 8 the circuits 22, 24, 23 are the same as in FIG.

Circuit 25 is a power supply, circuits 26 and 27 are switches, and switching transistor circuits 18 and 19 in FIG.
1, which corresponds to FIG.
flows through the transformer of the resistor circuit 23. The current flows through the load of the circuit 24 by the action of the transformer circuit 23. What should be noted in Fig. 8 is the circuit 26.
, 27 alternately close the switches (corresponding to ±1 transmission of bipolar signals), and 1 means that both switches of circuits 26 and 27 are closed (corresponding to O transmission of bipolar signals).

Therefore, when the switch in circuit 26 or 27 is closed, the circuit is impedance matched, but circuit 26.
If both switches 27 are not closed, impedance matching cannot be achieved.

As described above, conventional circuits have drawbacks such as impedance matching with the load.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse signal sending circuit that can always maintain impedance matching and can reduce power consumption.

According to the present invention, in a pulse signal sending circuit which sends out a chivalrous signal by transformer coupling of first and second windings and has an output impedance of 2, the two first A closed loop is formed through the winding resistance, first and second switch circuits are provided in each of the closed loops, and a third switch is provided between the midpoint of the first winding and the voltage source. a circuit is provided, and when the pulse signal is absent, the first and second switch circuits are turned on and the third switch circuit is turned off, thereby setting the output impedance of the pulse signal sending circuit to 2 and setting the output impedance of the pulse signal sending circuit to 2, and A pulse signal sending circuit is proposed, which is characterized by reducing power consumption by suppressing the current flowing in a closed loop between two windings.

Embodiments of the pulse signal sending circuit according to the present invention will be described in detail below.

(7) FIG. 9 is a principle diagram for explaining the present invention, and FIG. 10 is an embodiment of the present invention.

In FIG. 9(a) l(b), circuits 23 and 24
is similar to that described in FIGS. 6 and 8. The circuits 25, 26, 27 are the same as those in FIG.

Circuit 31 is an added switching circuit, circuit 32.3
3 is a matching resistor.

Figure 9(a) shows the bipolar signal "+17/or -1".
"Indicates the sending state, and either circuit 26 or 27 is open and circuit 31 is closed. At this time, circuit 25 is connected to circuit 2.
3 transformer, circuit 32 or 33 and current flows through circuit 2
At the same time, impedance matching between the load ZL of the multi-circuit 24 and the load ZL of the multi-circuit 24 is realized by the matching resistor of the circuit 32 or 33.

FIG. 9(b) shows a state in which the bipolar signal is sent out as "0", with circuits 26 and 27 both valves closed and circuit 31 open. At this time, the circuit 240 is terminated by the first winding of the output transformer of the circuit 23 and the matching resistor of the circuit 32.33.
Impedance matching with the load ZL (8 nos) is achieved, and by opening the circuit 31, current is no longer supplied to the closed loop, achieving low power consumption.

FIG. 10 shows the principle diagram of FIG. 9 realized in an output circuit, and is one embodiment of the present invention. Fig. 11 is the time chart/-, J In Fig. 10, circuits 11 and 12
, 13, 16.17 and circuit 18t19t20t21.2
3 and 24 are the same as in Fig. 6, 1 circuit 14.15 NAND gates, and circuit 34 is the switch circuit p31 in Fig. 9.
Switching transistor corresponding to circuit 32.33
is the same matching resistor as in FIG. 9, and the circuit has 35 resistors.

Signals (a) and (b) in Figure 10 and Figure 1
, (C) t (d) *(e) l (f) is the sixth
It is the same as Figure 7 and Figure 7.

This circuit uses a signal (
g)'*(hY makes circuits 18 and 19 1 logic each)
It is turned off only when the signal (a) is "0", and at that time, a bipolar signal as shown in FIG. If the signal is (Th)', both windings 1318 and 19 are on, and the two windings of circuit 23 are connected to circuits 32 and 3.
The circuit 34 is terminated by a matching resistor No. 3, and is turned off only when the circuit 34 is in the h-IOH state by the signal (d). When the bipolar signal "published" or "-1" is being sent out by such an operation, only the circuit 32 sends out the bipolar signal "0" through the circuit 33.
”, circuit 2 is sent by circuits 32 and 33.
Impedance matching with 4 can always be achieved,
When the bipolar signal O'' is being sent, the circuit 34 can reduce the power consumption.

As described above in detail, according to the present invention, impedance matching with the load can always be achieved, and by suppressing signal reflection in the signal sending circuit, adverse effects on reception can be removed, and power consumption can be reduced. Further, such a configuration can be configured with a single power supply and is suitable for integrated circuits (ICJs).

[Brief explanation of drawings]

Figure 1 is a diagram for explaining a conventional transmission line, Figures 2 and 3 are diagrams for explaining the configuration of a transmission line to which the present invention is applied, and Figures 4 and 5 are diagrams for explaining the configuration of a transmission line to which the present invention is applied. Figure 6 is a circuit diagram of an example of a conventional pulse signal sending circuit, and Figure 7 is a diagram for explaining the adverse effects of frequency when not applied.
Figure 8 is an equivalent circuit of the main part of the circuit of Figure 6, Figure 9 is a principle diagram of the main part of the circuit of the present invention, and Figure 1O is a diagram showing the operation of the circuit of the present invention. FIG. 11 is a circuit diagram of one embodiment of the pulse signal sending circuit according to the present invention, and FIG. 11 is a time chart showing the operation of the circuit of FIG. In FIG. 10, 18, 19 and 34 are switching transistors, 32 and 33 are matching resistors, and 24 is a storage circuit. Patent applicant Fujitsu Corporation Nippon Telegraph and Telephone Public Corporation Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi (11) 1II Figure 3 2 (12) fM1fM2 Frequency 6 Continuing from Figure 1 page [phase] Inventor Masaaki Sasayo Yokosuka Automobile 1-2356 Nippon Telegraph and Telephone Public Corporation Yokosuka Telecommunications Research Center Applicant Nippon Telegraph and Telephone Public Corporation

Claims (1)

[Claims] In a pulse signal sending circuit that sends out a pulse signal by transformer coupling of first and second windings and has an output impedance of 2, two first windings and a resistance are connected to each other from the midpoint of the first winding. a first and a second switch circuit are provided in each of the closed loops, and a third switch circuit is provided between the midpoint of the first winding and the voltage source, and a third switch circuit is provided between the midpoint of the first winding and the voltage source; By turning on the first and second switch circuits and turning off the third switch circuit in the absence of a pulse signal, the output impedance of the pulse signal sending circuit is set to 2, and between the two first windings. A pulse signal transmission circuit characterized by reducing power consumption by suppressing the current flowing in the closed loop of the circuit.