JPS5894034A - Data transmitter - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the processing efficiency for the 1st system for a device which transmits the data between the 1st and 2nd systems which work asynchronously with each other, by giving a block process to each of plural sets of data which are supplied from the 1st system. CONSTITUTION:For a device which transmits the data between the 1st and 2nd systems which work asynchronously with each other, the 1st system 1 delivers a stop code as a type of data every time the process output of each set of data is through. The 2nd system 2 detects the stop code to perform a stop process. Thus it is possible to perform the process of data for each block and between the systems 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data transmission device that is equipped with an FIFt (FIFt) as an interface for coupling two systems that operate asynchronously and that transmits data between the two systems.

TECHNICAL BACKGROUND OF THE INVENTION FIG. 1 shows an overview of a conventional data transmission device. In FIG. 1, 1 is a first system, 2 is a second system, and 3 is a FIFO that connects the systems 1 and 2 via a first path 4 and a second path 5. The FIFO
The characteristics of j are: ■ It has an input/output order in which the first input data is output first, ■ Input and output are asynchronous, and ■ FIFO itself determines whether input and output are possible. The point is to output the results.

The first system J u receives an input enable signal S1 from the FIFO, outputs data onto the first path 4, and outputs a write-in signal S2 to the FIFOJ.

When the FIFOJ is in the input enable state, the input enable signal S1
is output to the first system 1, and the data on the first path 4 and the write signal S2 from the first system 1 are input. When the PIF'03 is in the input enabled state, when the write signal S2 is input from the first system 1 to the FIFOJ, the data on the first path 4 is written to the FIFOJ. Further, the PIFO3 is the 20th system 2
Inputs the read signal S3 from , outputs the output enable signal S6 to the second system 2 when the output is enabled, and outputs the data 5 degrees above the second path. and the data on the second path 5 are asynchronous, and the data output order of the second path 5 is the same as that of the first path 4.
This is the same as the data input order above. On the other hand, the FIFO
3 is in the output enabled state, when the read signal 83 is input from the second system 2 , the data on the second path 5 is read out to the second system 2 . Note that the first and second systems are composed of digital computers. In addition, input enable signal S1 and output enable signal B6td, FIF
Since the signal is from the OJ itself, there is no need for a separate control circuit or the like.

As is well known, for example, when the first system 1 is a high-speed computer and the second system 2 is a low-speed computer, data is written from the first system 1 to the FIFOJ at high speed, and from the FIFQ 3 to the second System 2 can read data at low speed. Conversely, the first system 1
It is well known that even when the second system 2 is low speed and the second system 2 is high speed, the PIFO 3 is similarly used as the interface.

Regarding the operating principle of the above-mentioned PIFO3, for example, there is an explanatory article r Electro Digest J magazine published by Electro Digest, November 1974 issue, pages 1 to 8.
"Characteristics and Applications of FIFo Memory". Here, the description thereof will be omitted as it is well known.

Problems with the Background Art Now, for example, when the first system 1 is a high-speed computer that controls the controlled object online, and the g2 system 2 is a low-speed recording needle, conventionally the data to be transmitted has not been prepared in advance. The order and number of data are determined and transmitted from the first system 1 to the second system 2 according to a predetermined transmission format. In this case, it is impossible to change the order or number of data, and processing such as reconfiguring the data to match the transmission format and preparing dummy data for types of data that do not need to be transmitted is the first 7th standard. 1, the first system 1 reduces the processing efficiency of calculations.

Hereinafter, this point will be specifically explained using FIG. 2.

Here, for simplicity, the transmission format transmitted from the first system 1 to the second system 2 is the type of data:
4 types of A, B, C, D, order; A, B, C, D order;
Number: 4 words, let die be X. For example, if the first system 1 performs arithmetic processing in the order of CAD in the first processing and Bm in the second processing, the datums XCD and BXX are transferred to the second system. 2
, it is necessary to prepare a dummy during data reconstruction.

As described above, since the conventional technology uses a transmission format in which the order and number of transmitted data are fixed, there is a drawback that the arithmetic processing efficiency of the first system 1 is reduced.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the prior art as described above.
．． In data transmission between the second systems, the second system can process multiple sets of data from the first system for each set of weights without completely reducing the processing efficiency of the first system. The objective is to provide a data transmission device that can.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an apparatus for transmitting data between a first system and a second system that operate asynchronously, which is equipped with a FIFO as an interface for coupling the systems. Multiple sets of r-, including a stop code that indicates the delimitation of each set of data.
the first system for reading the data; extracting the data from the FIFO; detecting the stop code;
Separate the extracted data for each stop code.
and the second system for processing each set weight, and a control circuit is provided, and the first system is connected to the control circuit by F.
A start signal for reading out the data in the IFO is output to each group of the data, and the 1111j control circuit reads out the data in the FIFO and outputs it to the second system, and also outputs a start signal to read out the data in the FIFO, and also outputs a start signal to read out the data in the FIFO. It is characterized in that when it detects the end signal of each set of data, it outputs the end signal of each set of data to the second system.

Embodiment of the Invention Hereinafter, an embodiment of the invention shown in FIG. 3 and FIG. 4(a) will be described. FIG. 3 shows an example of the configuration of a data transmission device according to the present invention, and the configuration is the same as that of FIG. 1 described above. Further, FIG. 4(a) shows a flowchart of the output to FIFOj of the first system 1, and FIG. 4(b) shows a flowchart of the input from the WIFOs of the second system 2. .

First, in FIG. 4 (&), 8 is the output, 9 is the judgment whether the transmission is completed, 10 is the strike, ! Each represents the code output. The processing in the first system 1 starts by outputting data on the first path 4 and writing it into the FIFO, and then determining whether or not the required number of words has been transmitted.
If NO, output the data to the '1st pass 4 again El,...
If YES, strike! Output the code on the first path 4 and write it to 10°Fl, FOj. Also, in Fig. 4(b), 1-1 is the input, 12 is the strike code, judgment is made as to whether it is a go code, and 13 is the stop processing. represent. The processing in the second system 2 starts with the FIF
The data on the second path 5 is inputted 10 from O3, and then it is determined 11 whether the data on the second path s is a strike or zo code, and if NO, the second path 6 is inputted again. Enter the above data, and if YES, strike! Process 13 is performed.

Next, the operation of the data transmission device configured as above will be described. Note that an example used in the explanation of -1 prior art will be explained here.

Now, it is assumed that the first system 1 outputs "CAD" as the first processing output and "BA" as the second processing output to the FIFO 3.

As explained in FIG. 4, the first system 1 outputs a stop code every time the processing is completed, so this code is written as "S". :, the data on path 4 of Ml is 1CmD8BA" in the output order. Then, F
IFO3 is the data on the first path 4 ""CAD8BA
" is input and output to the second system 2 as data on the second path 5 in the input order.
System 2 of @C as data on path 5 of nuclear 2
ADSBA", strike every word, f code =
Determine whether it is @8#.

As a result, the data on the second path 5 is transferred to the second system 2.
These are processed separately for each professional as "CAD" and "BA".

In this way, ■the first system 1 outputs a stop code as a type of data every time the processing output of each set is completed;
The second system 2 detects this stop code and performs stop processing, so that the first system 2 operates asynchronously. Second
It becomes possible to process data block by block in the two systems.

Modification of the invention (1) Next, another embodiment of the invention will be described with reference to FIGS. 5 and 6. In the friend embodiment described above,
The second system 2 performs FIFOJ K N and outputs the continuation signal s4, and a stop code of the data on the 20th path 6 is detected, but in this embodiment, the software of the second system 2 Alternatively, a separate control circuit is provided to reduce the hardware burden.

FIG. 5 shows an example of its configuration. In FIG. 0, the same parts as in FIGS. 1
, S7 is a read start signal, 's8 is a leveling signal, S9 is a second write signal, and S1o is a stop signal. The first system 1 outputs data on the first path 4, a first filling signal S2 to the FIFOJ, and a read start signal S1 to the control circuit 14, respectively. As a result, 'FIFOJ first receives the data on the first path 4 from the first system 1 and #! 1 write signal S3 and a heave setting signal S8 from the control circuit 14 are input, and the r-wave signal is outputted onto the second path 5. The control circuit 14 also receives a read start signal S7 from the first system 1.
, ma(r- on path 5 of 582 from r-FIFOJ
The read signal s8 is sent to the # FIFOJ, and the second write signal S9 is sent to the second system 2. A signal 810 is output respectively. As a result, the second system 2 receives the data on the second path 5 from the FIFOJ, the write signal S9 from the control circuit 14, and the write signal S9 from the control circuit 14.
) Input signal BIG.

゛ FIG. 6 shows details of the control circuit 14 in FIG. 5. Note that the data on the second path 5 is N bits (N: positive integer), and the stop code is all ""1.
”.

In FIG. 6, 41 is the first flop, 42
is a first AND circuit, 43 is an oscillator, 44 is a counter,
45 is a second AND circuit, 46 is a shift register, 41
is an N-input AND circuit, 48 is a second Fritznofrog, 49 is a NOT circuit, and 50 is a second four /T circuit.゛Thus, first, the Ml 7 lip-flop 41 has its P N input and D input connected to the power supply voltage, inputs the read start signal S1 as the clock CK input, and outputs the Q output at the rising edge of the clock CK input. 54J=”l
', and the first clear signal 849 is input as the clear CLR input, and the Q output crab '''0'' is input to the first AND circuit 42.
Output to. Further, the first AND circuit 42 outputs the Q output 847 of the first FURITUNO FUROTUNO and the second clear signal SS.
The 0 oscillator 43 which inputs 0 and outputs its negative filling output S42 as the clear CLR input of the counter 44 inputs the output to CKN of the counter 44 and the shift register 46 and outputs it. This counter 44 uses the output of the oscillator 43 as a clock CK input, and also has a navy blue 1 AND circuit output B.
42 is input as a clear CLR input, counts at the falling edge of the CKN input, and outputs the count results as Q and QB. The QA output is output to the second AND circuit 45. Further, the QB output becomes the above-mentioned heeling signal S8.

The second AND circuit w145 inputs the QA output and QB output of the counter 44, and its @embedded output becomes the second write signal S9. Note that when the clear CLR input is 0, both the QA and QB outputs of the counter 44 become 0.

On the other hand, the N-input AND circuit 41 inputs the data on the second path 5, performs a logical product, and sends the output 84F to the second path 5.
Output to 7 Ritzoflo, No.48. Second 7s! 7
0. The input circuit 41 has its PRN input and D input connected to the power supply voltage, inputs the output 84F of the N-input AND circuit 41, and when the output 84F rises, outputs the Q output 548="11" to the A input of the shift register 46 and It is output as a CLR input.Also, the second free signal 849 inputs the first clear signal 849 as a CLR input, and the CLR input=
When "0", Q output 541 = 10' is shifted to shift register 4.
Output to 6.

The shift register 46 inputs the output CKN of the oscillator 43, and inputs the Q output 848 of the second fritsuno frog as an A input and a CLR input, is counted when the CKN input rises, and outputs the count result to QA and QB. Output as . This QA high output becomes the stop signal 810 and is output to the second NOT circuit 50. Also Q
The B output is output to the ml knot circuit 49. This first
The NOT circuit 49 inputs the QB output of the shift register 46, and uses the negative output as a first clear signal 849 for the first FRI, ZO 41 and the second FRI, GFLO! 48. Further, the second NOT circuit 50 serves as the QA high output input of the shift register 46 and outputs its negative output 850 to the first AND circuit 42 .

Although the explanation here assumes that the stop codes are all "1", in other cases, such as when the data on the second path 5 is required, the negative output of the gate or the power supply voltage can be changed to the N input. The configuration may be such that it is input to the AND circuit 41.

Next, the operation of the present device configured as shown in FIG. #I5 and FIG. 6 will be explained using FIG. 7.

Note that the operation of writing data from the first system 1 to the FIFO in Fig. 5 is well known, so a description thereof will be omitted. FIG. 7 shows a time chart of the present invention, and each signal name is indicated by the same signal in FIGS. 5 and 6.

Now, when the start-up signal S1 becomes "ml", the output 84J of the first step 41 becomes "1", and the output 842 of the first AND circuit 42 becomes "1". Therefore, at the second falling edge of the output 8430 of the oscillator 43, the start-up signal 88 becomes 11''. When the read signal 88 rises, the data S5 on the second path 5 from the FIFOJ is read out. Then, at the fall of the output 843 of the oscillator 4J, the second read signal 89 is read out. 11'', the first food item of the data s5 on the second path 5 is written to the second system 2.Furthermore, when the output 843 of the oscillator 43 falls, the start-up signal 88 and The second write signal S9 is "O" and the read signal S8 is 1.
01, the data 85 on the second path S becomes high impedance. Thereafter, when the read signal 8J1 rises by the counter 44, the second sword of the data S5 on the second path 5 is written into the second system 2. The same process is repeated below.

On the other hand, when the N-input AND circuit 41 inputs the stock code=all ""l", the output 84F of the N-input AND circuit 41 becomes 11".

When the output 84F of the N-input AND circuit 41 rises, the output S number 8411 of the second FRI, fFLO, NO 48 becomes @1.
1, when the output 4J of the excavator 43 rises, the f signal 810 becomes "1" and #! It is output to system 2 of 2. When this stop signal 810 becomes "l", the second
The clear signal SSO becomes @0#, and the output 842 of the first AND circuit INr4j becomes 10', and the read signal S8 and the second read signal 89 become 10.
". Furthermore, when the second clear signal 849 becomes 10" due to the rising edge of the output 430 of the oscillator 43, the first 70°f41f) output 841 and the output 848 of the second f4# ``o1 and nasi, upper ml
The ST, Z signal 810 becomes "0", and the second clear signal 849 returns to @1", which is a series of actions from the rise of the read activation signal to the fall of the ST,! signal.

Note that the arrangement of the output terminals of the counter and shift register in the ls6 diagram may vary depending on the time width of each number 16 in the time chart diagram shown in FIG. Also, positive logic,
Due to the negative logic, the use of r-) and flip-flops in FIG. 6 may vary. These modifications can be easily deduced from this example, and these modifications are included in this example. In addition, in this embodiment, the FIFO shown in FIG.
The input enable signal S1 and output enable signal S5 of FIFOJ were not used, but this is because the storage capacity of PIF'OJ in FIG. 5 is known, so the first write signal S1 and read signal S8 are This is because the data is output to the FIFOs in the input enabled state and output enabled state.

As described above, according to the configuration shown in FIGS. 5 and 6, the control circuit 14 detects the stop code from the data on the second path and outputs the stop signal 810 to the second system 2. By this, the first system 1 and (
j fM 2 tD Both systems 2 and 2 can perform processing on a professional basis.

(2) In the embodiments shown in FIGS. 5 and 6 above, the read start signal S7 from the first system 1 is sent to the control circuit before the stop signal 810 is output from the control circuit 14 to the second system 2. 14 is not input. That is, the processing results of the th set of the first system 1 are output to the FIFO 3, and the read start signal S
7, the output from the PIFO 3 to the second system 2 is started, and after the processing results of the 2nd set have been output to the 2nd system 2, the (K+1
It is assumed that the read start signal S7 for the processing result of the )th set is output to the control circuit 14. However, the first
Depending on the processing of system 1, M
In the system 1 of No. 41, processing of the Mf K+1 )th set and output to g FIFQ3 are completed, and it is also possible to output the read start signal S7 to the control circuit 14.゛The configuration of an embodiment of the present invention for this case is shown in No. 8-.

Figure 8 shows @1's 7 lip flop 74 in Figure 6.
61, 62, and 63 are the 3rd. 4th. 5th 7 Ripfrotz! and 64 is a third AND circuit. Further, the same parts as in FIG. 6 are indicated by the same reference numerals.

In FIG.
It is connected to the D large input and the PR large input power supply voltage, and by inputting the read start signal S7 with the CK large input, l, C
When the K input rises, the Q output (s61) = "x" is output to the third AND circuit 64. Further, when CLR="0", Q output 561="0" is output to the third AND circuit 64. The third AND circuit 6°4 is the third flip! The output S'61 of the file f61 and the fifth 79.f file f
The Q output of 6B is input, and the logical product output 864 is output as the D input of the fourth 70 ftqt. The fourth 7-lip converter 62 has its PR large input and CLR input connected to the power supply voltage, receives the first and third AND circuit outputs 864 as its D input, receives its CKN input, and receives the output S43 of the oscillator 43. Said fourth furitsunofurotsuno 62
The Q output 862 is the fifth free lag 70, and the CK of Noro 3
N input, Q output to C of the third Fritsuno 61
They are output as LR inputs. The fifth Frisogefurotsuno 63 has its PR large input and D input connected to the power supply voltage,
The Q output 862 of the fourth Furitsuno Furitsuno 62 is manually inputted to CKN, and the lth clear signal 84 is input as the CLR input.
G input, Q output 863 to the first AND circuit 42,
Further, the Q output is outputted to the third AND circuit 64.

Next, the operation of the apparatus constructed as above will be explained using FIG. 9. Note that each signal name in FIG. 9 corresponds to the same signal name in FIG. 8, respectively.

First, after the data S5 on the second path 5 corresponding to the (K-1)th set of processing results in the first system 1 has been written to the second system 2, A case will be described in which the read start No. 16 S7 corresponding to the processing result of the th set is input. Now, when the start-up bow S7 becomes 11", the 4iI43's fritsunoflow, no.
861 became Pa 1", and now the 5th Furisogefurotsuno 6
Since the Q output of 3 is '1''', the third AND circuit 6
4's output S64 becomes '1''. At the rise of the oscillator output 843, the Q output 862 of the 4th frisogeflotsuno 62 becomes l#. The output 861 of the 3rd fritsunofrog 61 becomes '0' ◎ Also, the output S64 of the third AND circuit 64 also becomes '0', and the oscillator 43
With the rise of the output 843, the fourth
The Q output S62 of the 2nd circuit becomes 0''. When the Q output 863 of the 5th fritsunofurotsuno 63 becomes 1'', the output 842 of the first AND circuit 42 becomes 1'', and henceforth.

The indulgence signal S8 and the second
A write signal J#-jS 9 is output.

Next, before the writing of the data s5 of pass 50 of the 2nd pass corresponding to the processing result of the (K+1)th group is completed to the second system 2, the processing result of the (K+1)th A case where the read start signal S7 is input will be explained.

Now, when the read start signal S2 is input, the output 56JFi of the third frit-no-flotz f61 becomes "1", but since the Q output of the fifth frit-no-flotz 63 is "0",
The output s64 of the third AND circuit 64 remains at "0". That is, the (K+1)th set of set-up start signal 87 is checked by -)7, but the set-up of the (K+1)th set of data is put on standby. When the output 847 of the N-input AND circuit 470 becomes "11" and the ST 2711 810 finishes outputting as in FIG. The output 864 becomes 1'', and reading is permitted by the read activation signal S7 for the (K+1)th set of processing results.Hereinafter, l) The time chart is the same as that already explained.

In this way, according to the real IM example, the lth system 1
From No. (K+1) 1, the start of the stitching of the eye group No. 11 No. 8
7 is input to the control circuit 14 at any timing,
Fl)'O,? The MK4 to the system 2 of m12 is made to wait until the output of the data on the second path 5 of the eye set is completed, and the (K+1)th readout is started 16 after the output of the fourth eye is completed. It is possible to permit hedding according to No. S1.

(3) In the above embodiment, the readout signal S8 from the control circuit 14 to the FIFO 3 is activated in response to the heel start signal S7 from the first system 1.

However, due to the output aJ function signal S6 of the FIFO3,
It is also possible to control this heave setting signal S8,
This embodiment will be explained using FIG. 10, FIG. 11, and FIG. 12.

In FIG. 10, 14 is a control circuit, except that the control circuit J4A manually outputs the output enable signal S6 from the FIFOJ, and that the start-up signal S7 in FIG. m5 is not in FIG. It has the same configuration as that shown in FIG.

FIG. 11 shows the details of the control circuit 14 in FIG. 10, with 65 and 66 being the third and fourth knot circuits, and 67 being the sixth flip-flop! It is.

This 30th knot circuit 65 manually outputs the output enable signal S6, and sends the output S65 to the 6th pref, fflop f.
67 PR large input and output.

In addition, the CLR input of this sixth fritsuno 62 is unified to the 11t source voltage, the D input is unified to ovK7, and the third
The output 865 of the knot circuit 65 is input as a PR input, and the Q output 867='l' is input to the first ant circuit 4.
Output to 2. Furthermore, the CK large input is input, the output S66 of the fourth NOT circuit 66 is input, and the Q output 56 is input at the rising stage.
7="0" is output to the first AND circuit 42. The fourth knot circuit 66 inputs the QB output of the color/return circuit 44 and outputs its negative output 866 to the sixth flip-flop 67. Note that the other elements are the same as those in FIG. 6, so their explanation will be omitted.

Next, the operation of this fruitful example will be explained using FIG. 12. In FIG. 12, the output enable signal S6 is now “1”.
Then, the output 867 of the sixth Frinobu Flora f67 becomes '1'', and therefore the output 84 of the first AND circuit 42
2 becomes "1#," as described above, the start-up symbol S8 and the second write signal S9 become "1".

Here, due to the nature of FIFQJ, the read signal S8 is 1
”, it means that the thread is being cut out, so the output ready signal S
6 becomes et Oa. 'Also, the read signal S8 is “
When it becomes 0#, the output enable signal S6 returns to "'l#." In FIG.
67 becomes "0#" at the fall of this start-up signal S8. The same operation is repeated thereafter. Then, by detecting the stop code in the same manner as in FIG. 7, the first system 1 In the second system 2, a coherent process is performed for each lock.

As described above, according to this embodiment, the read signal to the FIFQ3 can be controlled by using the output enable signal of the FIFOJ.

As described in detail, the data transmission device of the present invention provides the following effects.

(1) The first system outputs a stop code as a data delimiter to the FIFO, and the control circuit of the second system detects the stop code and performs predetermined stop and f processing. In this system, it is possible to perform processing corresponding to a block of data output from the first system.

(2) By providing a function to wait for a data read start signal from the first system to the control circuit, the FIF
In the data transmission from O to the second system, after the transmission of data corresponding to the previous process of the system of stripe 1 is completed, it is possible to start transmitting the data corresponding to the current process.

[Brief explanation of drawings]

Figures 1 and 2 are schematic diagrams for explaining the prior art, and Figures 3 and 4 (a) ψ) are schematic diagrams showing an embodiment of the present invention. Figures 5 to 12 are FIG. 6 is a schematic diagram showing another embodiment of the present invention. 1... ml system, 2... second system, 3
...FIFO14...first bus, 5...second bus, 8...output, 9...transmission end judgment, 1o...
・Stotsuno code output, 11... Input, 12... Strike, saw-')' size ML J s... Stotsuno processing. Applicant's representative Patent attorney Takehiko Sunae Figure 1 Figure 2 Figure 3 Figure 4 (a) (b) Figure 6■ Shi-J Figure 7 Figure 81! I Fig. 9 (510) -111, ---- Dm 1011 Fig. 12 (567) J U L Fig. 11, -1 to -J

Claims (4)

[Claims] (1) The first system and Shima 2 that operate asynchronously
An apparatus for transmitting data between systems, comprising a FIFO as an interface for connecting the systems, and #FIFO indicating a division of each set of data;
! the first system writes a plurality of sets of data including codes, reads the data from the FIFO, detects the strag code, and divides the read data into each set by dividing the data by the strag code; A data transmission device comprising the second system for processing each time. (2) A device for transmitting data between a first system and a second system that operate asynchronously, which includes a control circuit and a FIFO as an interface for connecting the systems, and #FIFO is used to divide each set of data. the first system for omitting a plurality of sets of data including the indicated strag codes; and the first system extracts the data from the FIFO, detects the strag codes, and separates the read data for each strag code. and the second system processes each set of data by attaching a , and the first system outputs to the control circuit a starting credit for reading data in the FIFO for each set of data, The control circuit reads out the data in the FIFQ and outputs it to the second system, and outputs an end signal of each set of data to the second system when it detects a strag code indicating a break between each set. A data transmission device characterized in that: (3) In the invention described in claim No. (2), the control circuit is provided with a circuit that waits for the start signal from the first system, and the control circuit (K is a positive integer) data set, m2
During output to the (K+1)th system, the (K+1)th readout starts (No. 8 is placed on standby, and after the control circuit finishes the readout processing of the first r-tater, the data of the (K+1)th set is Nine data transmission devices to allow reading. (4) The data transmission device according to claim (2), wherein the control circuit reads out the FIFO when the control circuit receives an output enable signal from the FIFO.