JPS589321A - Manufacture of silicon thin-film - Google Patents

Manufacture of silicon thin-film

Info

Publication number
JPS589321A
JPS589321A JP56105704A JP10570481A JPS589321A JP S589321 A JPS589321 A JP S589321A JP 56105704 A JP56105704 A JP 56105704A JP 10570481 A JP10570481 A JP 10570481A JP S589321 A JPS589321 A JP S589321A
Authority
JP
Japan
Prior art keywords
thin film
silicon thin
film substrate
manufacturing
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56105704A
Other languages
Japanese (ja)
Other versions
JPH0376019B2 (en
Inventor
Kazunobu Tanaka
田中 一宜
Akihisa Matsuda
彰久 松田
Toshihiko Yoshida
利彦 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tonen General Sekiyu KK
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Toa Nenryo Kogyyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology, Toa Nenryo Kogyyo KK filed Critical Agency of Industrial Science and Technology
Priority to JP56105704A priority Critical patent/JPS589321A/en
Priority to US06/394,074 priority patent/US4490208A/en
Priority to EP82303526A priority patent/EP0069580B1/en
Priority to DE8282303526T priority patent/DE3276280D1/en
Publication of JPS589321A publication Critical patent/JPS589321A/en
Priority to US06/790,781 priority patent/US4598304A/en
Publication of JPH0376019B2 publication Critical patent/JPH0376019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

PURPOSE:To decrease a primitive additive impurity and dope a new impurity, by placing a doped Si thin-film in mixed gas plasma of one of F, Cl and H, primitive additive impurity, and another element gas. CONSTITUTION:A P or N type Si thin-film of single crystal, amorphous or mixture of fine crystal powder in amorphous is placed under plasma discharge, by mixing primitive additive impurity, and the other impure element gas at the rate of 10<-5>-10<-1> to one element of F, Cl and H, adjusting the pressure at 1.5X 10<-2>- 3 Torr, and keeping the flow within a container at a viscosity range, and varying the power density within 0.5-50W/cm<3>. At the same time, the primitive additive impurity decrease depth and new impurity doping depth can be adjusted arbitrarily from the thin-film substrate surface to a depth of 5,000Angstrom at maximum. This method decreases manufacturing processes and brings such devices of excellent characteristics as PN-junction and PIN-junction.

Description

【発明の詳細な説明】 本発明はダイオード、太陽電池、画像形成用光導電体又
は統壕装置用光電変換嵩子等に適用することのできるシ
リコン薄膜の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for producing a silicon thin film that can be applied to diodes, solar cells, photoconductors for image formation, photoelectric conversion bulkheads for tunneling devices, and the like.

従来、シリコン薄膜が所期の目的を達成するためkpi
n接合素子又はpn*合素子として使用されている。こ
のようなpin又はpn接合素子は通常グロー放電法に
よりプラズマ雰囲気下にて例えば不純物としてB(ホウ
素)を添加したpm[シリコン薄膜を形成し、次で該p
ilシリコン薄膜上に活性層である添加しないil[シ
リコン薄膜及びP(リン)を添加したnii[シリコン
薄膜を、又は前記p飄シリコン薄膜上Kl[*前記nf
jlシリコン薄膜を成長させる二つ又は三つの成膜工程
によって作製されている。別法として最初Kn層膜を、
次で1■層及びp層膜を又は前記n層膜上に直接9層膜
を成膜する作製方法も又同じょ5に行なわれた。
Conventionally, silicon thin films have been used to achieve the intended purpose by
It is used as an n-junction device or a pn* junction device. Such a pin or pn junction element is usually manufactured by forming a thin film of pm [silicon] doped with B (boron) as an impurity in a plasma atmosphere by a glow discharge method,
The active layer is formed on the il silicon thin film without doping il [silicon thin film and P (phosphorous) added nii [silicon thin film] or on the p-doped silicon thin film Kl [*the above nf
jl It is fabricated by two or three deposition steps of growing a silicon thin film. Alternatively, first the Kn layer film is
Next, the manufacturing method of forming a 12-layer film and a p-layer film or a 9-layer film directly on the n-layer film was also carried out in the same manner.

しかしながら、このような成膜方法によって作製された
素子は、既成長の下層膜上に新しい上層な成膜する@に
下層(既成長)膜の不純物がプラズマ雰囲気下で欽出さ
れ、上層の膜に混入するという欠点をもっている。その
結果、不純物を含まない基板上に成長させた膜に比べ不
純物を含む膜上に成長させた膜は、光電気伝導度及び暗
電気伝導度の低下が生じる。このため特に1太陽電池を
目的とするp1n接会半導体素子を製造した場合、基板
、p層膜、1層膜、n層膜の願に作製された素子につい
ていえば、1層腹中Kp層膜に添加した不純物が混入す
るために光電気伝導度及び暗電気伝導度が低下するとと
−に、良好な接合面が形成されない、他方、基板、n層
膜、1層膜、p層膜のI[K作製された素子についてい
えば、1層膜中にn層膜に添加した不純物が混入し、フ
ェル建レベルの位置を移動させるため、充分な開放電圧
を得ることができない。これらのことは結局、光のエネ
ルギー置換効率が低下することを意味し、太陽電池とし
ての性能を低下せしめると同様他の蹟用途に使用した場
合にも性能の低下をもたらすものであった。
However, when a new upper layer is formed on an already grown lower layer, the impurities in the lower layer (already grown) are extracted in a plasma atmosphere, and the elements fabricated by such a film formation method are damaged. It has the disadvantage of being mixed with As a result, a film grown on a film containing impurities has lower photoelectric conductivity and dark electrical conductivity than a film grown on a substrate that does not contain impurities. For this reason, when manufacturing a p1n junction semiconductor device especially for the purpose of a solar cell, if the device is fabricated using a substrate, a p-layer film, a single-layer film, and an n-layer film, the Kp layer in the middle of the first layer is If the photoelectric conductivity and dark electric conductivity decrease due to the contamination of impurities added to the film, a good bonding surface will not be formed. Regarding the device manufactured by I[K, the impurity added to the n-layer film mixes into the single-layer film and moves the position of the ferrule level, making it impossible to obtain a sufficient open circuit voltage. These things ultimately mean that the energy replacement efficiency of light decreases, which leads to a decrease in performance as a solar cell as well as when used for other purposes.

本発明者等は、不純物元素を添加したpHシリコン薄膜
基板又はnilシリコン薄膜基板を弗素、塩素及び水素
の群から選択された少なくとも一元素のガスと、前記シ
リコン薄膜基板中の不純物とは別種の不純物から成るガ
スとの混合ガスのプラズマ放電状態下におくと、誼シリ
コン薄膜基板はその表面から5ooolまでの深さの不
純物量が減少し、と同時k1合ガス中の別種の不純物が
シリコン薄膜基板の表面から任意の深さkゎたってドー
ピングされることを見出した。
The present inventors have prepared a pH silicon thin film substrate or a nil silicon thin film substrate doped with an impurity element using a gas containing at least one element selected from the group of fluorine, chlorine, and hydrogen, and a gas of a type different from the impurity in the silicon thin film substrate. When the silicon thin film substrate is subjected to a plasma discharge state of a mixed gas with a gas consisting of impurities, the amount of impurities at a depth of 5 mm from the surface of the silicon thin film substrate decreases, and at the same time, other types of impurities in the mixture gas It has been found that doping can be performed at an arbitrary depth of 1,000 km from the surface of the substrate.

更に又、シリコン薄膜基板からの不純物の減少程度及び
減少深さ、並びに該シリコン薄膜基板への新たな別種の
不純物のドーピング量及び新たな不純物のドーピング深
さは、(1)グツズ!放電状11におかれる混合ガスの
組成、(Jり真空容器のプラズマ放電時圧力、及び時間
、並びk(3)プラズマ放電電力密度を調整するととk
よって種々に変え得ることが分った。
Furthermore, the degree and depth of reduction of impurities from the silicon thin film substrate, the amount of doping of a new different kind of impurity into the silicon thin film substrate, and the doping depth of new impurities are as follows: (1) Gutszu! By adjusting the composition of the mixed gas placed in the discharge state 11, the pressure and time during plasma discharge in the vacuum vessel, and (3) the plasma discharge power density,
Therefore, it was found that various changes can be made.

本発明は以上の如き新しい知見に基いてなされたもので
ある。即ち、本発明に係るシリコン薄膜の製造方法は、
不純物(A)を含むpl[又はnilシリコン薄膜基板
を、弗素、塩素及び水素の詳から適訳された元素のガス
と、シリコン薄膜基板中の不純物(ム)を異なる不純物
(B)を含むガスとからなる混合ガスのプラズマ腋電状
lIk晒し、シリコン薄膜基板の不純物(ム)の淡度を
シリコン薄膜基板の表面から所望の深さまで減少させ、
と一時に不純物(B)をシリコン薄膜基板kli面から
任意の深さまでドーピングすることを顕著な特徴とする
The present invention has been made based on the above new findings. That is, the method for manufacturing a silicon thin film according to the present invention includes:
A pl [or nil silicon thin film substrate containing an impurity (A) is mixed with a gas containing elements properly translated from the details of fluorine, chlorine and hydrogen, and a gas containing an impurity (B) which is different from the impurity (mu) in the silicon thin film substrate. exposing the silicon thin film substrate to a desired depth from the surface of the silicon thin film substrate by exposing it to a plasma axillary electric current of a mixed gas consisting of;
A distinctive feature is that the impurity (B) is simultaneously doped to an arbitrary depth from the kli surface of the silicon thin film substrate.

また、不純物(ム)が除去されるととによって、できた
ダングリングボンドは弗素又は水素と結合すると考えら
れる。
Further, it is considered that the dangling bonds formed by removing impurities (mu) bond with fluorine or hydrogen.

例え%t、Myン原子を不純物として含むpffiシリ
コン薄膜表面から、リン原子をドーピングすることkよ
ってpnll!I合素子を本発明により製造する場合に
は、このpm[シリコン薄膜基板な、ホスフィンPH,
を水素で希釈した混合ガス又は五フフ化リンを弗素で希
釈した混合ガスのプラズマ放電状態下にさらす。この操
作によってp型シリコン薄膜基板中のdaン原子の量は
!!面から所望の欅さまで減少される一方、混合ガス中
のリン原子がシリコン薄膜基板の表面から任意の深さま
で、ドーピングされ、成膜工程を必要とせず、pn!1
合素子が作製される。又、リン原子を不純物として含む
n型アモルファスシリコン薄膜基板から、ポロン原子を
ドーピングすることによってpn*合素子を本発明によ
り製造する場合には、このn型シリコン薄膜基板を、ジ
ボランB、H,を水素で希釈した混合ガス又は三フフ化
メロンを弗素で希釈した混合ガスのプラズマ放電状態下
にさらす。この操作によってnilシリコン薄膜基板中
のリン原子の量は表面から所望の深さまで減少される一
方、混合ガス中のポロン原子がシリコン薄膜の表面から
任意の深さまで、ドーピングされ、成膜工程を必要とせ
ず、pn接合素子が作製される。
For example, if phosphorus atoms are doped from the surface of a pffi silicon thin film containing %t, My atoms as impurities, pnll! When manufacturing an I-combined device according to the present invention, this pm [silicon thin film substrate, phosphine PH,
is exposed to a plasma discharge state of a mixed gas of diluted with hydrogen or a mixed gas of phosphorus pentafluoride diluted with fluorine. By this operation, the amount of dan atoms in the p-type silicon thin film substrate is reduced! ! While the pn! 1
A composite element is produced. In addition, when manufacturing a pn* composite element according to the present invention by doping poron atoms from an n-type amorphous silicon thin film substrate containing phosphorus atoms as an impurity, this n-type silicon thin film substrate may be doped with diborane B, H, The melon trifluoride is exposed to a plasma discharge state of a mixed gas diluted with hydrogen or a mixed gas diluted with fluorine. By this operation, the amount of phosphorus atoms in the nil silicon thin film substrate is reduced to a desired depth from the surface, while the poron atoms in the mixed gas are doped to the desired depth from the surface of the silicon thin film, necessitating a film formation process. A pn junction element is fabricated without doing so.

上記いずれの方法においても、混合ガスの組威即ち混合
割合を変えるととによって、シリコン薄膜基板からの不
純物の減少深さ及び他の不純物のドーピング渫さを制御
することができ、それkよって所望の性能を持った種々
のpn接合素子を製造することができ、Itはpin接
合素子をも製造することができる。更に詳しく説明する
と、本発明に係る製造方法において、混合ガスの組成は
放電時圧力及び時間並びに電力密度と共に本発明に係る
製造方法を実施する際の重要なパラメータである。ガス
組成について説明すると、(不純物(B)ガス/弗素又
は水素ガス)比が小さいときは、弗素又は水素によりシ
リコン薄膜基板中の不純物(A)が表面から減少される
櫟さに対して、新しい不純物(B)がドーピングされる
表面からの渫さは浅くなる。このため製造された原子は
pin接合素子となる。一方、(不純物(B)ガス/弗
素又は水素ガス)比が大きいと鎗は、弗素又は水素によ
り、クリコン薄膜基板中の不純物(A)が表面から減少
される深さと、新しい不純物(B)がドーピングされる
表面からの深さが、―ば同じとなる。このため製造され
た素子はpn接合素子となる。本発明の実mに際し好ま
しい混会ガス組威はB、H,、BP、/H。
In any of the above methods, the depth of reduction of impurities from the silicon thin film substrate and the degree of doping of other impurities can be controlled by changing the strength of the mixed gas, that is, the mixing ratio, and thereby the depth of doping of other impurities can be controlled as desired. It is possible to manufacture various pn junction devices with the performance of , and it is also possible to manufacture pin junction devices. To explain in more detail, in the manufacturing method according to the present invention, the composition of the mixed gas is an important parameter when carrying out the manufacturing method according to the present invention, together with the discharge pressure and time and the power density. Regarding the gas composition, when the ratio (impurity (B) gas/fluorine or hydrogen gas) is small, a new The depth from the surface to which the impurity (B) is doped becomes shallow. For this reason, the manufactured atoms become pin junction elements. On the other hand, if the ratio (impurity (B) gas/fluorine or hydrogen gas) is large, the depth at which the impurity (A) in the Crycon thin film substrate is reduced from the surface by fluorine or hydrogen, and the depth at which new impurity (B) is The depth from the surface to be doped is the same. Therefore, the manufactured device becomes a pn junction device. Preferred mixed gas compositions in the practice of the present invention are B, H, BP, /H.

又はPH,、PF、/乍、で10−1〜1O−1である
ことが分った。又諌混合ガスの真空容器内への流量はプ
ラズマ状態を安定に保つように設定されることが必要で
あり、0.5〜10081008CC好結果が得られた
Or, it was found that PH,, PF, /乍 is 10-1 to 1O-1. In addition, the flow rate of the mixed gas into the vacuum container must be set to keep the plasma state stable, and good results were obtained in the range of 0.5 to 10081008 CC.

本発明に係る製造方法を実際する際の重要なパラメータ
の一つである放電時圧力はi、 s x i o−”T
orr〜3Torrに制御されるのが好ましい。つまり
、放電時圧力が1.5 X 10 ”Torr以下であ
ると真空容器内の流れが拡散流となりシリコン薄膜基板
より放出された不純物が再びシリコン薄膜基板へと混入
する可能性が大となるために、真空容器内の流れを粘性
流とするべく放電時圧力は1.5X10−”Torr以
上であることが必要となる。父上隈としての放電時圧力
3Torrは、電極とアースシールドとの放電を防止す
るためであり、主k、装置因子によるものである。又放
電電力密度は使用されるプラズマガスの性質により変化
するが、0.5〜5 Q W/c−が適当である。この
ような条件下における放電時間は1秒〜5時間の間で種
々に変えることができる。又、放電電力密度と放電時間
との関41Kつ〜・て首えば、一般に放電電力密度は原
始添加不純物元素の減少深さ及び新たな不純物のドーピ
ング渫さに関与し、放電時間は原始添加不純物元素の減
少量及び新たな不純物のドーピング量に関与するという
ことができる。
The discharge pressure, which is one of the important parameters when actually implementing the manufacturing method according to the present invention, is i, s x i o-”T
It is preferable to control the pressure to between orr and 3 Torr. In other words, if the pressure during discharge is 1.5 x 10" Torr or less, the flow inside the vacuum container becomes a diffusion flow, and there is a high possibility that impurities released from the silicon thin film substrate will mix into the silicon thin film substrate again. In order to make the flow inside the vacuum container a viscous flow, the pressure during discharge must be 1.5×10 −” Torr or more. The pressure at the time of discharge of 3 Torr is to prevent discharge between the electrode and the earth shield, and is mainly due to equipment factors. Further, the discharge power density varies depending on the properties of the plasma gas used, but 0.5 to 5 Q W/c- is appropriate. The discharge time under such conditions can be varied between 1 second and 5 hours. In addition, the relationship between discharge power density and discharge time is generally related to the depth of reduction of the originally added impurity element and the doping depth of new impurities, and the discharge time is related to the depth of reduction of the originally added impurity element. It can be said that it is involved in the amount of element reduction and the amount of new impurity doping.

以上の説明で明らかなように1本発明の主たる目的は、
従来の製造方法に比べて少ない成膜工程にてpni[又
はpin IIのシリコン薄膜を製造することのできる
シリコン薄膜の製造方法を提供することである。
As is clear from the above explanation, the main purpose of the present invention is to
It is an object of the present invention to provide a method for manufacturing a silicon thin film that can manufacture a PNI [or PIN II] silicon thin film with fewer film forming steps than conventional manufacturing methods.

本発明の他の目的は、良好な光電気伝導度及び暗電気伝
導度を有し且つ光エネルギ変換効率の向上した太陽電池
、画像形成用光導電体、読取装置用光電変換素子又はダ
イオード等の作INK使用することのできるpnl[又
はpin IIシリコン薄膜の製造方法を提供すること
である。
Another object of the present invention is to provide solar cells, image forming photoconductors, photoelectric conversion elements or diodes for reading devices, etc., which have good photoelectric conductivity and dark electric conductivity and have improved light energy conversion efficiency. It is an object of the present invention to provide a method for manufacturing a PNL [or PIN II silicon thin film] that can be used for production INK.

本発明に係る製造方法においては、本発明に従って成膜
工程を施される原始シリコン薄膜基板としては、シリコ
ンの単結晶半導体、及びシラン(8iH,)にドーパン
トオスを混合したものを原料ガスとしプラズマ寥囲気下
にて任意の基板上に成膜された非晶質のシリ;ン半導体
等のpl[又はn型シリコン薄膜を使用することができ
るが、更に本出願人に係る特許出願(%願@55−14
3010号)K記載されるようなシリコン薄膜、即ち、
シラン8tH,またはハロゲン化シラン8tH,〜、X
4〜1(X:ハロゲン元素)のいずれか、またはその2
種以上の混合ガスを原料ガスとし、これにドーパントガ
スを混合し、成膜速度を十分に制御し結晶、非晶質混合
層を生成する目的で、前記混合ガスを、ヘリウム、ネオ
ン、アルゴン等の自ガスまたは水素等で約1対lより大
きい割合で希釈するとと−に、約0.2W/cs”以上
のグツズ−r放電電力密度の電力を投入しながら成膜さ
れたシリコン薄膜をも都合よく適用し得るものである。
In the manufacturing method according to the present invention, the original silicon thin film substrate to be subjected to the film forming process according to the present invention uses a silicon single crystal semiconductor and a mixture of silane (8iH, ) and a male dopant as the raw material gas and plasma plasma. Although it is possible to use a PL [or n-type silicon thin film such as an amorphous silicon semiconductor film formed on any substrate under a surrounding atmosphere, the present applicant's patent application (% application @55-14
No. 3010) A silicon thin film as described in K.
Silane 8tH, or halogenated silane 8tH, ~, X
Any one of 4 to 1 (X: halogen element), or 2
For the purpose of forming a crystalline or amorphous mixed layer by sufficiently controlling the film formation rate by mixing a dopant gas with a mixed gas of at least one species as a raw material gas, the mixed gas is mixed with helium, neon, argon, etc. When diluted with own gas or hydrogen at a ratio of more than about 1:1, a silicon thin film formed while applying power with a discharge power density of about 0.2 W/cs or more can also be used. It can be conveniently applied.

次に1本発明に係るシリコン薄膜の製造方法を実施例K
IAして説明する。
Next, a method for manufacturing a silicon thin film according to the present invention will be described in Example K.
IA and explain.

実施′例1 第1aiaicおいて、混合客器1を含めた全装置系を
油回転ポンプ2および油拡散ポンプ3を使って約10−
@Torrの真空にし、つffKyツ素lンべ4または
水素〆ンべ5、さらにドーパントガス(シボラン又はホ
スフィン)ボンベ6または7よりガスを混合容$IK所
要の割合で導入し、混合する。
Implementation Example 1 In the 1st aiaic, the entire equipment system including the mixing chamber 1 was operated using an oil rotary pump 2 and an oil diffusion pump 3 for about 10 minutes.
A vacuum of @Torr is created, and gases are introduced from the ffKy element tank 4 or hydrogen tank 5, and the dopant gas (ciborane or phosphine) cylinder 6 or 7 at the required ratio of the mixed volume $IK, and mixed.

混合されたガスは流量計8を通して真空客器9中に一庫
流量で導入される。メインパルプ10で操作して真空容
器9中の真空度を真空針11で監視しながら所要の圧力
に維持する。真空容器内の流れの状態は、基板膜中の放
出された不純物の再混入を防止するため、粘性流領域に
調整される。これは、主に真空容器内圧力を1.5 X
 10−” Torr以上KIIl持するととによって
実現できる。高周波発振器あるいは直流電源12で電極
13及び13′間に高周波電圧を印加してグレー放電を
発生させる。
The mixed gas is introduced into the vacuum chamber 9 through the flow meter 8 at a constant flow rate. The main pulp 10 is operated to maintain the required pressure while monitoring the degree of vacuum in the vacuum container 9 with the vacuum needle 11. The flow conditions within the vacuum vessel are adjusted to the viscous flow regime to prevent re-entrainment of released impurities in the substrate film. This mainly increases the pressure inside the vacuum vessel by 1.5
This can be realized by maintaining KIIl of 10-'' Torr or more.A high-frequency voltage is applied between electrodes 13 and 13' using a high-frequency oscillator or DC power supply 12 to generate gray discharge.

基板15としては、nil又はpallシリコン薄膜基
板を使用する。基板薄膜は0.1〜1声罵の範囲が好ま
しいが本実施例では0.7μ富とした。この基板15は
ヒーター14で加熱された基台上に載置され、ヒーター
で所要の温度に加熱される。以上の方法によりシリコン
薄膜基板15はpn接合素子又はpin接合素子となる
As the substrate 15, a nil or pall silicon thin film substrate is used. The thickness of the substrate thin film is preferably in the range of 0.1 to 1 μm, but in this example, the thickness was set to 0.7 μm. This substrate 15 is placed on a base heated by a heater 14, and heated to a required temperature by the heater. By the above method, the silicon thin film substrate 15 becomes a pn junction element or a pin junction element.

第1表に本発明による製造方法の実施例を示す。Table 1 shows examples of the manufacturing method according to the present invention.

使用したphiシリコン薄膜基板の成績条件は、81H
4: H,−1: 1の混合ガスを用い、ドーパントと
してジボランB、H,をS iH4に対して2−(体積
基準)混合したものを原料ガスとし【、プラズマ被電電
力密度Q、 I W/Cal’、酸膜圧力5 X 10
−”To r r s ji[料ガス流量15 BCC
M、成膜暗闘60分としたものであり、pI[シリコン
基板は■TO透明電極、hK上記実施例1に記載の成績
条件で製作されたものである。
The performance conditions of the phi silicon thin film substrate used were 81H.
A mixed gas of 4: H, -1: 1 was used, and a mixture of diborane B, H, and SiH4 as dopants was used as the raw material gas [, plasma applied power density Q, I W/Cal', acid film pressure 5 x 10
-”To r r s ji [Material gas flow rate 15 BCC
M, film formation time was 60 minutes, pI [silicon substrate was ■TO transparent electrode, hK was manufactured under the performance conditions described in Example 1 above.

第1表の試料ム1および轟2め素子は、V−i %性か
ら整流性が確認され、このことからpn接合素子が作製
されたことがわかった。
Rectification properties were confirmed from the V-i % properties of Samples M1 and Todoroki 2 elements in Table 1, and from this it was found that pn junction elements were fabricated.

更に試料42についてEMXII定及び加熱ガス放出実
験を行ない、その結果リン原子がp II S’ 9コ
ン薄膜中に4m[子囁含有していることが確認され、本
発明の製造方法によりリン原子がドーピングされている
ことがiE−された。
Furthermore, EMXII constant and heating gas release experiments were performed on sample 42, and the results confirmed that 4 m[2] of phosphorus atoms were contained in the p II S' 9 thin film. It was determined that it was doped.

1lll 試料番号      −1−−ヱー キャリャーガス      H,Ha ガス流量(8CCM)     5        5
電力密度(y/can” )      1.3   
    0.8基板温度(”C)       300
       300放電圧力(Torr)     
3X10”−”     3X10−”放電時間(分)
       60       30基板導電性タイ
プ      p         p第2WAは、本
発明に従った製造方法により作製された薄膜の電気伝導
度をプラズマ被電時間の関数として示すものである。た
だし、第2図に示されるシリコン薄膜は、本発明の製造
方法によりpmlI膜基板の表面からボーン原子量が減
少することを確■するためにグツズ−t gp Icホ
スフィ71スを混合していない条件により製造されて〜
・る、すなわち、第2WiAに示される試料の製造方法
&1、ボ闘ンドービンダp■シリツン薄膜を、水素流量
lo8CCM、放電時圧力ITorr、電力豐度0.8
W/aa” 、基板温度300℃、の下で水嵩プラズマ
放電することKよるものである。第2Eから、放電時間
とと−に電気伝導度が減少することがわかる。これは、
pl[シリコン薄膜表面から任意の欅さまで、メロン原
子量が減少するためである。
1lll Sample number -1--Carrier gas H, Ha Gas flow rate (8CCM) 5 5
Power density (y/can”) 1.3
0.8 Substrate temperature ("C) 300
300 discharge pressure (Torr)
3X10"-"3X10-"Discharge time (min)
60 30 Substrate conductivity type p pThe second WA shows the electrical conductivity of a thin film produced by the manufacturing method according to the invention as a function of plasma energization time. However, in order to ensure that the bone atomic weight is reduced from the surface of the pmlI film substrate by the manufacturing method of the present invention, the silicon thin film shown in FIG. Manufactured by ~
・That is, the manufacturing method of the sample shown in 2nd WiA & 1, the bombardment binder p silicon thin film, the hydrogen flow rate lo8CCM, the discharge pressure ITorr, the power intensity 0.8
W/aa'' and a substrate temperature of 300° C., it is due to the water bulk plasma discharge. From the 2nd E, it can be seen that the electrical conductivity decreases with the discharge time. This is because
pl [This is because the melon atomic weight decreases from the silicon thin film surface to an arbitrary Keyaki.

実施例2 実施例1と同様の方法にて、ボロンドープpHアモルフ
ァスシリコン薄膜基板(厚み5000λ)を■、ガスと
水素ガスの混合ガスのプラズマ雰囲気下で処通し、pi
n接金素子を作製した。#接合素子はV−1%性からp
inl!合素子であることが確認さ・れた。又、第38
11は81MBの瀾黛紬果を表わすものであるが、との
嬉3図からも、基板膜中のボーンが表面から35 O0
1の深さまで減少しており、混合ガス中のリンが新たに
ドーピングされていることが通解されるであろう。
Example 2 In the same manner as in Example 1, a boron-doped pH amorphous silicon thin film substrate (thickness 5000λ) was treated in a plasma atmosphere of a mixed gas of gas and hydrogen gas.
An n-type contact element was produced. # Junction element is p from V-1% property
inl! It was confirmed that it was a composite element. Also, the 38th
11 represents the 81 MB result, but from the figure 3, the bones in the substrate film are 35 O0 from the surface.
It will be understood that the phosphorus in the gas mixture is newly doped.

以上m1jjのように、本発明の製造方法によれば、p
alまたはnl[シリコン薄膜基板の表面から任意の深
さまで不純物量を減少させ、と同時に新たな不純物をと
の″シリコン薄膜中にドーピングすることができる。従
って、本発明の製造方法は成膜工程を従来の方法に比べ
減少させて、pnll*合素子又はpin If接合素
子を製造することができ製造工程を単純化し、シリコン
亭導体の生型性な増大せしめると共に、性能の良いダイ
オード、太陽電池勢を作ることができるといった効果を
有する。
As shown in m1jj above, according to the manufacturing method of the present invention, p
It is possible to reduce the amount of impurities from the surface of the silicon thin film substrate to an arbitrary depth and simultaneously dope new impurities into the silicon thin film. Therefore, the manufacturing method of the present invention It is possible to manufacture pnll* junction devices or pin if junction devices by reducing the It has the effect of creating momentum.

【図面の簡単な説明】[Brief explanation of drawings]

第i@1は本発明に係るシリコン薄膜製造方法を実施す
る装置を示す概略図である。 第2図は本実@に係る製造方法により作製されたシリコ
ン薄膜の電気伝導度をプラズマ放電時間の関数とし【示
すグツ7である。 第3図は本発明に係る製造方法により作製されたシリコ
ン薄膜のaIM8f)It定結果を示すグラフである。 l:混合容器 4.5.6.?:ガスlンペ 9:真空容器
The i@1 is a schematic diagram showing an apparatus for implementing the silicon thin film manufacturing method according to the present invention. FIG. 2 is a shoe 7 that shows the electrical conductivity of a silicon thin film produced by the manufacturing method according to the present invention as a function of plasma discharge time. FIG. 3 is a graph showing the aIM8f) It determination results of the silicon thin film manufactured by the manufacturing method according to the present invention. l: Mixing container 4.5.6. ? :Gas pump 9:Vacuum container

Claims (1)

【特許請求の範囲】 l)一つの不純物元素がドーピングされたシリコン薄膜
基板を弗素、塩素及び水素の群から選択された少なくと
も一元素のガスと、前記シリコン薄膜基板中の前記原始
添加不純物とは別種の不純物元素を含むガスとから成る
混合ガスのグツズ!雰囲気下に置き、それによって前記
シリコン薄膜基板の表面から所定の深さにわたって該シ
リコン薄膜基板中の原始添加不純物量を減少させると同
時にプラズマ中の新たな不純物を任意の深さまでドーピ
ングすることな特徴とするシリコン薄膜の製造方法。 2)混合ガスのプ2ズYw/L電時圧力を調整し容器内
の流れを粘性流領域とした特許請求の範1ijit項記
載の製造方法。 3)混合ガスのプラズマ放電時圧力は1.5 X 10
−’Torr〜3 Torrであることを特徴とする特
許請求の範囲第1項記載の製造方法。 匂 混合ガスの組成は一元素ガスに対する不純物元素ガ
スの割合を10−1〜1O−1の範囲で、且つ電力密度
を0.5〜50 W/3”の範囲で変えるととによって
原始添加不純物減少深さ及び新たな不純物のドーピング
深さを調整することを特徴とする特許請求の範囲第3項
記載の製造方法。 5)不純物量はシリコン薄膜基板の表面から最大s、o
oo、1の深さにわたって減少することを特徴とする特
許請求の範囲第4項記・載の製造方法。 6)シリコン薄膜基板は単結晶のシリコン半導体である
特許請求の範囲第1項記載の製造方法。 +7)シリコン薄膜基板は非晶質のシリコン半導体であ
る特許請求の範囲第1項記載の製造方法。 8)シリコン薄膜基板は非晶質層中に微結晶粒が混在し
ているシリコン半導体である特許請求の範8第1項記載
の製造方法。
[Claims] l) A silicon thin film substrate doped with one impurity element is treated with a gas of at least one element selected from the group of fluorine, chlorine, and hydrogen, and the original added impurity in the silicon thin film substrate is A mixed gas consisting of a gas containing another type of impurity element! The silicon thin film substrate is placed in an atmosphere, thereby reducing the amount of originally added impurities in the silicon thin film substrate to a predetermined depth from the surface of the silicon thin film substrate, and at the same time doping new impurities in plasma to an arbitrary depth. A method for manufacturing a silicon thin film. 2) A manufacturing method according to claim 1, in which the pressure of the mixed gas is adjusted so that the flow inside the container is in a viscous flow region. 3) The pressure during plasma discharge of mixed gas is 1.5 x 10
-'Torr to 3 Torr, the manufacturing method according to claim 1. The composition of the mixed gas can be determined by changing the ratio of impurity element gas to monoelement gas in the range of 10-1 to 1O-1 and the power density in the range of 0.5 to 50 W/3''. The manufacturing method according to claim 3, characterized in that the reduced depth and the doping depth of the new impurity are adjusted. 5) The amount of impurity is determined from the surface of the silicon thin film substrate to
5. The manufacturing method according to claim 4, characterized in that the depth decreases over a depth of oo, 1. 6) The manufacturing method according to claim 1, wherein the silicon thin film substrate is a single crystal silicon semiconductor. +7) The manufacturing method according to claim 1, wherein the silicon thin film substrate is an amorphous silicon semiconductor. 8) The manufacturing method according to claim 8, wherein the silicon thin film substrate is a silicon semiconductor in which microcrystalline grains are mixed in an amorphous layer.
JP56105704A 1981-07-08 1981-07-08 Manufacture of silicon thin-film Granted JPS589321A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56105704A JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film
US06/394,074 US4490208A (en) 1981-07-08 1982-07-01 Method of producing thin films of silicon
EP82303526A EP0069580B1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
DE8282303526T DE3276280D1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
US06/790,781 US4598304A (en) 1981-07-08 1985-10-23 Thin film devices of silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56105704A JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Publications (2)

Publication Number Publication Date
JPS589321A true JPS589321A (en) 1983-01-19
JPH0376019B2 JPH0376019B2 (en) 1991-12-04

Family

ID=14414741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56105704A Granted JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Country Status (1)

Country Link
JP (1) JPS589321A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0456170A (en) * 1990-06-21 1992-02-24 Fuji Electric Corp Res & Dev Ltd Manufacture of thin-film solar cell
JP2011001102A (en) * 2009-06-19 2011-01-06 Tomoku Co Ltd Packaging box

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55151374A (en) * 1979-05-14 1980-11-25 Shunpei Yamazaki Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55151374A (en) * 1979-05-14 1980-11-25 Shunpei Yamazaki Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0456170A (en) * 1990-06-21 1992-02-24 Fuji Electric Corp Res & Dev Ltd Manufacture of thin-film solar cell
JP2011001102A (en) * 2009-06-19 2011-01-06 Tomoku Co Ltd Packaging box

Also Published As

Publication number Publication date
JPH0376019B2 (en) 1991-12-04

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