JPS5890756A - Monolithic reference current source - Google Patents
Monolithic reference current sourceInfo
- Publication number
- JPS5890756A JPS5890756A JP19109381A JP19109381A JPS5890756A JP S5890756 A JPS5890756 A JP S5890756A JP 19109381 A JP19109381 A JP 19109381A JP 19109381 A JP19109381 A JP 19109381A JP S5890756 A JPS5890756 A JP S5890756A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- monolithic
- reference current
- series circuit
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
Description
【発明の詳細な説明】
この発明はモノリシック基準電流源に関するものである
。金属酸化物半導体（以下ＭＯ８と略称する）の大規模
集積回路ｃ以下Ｌ８工と略称する）上に集積化すること
のできる基準電流源としては特開昭５６−７１３１３号
公１１等で公知である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic reference current source. A reference current source that can be integrated on a metal oxide semiconductor (hereinafter abbreviated as MO8) large-scale integrated circuit C (hereinafter abbreviated as L8) is known from Japanese Patent Laid-Open No. 56-71313 No. 11, etc. be.
これは−イオン注入プロセスの追加によってしきいＩＥ
Ｉ：Ｅを２檎類つくると、そのしきい電圧の差は、コン
トロールが容易で温度依存性が小さく一定電圧になると
いうことを利用したものである。This - by the addition of an ion implantation process, the threshold IE
The difference in threshold voltage is easy to control, has little temperature dependence, and becomes a constant voltage when two types of I:E are made.
その−例を第１図に示す、同図において、（１）は電１
１１！ｌ戒圧’ＩＤＤが印加される端子−に接続された
モノリシック抵抗体−（２）はしきい−４ＥＥ ｖＴＨ
ＰｌをもっＰチャネルＭＯ＋３）ランジスタ、（３）は
しきい１Ｌ田ＶＴＨＰ２ （１ＶｘＩｉｐ１１ ＜ １
ＶＴｎｒ２１ ）をもつＰｆｆｆネＡ／ＭＯＳトランジ
スタ・（４）〜（６）はそれぞれしきいＩＩＥＥＶＴ□
をもつ腑チャネルＭＯ＆）ランジスタ、（７）は負荷で
ある。An example of this is shown in Figure 1. In the figure, (1) is
11! A monolithic resistor connected to the terminal to which the pressure 'IDD is applied - (2) is the threshold - 4EE vTH
P channel MO+3) transistor with Pl, (3) threshold 1L field VTHP2 (1VxIip11 < 1
PfffneA/MOS transistor with VTnr21) ・(4) to (6) are each threshold IIEEVT□
(7) is the load.
上記構成において、トランジスタ（４）、（５）の各ゲ
ートを共通に接続してカレント・ミラー回路を構成し、
トランジスタ（２）、（３）に流れる電流が等しくなる
ようにすると、トランジスタｆ２） 、 （！ｌ）の形
状Ｗ／Ｉ、（幡／長さ）が同じの場合、トランジスタ（
２）トトランジＸ タ（１９） ノ各しきイＩＩＥ ｆ
Ｅ ｖＴＨＰｌ 、 ’ｔｌｒｒａＰ２の差を抵抗体１
１）の抵抗値で割った値の電流が各トランジスタ（４）
、（５）に流れ、負荷（７）にはトランジスタ（６）ト
）ラングＸり（５）の形状比（Ｗ ／ Ｉ＋の比）倍の
゛電流が流れる。In the above configuration, the gates of transistors (4) and (5) are connected in common to form a current mirror circuit,
If the currents flowing through transistors (2) and (3) are made equal, if the shapes W/I and (length/length) of transistors f2) and (!l) are the same, transistor (
2) Totranji
E vTHPl, 'tlrraP2 difference is resistor 1
The current divided by the resistance value of 1) is the current for each transistor (4).
, (5), and a current that is twice the shape ratio (W/I+ ratio) of transistor (6) and rung (5) flows through load (7).
この際−モノリシック抵抗体（１）のキャリヤ密度が大
きいと、抵抗値の温度依存性は小ざ＜、シたかって、温
度依存性の小さい基準電流源が得られる。しかし、低消
費電力を要求されるＬ８工の場合は・基準電流源も、数
μＡ以下の低電流が必要となり、このためモノリシック
抵抗体（１）は数百にΩ以上の大抵抗値のものが必要と
なる。このような大きな抵抗値をチップ上で実現する際
には、パターン上の制約から、キャリヤ密度の小さい抵
抗を用いざるを得ないが、この場合、第２図のように抵
抗値の温度依存性が大きいために、第６図のように基準
電流の値も温度依存性が大きいという結果を生じていた
。In this case, if the carrier density of the monolithic resistor (1) is large, the temperature dependence of the resistance value will be small or strong, and a reference current source with small temperature dependence will be obtained. However, in the case of the L8 design, which requires low power consumption, the reference current source also requires a low current of several μA or less, so the monolithic resistor (1) has a large resistance value of several hundred ohms or more. Is required. When realizing such a large resistance value on a chip, it is necessary to use a resistor with a low carrier density due to pattern constraints, but in this case, the temperature dependence of the resistance value is As a result, as shown in FIG. 6, the value of the reference current also has a large temperature dependence.
この発明は上記従来の欠点を除去するためになされたも
ので一簡単な構成によりｆｊＡ度依存性の小さい低電流
のモノリシック基準電流源を容易に実現することを目的
としたものである。The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art, and it is an object of the present invention to easily realize a low-current monolithic reference current source with small fjA degree dependence using a simple configuration.
以下、この発明の一実施例を図面にしたがって説明する
。第４図はこの発明に係るモノリシック基準電源の一例
を示すもので、第１図と同一部所には同一符号を付して
説明を省略する。同図において、（８）はＰＭ接合ダイ
オードであシ、電源端子（至）とモノリシック抵抗体（
１）との間に介挿されている。An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows an example of a monolithic reference power supply according to the present invention, and the same parts as in FIG. In the same figure, (8) is a PM junction diode, and the power supply terminal (to) and the monolithic resistor (
1).
この構成において、トランジスタ（４）、（５）がカレ
ント・ミラー回路を構成しておシ、トランジスタ（２）
とトランジスタｉ８）のしきい電圧の差（ＩＴ１１１２
−ＶＴｉｉＰｌ ）に相当するｉｔ王がトランジスタ（
２）のソースとａ源端子−との藺に発生する。ｐｗ接合
ダイオード（８）の０１’戒圧（順方向型ＥＥ）の２！
！腐特性は・周知の通り負の温度係数をもっており、こ
れと第２１１１１に示す正の温度係数をもつ七ノリシッ
ク抵抗体（１）とを組み合わせることにより、温度係数
を打ち消して、湿度依存性の小さい基準電流源を得るこ
とができる。第５図はし古い１に王の差を１．０ｖモノ
リシック抵抗体（１）のｍ抗値ｔ−５５０にΩ（２０＠
０）としてた場合のモノリシック基準電流源の温Ｉｆ特
性である。In this configuration, transistors (4) and (5) constitute a current mirror circuit, and transistor (2)
and transistor i8) threshold voltage difference (IT1112
The IT king corresponding to the transistor (-VTiiPl) is the transistor (
2) occurs between the source and the a source terminal. 2 of 01' pressure (forward type EE) of pw junction diode (8)!
! As for corrosion characteristics, as is well known, it has a negative temperature coefficient, and by combining this with the seven-nolithic resistor (1) having a positive temperature coefficient as shown in No. 21111, the temperature coefficient is canceled out, resulting in a material with low humidity dependence. A reference current source can be obtained. FIG.
0) is the temperature If characteristic of the monolithic reference current source.
なお、上記接合ダイオード（８）を複数個接続してもよ
く、また、Ｎチャネルトランジスタ（３）、（４）のし
きい電圧を２檎傾つくってダイオード（８）と抵抗体（
１）の挿入位置を変更することもできる。Note that a plurality of the junction diodes (8) may be connected, or the threshold voltages of the N-channel transistors (3) and (4) may be increased by 2 degrees to connect the diode (8) and the resistor (
The insertion position of 1) can also be changed.
以上のように、この発明は、接合ダイオードとモノリシ
ック抵抗体とを、しきい電圧の異なるＭＯＳ）ランジス
タのソース側に直列接続することによって、′ＩＭ度依
存性を小さくすることができるモノリシック基準電ｆｉ
＃を大嵐模集積化容易にして得ることができる効果があ
る。As described above, the present invention provides a monolithic reference voltage that can reduce IM degree dependence by connecting a junction diode and a monolithic resistor in series to the source sides of MOS transistors having different threshold voltages. fi
There is an effect that can be obtained by easily integrating # into a big storm.
第１図は従来のモノリシック基準電流源を示す電気回路
図、第２図はモノリシック抵抗体の温度特性図、第６図
は従来のモノリシック基準電流源の温度特性図、第４図
はこの発明に係るモノリシック基準電流源の一例を示す
電気回路図、第５図はこの発明によるモノリシック基準
電流源の温度特性図である。
〔１〕・・・モノリシック抵抗体、（２）、（８）・・
・！チャネルＭＯ！３）ランジスタ、（４）〜（６）・
・・Ｎチ↑ネルＭＯＳトランジスタ、（γ）・・・負荷
、（８）・・・ｌ’Ｍ接合ダイオード、叫・・・’ｌ＃
。
なお、図中、同一符号は同一もしくは相当部分を示す。
第１図
十Ｖｐｐ
第２図
第３図
囁ｔ（τ）
第４図
＋ｈρ
第５図
、１ｊｌ（Ｃ）
手続補正書（自発）
特許庁長官殿
、 ｉｔ件の表示 特願昭 ５６−１９１０９
ｓ 号、発明の名称
毎ノリシック基準電流源
、補正をする各
６、補正の対象
明細書の「特許請求の範囲」および「発明の詳細な説明
」
６、補正の内容
ム、明細書墨
（１）特許請求の範囲の記載を別紙の通シ補正いたしま
す。
（！）第５頁第１３行目蓼
ｒｌ、ＱＶＪとあるをｒ １．ＯＶ、ｉ Ｊと補正いた
します。
以上
別 紙
補正後の特許請求の範囲
ｒ （１） 、電源と接地との間に第１導電形の第１の
トランジスタと、第２導電形の１ｇ２のトランジスタと
、モノリシック抵抗体とから成る第１の直列回路ならび
にｆＩｇ１導電形のｆ！Ｘ５のトランジスタと、第２導
電形の第４のトランジスタとから成る第２の直列回路と
をそれぞれ並列に接続し、第１のトランジスタと第３の
トランジスタあるいけ第２のトランジスタと第４のトラ
ンジスタのしきい電圧をそれぞれ第１および第２のしき
い電圧として異ならせ、上記第１のトランジスタのゲー
トと上記第３のトランジスタのゲートを共通接続すると
と４に一方の直列回路に属する上記第１もしくは第３の
トランジスタのドレインに接続し、上記第２のトランジ
スタのゲートと上記１ｇ４のトランジスタのゲートを共
１ｉＩＫ接続するとともに他方の直列回路に属する上記
第２もしくは第４のトランジスタのドレインに接続して
、さらに電源と接地との間に、ゲートが上記第２のトラ
ンジスタのゲートに接続され友、第２導電形の第５のト
ランジスタと負荷回路とから成る第５の直列回路を接続
し。Fig. 1 is an electric circuit diagram showing a conventional monolithic reference current source, Fig. 2 is a temperature characteristic diagram of a monolithic resistor, Fig. 6 is a temperature characteristic diagram of a conventional monolithic reference current source, and Fig. 4 is a diagram showing the temperature characteristics of a monolithic reference current source according to the present invention. An electric circuit diagram showing an example of such a monolithic reference current source, and FIG. 5 is a temperature characteristic diagram of the monolithic reference current source according to the present invention. [1]... Monolithic resistor, (2), (8)...
・! Channel MO! 3) Ransistor, (4) to (6)・
...N channel ↑ channel MOS transistor, (γ)...load, (8)...l'M junction diode, scream...'l#
. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 10 Vpp Figure 2 Figure 3 Whisper t (τ) Figure 4 + hρ Figure 5, 1jl (C) Procedural amendment (voluntary) Commissioner of the Japan Patent Office, Indication of IT Patent application No. 56-19109
No. s, Nolithic reference current source for each title of the invention, each item to be amended 6, "Claims" and "Detailed description of the invention" of the specification to be amended 6. Contents of the amendment, Description black (1) ) We will amend the description of the scope of patent claims in a separate document. (!) Page 5, line 13, 蓼rl, QVJ and r 1. We will correct it as OV, i J. Claim r(1) after amendment of the appendix: A first transistor between the power supply and the ground, which comprises a first transistor of the first conductivity type, a 1G2 transistor of the second conductivity type, and a monolithic resistor. 1 series circuit as well as f! of fIg1 conductivity type. A second series circuit consisting of a transistor of When the first and second transistors have different threshold voltages, and the gates of the first transistor and the third transistor are connected in common, the first transistor belonging to one series circuit Alternatively, it is connected to the drain of the third transistor, the gate of the second transistor and the gate of the 1g4 transistor are both connected in 1IK, and connected to the drain of the second or fourth transistor belonging to the other series circuit. Further, a fifth series circuit comprising a fifth transistor of the second conductivity type and a load circuit, the gate of which is connected to the gate of the second transistor, is further connected between the power supply and ground.
Claims (1)
ジスタと、第２導電形の第２のトランジスタと一モノリ
シック抵抗体とから成る第１の直列回路ならびに第１導
゛１形の第６のトランジスタと、第２導電形の第４のト
ランジスタとから成る第２の直列回路とをそれぞれ並列
に接続し、第１のトランジスタと第３のトランジスタあ
るいは第２のトランジスタと第４のトランジスタのしき
い電圧を第１および第２のしきい゛電圧として異ならせ
、上記′ｓ１のトランジスタのゲートと上記第６のトラ
ンジスタのゲートを共通接続するとともに一方の直列回
路に属する上記第１もしくは第６のトランジスタのドレ
インに接続し、上記第２のトランジスタのゲートと上記
第４のトランジスタのゲートを共通に＊ａするとともに
他方の直列回路に属する上記第２もしくは第４のトラン
ジスタのドレインに接続して、さらに電源と接地の間に
、ゲートが上記第２のトランジスタのゲー）＆：接続さ
れた、第２導電形の第５のトランジスタと負荷Ｌｇｌ賂
とから成る第６の直列回路を接続し、上記負荷回路に基
準電流を供給するものにおいて、上記第１のし古い電圧
の絶対値を上記第２のしきい電圧の絶対値より小さくし
、さらに上記第１の直列回路における第１もしくは第５
のトランジスタのソースに接合ダイオードを直列に接続
したことを特徴とするモノリシック基準電流源。(1) A first series circuit consisting of a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a monolithic resistor between 1t# and ground; A second series circuit consisting of a sixth transistor of the same conductivity type and a fourth transistor of the second conductivity type are connected in parallel, and the first transistor and the third transistor or the second transistor and the fourth transistor are connected in parallel. The first and second transistors have different threshold voltages, the gates of the transistor 's1 and the sixth transistor are commonly connected, and the first transistor belonging to one series circuit is Alternatively, it is connected to the drain of the sixth transistor, the gate of the second transistor and the gate of the fourth transistor are connected in common *a, and the drain of the second or fourth transistor belonging to the other series circuit is connected. and further between the power supply and ground, a sixth series circuit consisting of a fifth transistor of the second conductivity type and a load Lgl, the gate of which is connected to the gate of the second transistor. and supplying a reference current to the load circuit, wherein the absolute value of the first threshold voltage is smaller than the absolute value of the second threshold voltage, and the first threshold voltage in the first series circuit is Or the fifth
A monolithic reference current source characterized by a junction diode connected in series to the source of a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19109381A JPS5890756A (en) | 1981-11-25 | 1981-11-25 | Monolithic reference current source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19109381A JPS5890756A (en) | 1981-11-25 | 1981-11-25 | Monolithic reference current source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5890756A true JPS5890756A (en) | 1983-05-30 |
Family
ID=16268730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19109381A Pending JPS5890756A (en) | 1981-11-25 | 1981-11-25 | Monolithic reference current source |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5890756A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002246685A (en) * | 2001-02-16 | 2002-08-30 | Canon Inc | Driving circuit for light emitting element |
| JP2010171755A (en) * | 2009-01-23 | 2010-08-05 | Sony Corp | BIAS CIRCUIT, gm-C FILTER CIRCUIT WITH THE SAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP2011082825A (en) * | 2009-10-07 | 2011-04-21 | Asahi Kasei Electronics Co Ltd | Filter circuit |
| JP2012119835A (en) * | 2010-11-30 | 2012-06-21 | Asahi Kasei Electronics Co Ltd | Active filter |
| CN112099563A (en) * | 2020-11-17 | 2020-12-18 | 四川科道芯国智能技术股份有限公司 | Low-power-consumption CMOS current source circuit for NFC chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253681A (en) * | 1975-10-28 | 1977-04-30 | Matsushita Electric Works Ltd | Temperature correction circuit for resistors |
-
1981
- 1981-11-25 JP JP19109381A patent/JPS5890756A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253681A (en) * | 1975-10-28 | 1977-04-30 | Matsushita Electric Works Ltd | Temperature correction circuit for resistors |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002246685A (en) * | 2001-02-16 | 2002-08-30 | Canon Inc | Driving circuit for light emitting element |
| JP2010171755A (en) * | 2009-01-23 | 2010-08-05 | Sony Corp | BIAS CIRCUIT, gm-C FILTER CIRCUIT WITH THE SAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP4670969B2 (en) * | 2009-01-23 | 2011-04-13 | ソニー株式会社 | Bias circuit, gm-C filter circuit having the same, and semiconductor integrated circuit |
| JP2011082825A (en) * | 2009-10-07 | 2011-04-21 | Asahi Kasei Electronics Co Ltd | Filter circuit |
| JP2012119835A (en) * | 2010-11-30 | 2012-06-21 | Asahi Kasei Electronics Co Ltd | Active filter |
| CN112099563A (en) * | 2020-11-17 | 2020-12-18 | 四川科道芯国智能技术股份有限公司 | Low-power-consumption CMOS current source circuit for NFC chip |
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