JPS5890201A - Triple process input and output device - Google Patents

Abstract

PURPOSE:To improve the reliability, by providing a signal receiving/processing part to each triple device to check the soundness of the signal which is received from a central computer and setting the output to be fed to a majority circuit at an extreme value when the signal is faulty. CONSTITUTION:A central computer 1 is connected to transmission/reception processors 3a-3c via a bus 2 and couplers 22a-22c. The relay contacts 5a- 5c are connected to a processor 7 via an analog majority logic 6. The signal 11 detected through the processor 7 is fed to the processors 3a-3c respectively. These signals are processed by a command of an arithmetic processor 31 and then fed to the computer 1 via a transmission control unit 32. The signal sent from the computer 1 is fed to a memory 33 under the control of the processor 31 via the unit 32 and at the same time receives a D/A conversion 35 to be fed to the logic 6 through the contact 5a. The signal of the converter 35 receives an A/D conversion 34 again and is compared with the contents of the memory 33. If a discordance is detected through a self-diagnosing unit 37, a relay 4a is driven by a fault processing unit 38 to break the contact 5a.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a triple system process input/output device, and in particular to a single-atom couplant or the like having a function of outputting control signals digitally multiplexed from a central computer to a process with high reliability. The present invention relates to a suitable input/output device for a three-dimensional thread process.

Process systems that require high confidence such as atomic couplants@
In the l-thread, signals digitally transmitted from the central computer are received by triplexed input/output devices for one output, and the most probable one of the received signals is selected by majority logic and processed. There is a known method of outputting to .

FIG. 1 shows an example of such a conventional process personnel dispatching device, in which a signal from a central computer is converted into an analog signal and given as a target signal IO. This fHHIO2
The signals are input to operational amplifier circuits Ba, Bb and 8C having the same structure and output as VI, Vt and V3, which are input to an analog majority logic circuit 6. This circuit 6 has an input V0. One of the most probable signals among V2 and ■ is output to the open side 1 target 9 to control it.

Here, the analog operational amplifier circuits 8a, 8b, and 8C are connected in a feedback loop, and the controlled object 9
A signal detecting the state of is fed back to each arithmetic amplifier circuit f3a, 8b and f3cm\ via conductor IvlII+91.

The operation of the majority logic circuit 6 is, for example, V, >V.

〉■, then the negative bias power supply 65 is connected to the resistor 6
4a, 64b, and 64C, the voltage on the conductor 66a is Vl, since the diode 618 is on and the diode 628 is off because V, >V. Similarly, the voltage I on conductor 66b
The voltage on the conductor 66C is V, which is the smaller of V and v3. Therefore, the diodes 63a, 63b, 63Cfd
: These conducting wires 66a.

The smallest voltage among the voltages 66b and 66C, ie, V2 in the above example, is selected and output.

This is the same even when V + > V 2 > V s, and a signal in the middle is always selected as the most probable signal. That is, 1, for example, an operational amplifier circuit 8a.

Either Bb or Bc becomes VI +L after 1 hour of acid
Even if one of the values of +V becomes a completely extreme value, as long as the other two values are normal, the majority logic circuit 6 eliminates this abnormality +ii1 and outputs a normal value. be.

However, this conventional device has a common part that receives a digitally transmitted signal and obtains the target signal source 10 by D/A conversion (digital-to-analog conversion), etc., and is susceptible to malfunction or failure of this part. could not be addressed, and there were problems with reliability.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide a more reliable triple-tube process input/output device.

In the present invention, a reception processing section is provided for each device in a triplexed device, and the soundness of the signal received from the central control unit 'X' is checked by each reception processing section, and if there is an abnormality, The present invention is characterized in that by setting the output to the majority logic circuit to an extreme value, the output of the reception processing section is not selected by the majority logic.

The present invention will be explained in detail below using examples.

FIG. 2 is a schematic configuration diagram showing an embodiment of the device of the present invention, in which the central computer 1 includes a bus coupler 21, a data bus 2. It is coupled to the triplex process input/output devices via bus couplers 22a, 22b, and 22C.

The device of the present invention includes transmission and reception processing units 3a and 3b.

3c, it consists of relay coils 4a, 4b, 4C, their normally closed contacts 5a+ 5b+ 50, and a majority logic circuit 6. In FIG. 2, only one system of the device of the present invention is shown. . Therefore, in reality, a plurality of similar devices are generally connected to the data bus 2, but this is omitted.

In the configuration shown in FIG. 2, the signal 11 detected from the process 7 is input to the transmission/reception processing units 3a, 3b, and 3C, and after signal processing, the transmission control within the transmission/reception processing unit is performed according to instructions from the central computer 1. The data is serially multiplexed from the central computer 1 and transmitted to the central computer 1. The signal received by the central WF calculator 1 is subjected to each product calculation process, and then serially multiplexed and sent out as a control signal, received by the transmission control section of each transmission/reception processing section, converted into a parallel signal, and further After undergoing D/A conversion processing, relay contacts 5a, 5b and 5C'
It is input to the analog majority logic 6 via r. Here, in the transmission/reception processing units 3a, 3b, and 3C, the soundness of the output signal to the process and the soundness of each 4'*m function are determined,
If there is an abnormality, please check the relay coils 4a, 4b or V.
Breaking relay contact 5a, 5b6 or 5C by i4C causes the input to analog majority logic 6 to be an extreme value and prevent it from being output to the process.

However, in this case, it is assumed that the control signal converted into an analog signal and outputted to the process is unipolar, and has a certain level of magnitude as a normal value, rather than a value of zero or a value close to zero.

FIG. 3 shows an example of the configuration of the transmission/reception processing unit 3a (others have the same configuration), which is a feature of the present invention and is used to perform the above-mentioned operations.
I unit 32, memory 33. AI Units) 34. A.O.
Unit 35, buffer 36. self-diagnosis unit 37,
It consists of an abnormality processing unit 38.

Central total J! 'Transmission and reception of signals with machine 1 is performed by arithmetic processing unit 3.
This is carried out in the transmission open side 1 unit 32 according to the command of 1.

The transmission signal from the central computer 1 is received by the transmission control MLJ unit 32, and stored in the memory 33 under the control of the arithmetic processing unit 31.

The signal is D/A converted by the AO unit 35 and inputted to the analog majority logic 6 through the buffer 36 and the relay contact 5a.

On the other hand, the analog output signal from the AO unit 35 is A/D converted by the υAI unit 34 under the control of the arithmetic processing unit 31 and returned to a digital signal. - compared with Q. If there is a discrepancy here, this is detected by the self-diagnostic analysis unit 37, and the relay coil 4a is driven through the entire abnormality processing unit 38, and the relay contact 5a is disconnected.

-2 The self-diagnosis unit 37 monitors the functional operation of each unit, and instructs a colleague to turn off the relay contact 5a if an abnormality is detected.

Furthermore, the data stored in the corresponding memories 33 in the three transmission/reception processing units 3a, 3b, and 3c are as follows.

Under the control of the arithmetic processing unit 31 in each device, the bus couplers 22a, 22b, 22C, and the data bus 2 are checked, and the data L stored in the own device and the data in the other two devices are checked. If there is a mismatch, similar processing is performed.

In this way, each transmission/reception processing unit 3a, 3b, 3c constantly checks the soundness of the output signal to the process and the soundness of various functions, and if there is an abnormality, the input voltage to the analog majority logic 6 is changed. Let's go. Therefore, if the inputs to the other two analog majority logics 6 are normal (normal values are defined as absolute values not near zero in this embodiment),
Of the three manual inputs, the voltage of the two normal shifts with the smaller absolute value is output to the process 7 as the most probable signal, making it possible to perform the process system 011 with extremely high reliability.

In addition, in one or more embodiments, when an abnormality is detected, the output to the majority logic circuit is set to zero by turning off the relay contact, but this outputs a voltage that is outside the range of normal control signals. It is obvious that various means other than relays can be used.

Further, although the data bus connection between the central computer and the process input/output device is configured in a loop configuration, it may be in any other bus configuration such as star or multi-drop.

Furthermore, the control output in most process controls is an analog signal, but when outputting a digital signal (), either a or low signal) f: to a process (9), the implementation shown in Figure 3 can be used. In the example, both the AI unit 34 and the AO unit 35 are flip-flops. In this case, the high-level and low-level signals are reliably distinguished by the three-way line, and is one of the cases to which the present invention is applicable.

As is clear from the above description, the present invention has the effect that the output control signal from the central computer in the digital process control system can be output to the process with extremely high reliability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional triple system process input/output device, Fig. 2 is an overall block diagram showing an embodiment of the present invention, and Fig. 3 is a diagram showing details a of the embodiment of Fig. 2. . 1... Central computer, 3a, 3b, 3c... Transmission/reception processing unit, 4a, 4b, 4cm relay coil,
5a. 5b, 5c... Relay contact, 6... Analog majority logic circuit, 7... Process, 31... Arithmetic processing unit, 32... Transmission control unit, 33... Memory,
34...AI unit, 35...AO unit, 36
... Pan (10) Fa, 37 ... Self-diagnosis unit, 38 ... Abnormality processing unit. Agent: Patent attorney Masami Akimoto (11)

Claims (1)

[Claims] ■. Sending process data from the process end to the central computer and receiving digital control signals from the central computer? There are three transmission/reception processing sections that have the function of converting the received signal into a supply signal to be supplied to the process end and outputting it, and one intermediate shift of the three outputs of each transmission/reception processing section is selected and sent to the process end. and an analog majority logic circuit for outputting the signal to the central computer, and each of the transmission/reception processing sections includes a first means for inversely converting the supplied signal into a digital signal and comparing it with a digital control signal from the central computer; A second means for detecting as an abnormality when a discrepancy occurs as a result of the comparison or when another abnormality occurs in the own processing unit, and a second means for detecting the above-mentioned supplied signal as an abnormality when the abnormality is detected. a third means for forcibly setting the value of , thereby preventing the analog majority logic circuit from selecting a signal supplied from its own processing section. 2. When the range of normal values of the supply signal is only positive or negative, the third means is configured by a relay that is turned off when the second means detects an abnormality. A triple system process input/output device according to claim 1.