JPS5888908A - Protective device for transistor - Google Patents

Protective device for transistor

Info

Publication number
JPS5888908A
JPS5888908A JP56187247A JP18724781A JPS5888908A JP S5888908 A JPS5888908 A JP S5888908A JP 56187247 A JP56187247 A JP 56187247A JP 18724781 A JP18724781 A JP 18724781A JP S5888908 A JPS5888908 A JP S5888908A
Authority
JP
Japan
Prior art keywords
transistor
current
collector
emitter
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56187247A
Other languages
Japanese (ja)
Inventor
Hideo Iwamoto
岩本 英雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56187247A priority Critical patent/JPS5888908A/en
Publication of JPS5888908A publication Critical patent/JPS5888908A/en
Pending legal-status Critical Current

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Landscapes

  • Electronic Switches (AREA)
  • Amplifiers (AREA)
  • Protection Of Static Devices (AREA)

Abstract

PURPOSE:To realize the protection simply and inexpensively, by short-circuiting the base and emitter of a transistor (TR), when a voltage between the collector and emitter reaches a prescribed value or over. CONSTITUTION:If a load 11 is short-circuited and an overcurrent flows to a TR1, the collector current of the TR1 is increased and a collector-to-emitter voltage is increased at the same time. Thus, the base current of a TR2 is increased and the TR2 is turned on. After a specified delay time with a saturable reactor 3, a collector current flows to the TR2, a current from an emitter of a TR7 becomes the collector current of the TR2 to protect the TR1 by interrupting the base current of the TR1 and turning off the TR1.

Description

【発明の詳細な説明】 この発明はトランジスタを過電流から保護する保護装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection device that protects a transistor from overcurrent.

従来この種の保護装置に用いる過電流検出装置は保護の
対象とするトランジスタのコレクタ又はエミッタに直列
に接続された。そして過電流が検出されるとペース制御
回路により当該トランジスタのペース電流をしゃ断しそ
れによってコレクタ電流をしゃ断していた。
Conventionally, an overcurrent detection device used in this type of protection device is connected in series to the collector or emitter of a transistor to be protected. When an overcurrent is detected, the pace control circuit cuts off the pace current of the relevant transistor, thereby cutting off the collector current.

しかし、このような従来の装置において電流検出装置と
して変流器を用いる場合変流器が大形かつ高価になり、
抵抗による電圧降下を用いる場合は抵抗での電力損失が
大きいことと回路構成が複雑となり、かつコスト高にな
るという欠点があった。
However, when a current transformer is used as a current detection device in such a conventional device, the current transformer is large and expensive.
When using a voltage drop caused by a resistor, there are drawbacks such as large power loss in the resistor, complicated circuit configuration, and high cost.

この発明は従来の装置における上述の欠点を除去するた
めになされたもので、小形で安価なトランジスタの保護
装置を提供することを目的としている。
The present invention has been made to eliminate the above-mentioned drawbacks of conventional devices, and an object of the present invention is to provide a small and inexpensive transistor protection device.

以下図面によシこの発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

オ1図はこの発明の一実施例を示す接続図であって、図
において(1)は保護の対象とするトランジスタ、+2
1t!スイツチ用トランジスタ、(3)は可飽和リアク
トル、(4) e (5) e te+はそれぞれ抵抗
、(71II2制御用トランジスタ、+81 Fi制御
装置、 19+ 、 filはそれぞれ電源、αυは負
荷である。
Figure 1 is a connection diagram showing one embodiment of the present invention, in which (1) is the transistor to be protected, +2
1t! The switch transistor, (3) is a saturable reactor, (4) e (5) e te+ are each a resistor, (71II2 control transistor, +81 Fi control device, 19+ and fil are each a power supply, and αυ is a load.

また第2図tiオ1図の各部の波形を表す波形図で、横
軸は時間を示し、第2図(a)Fi)ランジスタ(7)
のコレクタ電流、同図(b)はトランジスタ(1)のベ
ース電流、同図(C)はトランジスタ(1)のコレクタ
電流、同図(d)H)ランジスタ(1)のコレクタ、エ
ミッタ間電圧、同図(e)はトランジスタ(2)のベー
ス電流、同図(f)はトランジスタ12+のコレクタ電
流を示す。
In addition, Fig. 2 is a waveform diagram showing the waveforms of each part in Fig. 1, the horizontal axis indicates time, and Fig. 2 (a) Fi) transistor (7).
(b) is the base current of transistor (1), (C) is the collector current of transistor (1), (d) is the collector-to-emitter voltage of transistor (1), FIG. 5(e) shows the base current of transistor (2), and FIG. 2(f) shows the collector current of transistor 12+.

次に第2図を用いて第1図の回路の動作を説明する。第
2図のt1時点以前においてはトランジスタ(7)はオ
フ状態にありしたがってトランジスタ(11のベース電
流が流れずトランジスタ(1)モオフ状態にある。その
ときトランジスタ(11のコレクタ、エミッタ間電圧は
電源a〔の電圧に等しくなっており、この電圧が抵抗1
41 、151で分圧されてトランジスタ(2)のベー
スに加えられトランジスタ(2)のベース電流は第2図
(e)に示すとおりになっている。しかしトランジスタ
(7)がオフ状態にあるからトランジスタ(2)のコレ
クタ電流(第2図(f))は流れていない。
Next, the operation of the circuit shown in FIG. 1 will be explained using FIG. 2. Before time t1 in FIG. 2, the transistor (7) is in the off state, so the base current of the transistor (11) does not flow and the transistor (1) is in the off state. At that time, the voltage between the collector and emitter of the transistor (11) is It is equal to the voltage of a[, and this voltage is equal to the voltage of resistor 1
The voltage is divided by 41 and 151 and applied to the base of transistor (2), and the base current of transistor (2) is as shown in FIG. 2(e). However, since the transistor (7) is in the off state, the collector current of the transistor (2) (FIG. 2(f)) does not flow.

次に、第2図の魁時点で制御装置(81からトランジス
タ(7)にベース電流が供給される。このためトランジ
スタTRI i′iターンオンし第2図(a)に示すコ
レクタ電流が流れる。このコレクタ電流はすべてトラン
ジスタ(1)のベース電流(第2図(b) )となって
流れ可飽和リアクトル(3)の方へは分岐しない。それ
は可飽和リアクトル(3)の電流遅延効果によるもので
ある。このためトランジスタ(1)はターンオンし第2
図(e)に示すコレクタ電流が電源叫→負荷αυ→トラ
ンジスタ(1)のコレクタートランジスタ(1)のエミ
ッタと流れ負荷αυによる電圧降下のためトランジスタ
(1)のコレクタ、エミッタ間電圧はほとんどOとなり
(第2図(d) ) )ランジスタ12)がカットオフ
される(第2図(e) 、 (f)参照)。このように
、トランジスタ(1)が定常のオン状態では可飽和リア
クトル(3)とスイッチ用トランジスタ(2)の直列回
路はトランジスタ(1)のベース電流制御には何等の影
411を及はさない。
Next, at the point in time in FIG. 2, a base current is supplied from the control device (81) to the transistor (7). Therefore, the transistor TRI i'i is turned on and the collector current shown in FIG. 2(a) flows. All of the collector current becomes the base current of the transistor (1) (Fig. 2 (b)) and does not branch to the saturable reactor (3). This is due to the current delay effect of the saturable reactor (3). Therefore, transistor (1) turns on and the second
The collector current shown in Figure (e) is from the power source → load αυ → collector of transistor (1). Because of the voltage drop due to the emitter of transistor (1) and current load αυ, the voltage between the collector and emitter of transistor (1) becomes almost O. (FIG. 2(d))) The transistor 12) is cut off (see FIG. 2(e) and (f)). In this way, when the transistor (1) is in a steady on state, the series circuit of the saturable reactor (3) and the switching transistor (2) does not have any influence 411 on the base current control of the transistor (1). .

次に、t3時点において負荷αυが短絡した為トランジ
スタ+11に過電流が流れるとする。トランジスタ(1
1のコレクタ電流(第2図(C))が増加し、同時にそ
のコレクタ、エミッタ間電圧(第2図(d))が増加す
る。したがってトランジスタ(2)のベース電流(第2
図(e))が増加しトランジスタ(2)ハターンオンす
る。可飽和リアクトル(31による所定の遅延時間の後
t1時点においてトランジスタ(21のコレクタ電流(
第2図(f))が流れトランジスタ(7)のエミッタか
らの電流はトランジスタ(2)のコレクタ電流となりト
ランジスタ(1)のベース電流をしゃ断しトランジスタ
(11をターンオフしてトランジスタ(11を保^する
Next, suppose that an overcurrent flows through the transistor +11 because the load αυ is short-circuited at time t3. Transistor (1
1's collector current (FIG. 2(C)) increases, and at the same time, its collector-emitter voltage (FIG. 2(d)) increases. Therefore, the base current of transistor (2) (second
(e)) increases and transistor (2) turns on. At time t1 after a predetermined delay time due to the saturable reactor (31), the collector current of the transistor (21 (
Figure 2 (f)) flows, and the current from the emitter of transistor (7) becomes the collector current of transistor (2), cuts off the base current of transistor (1), turns off transistor (11), and maintains transistor (11). do.

第3図はこの発明の他の実施例を示す接続図で第1図と
同一符号は同一または相当部分を示し、第3図に示す実
施例ではスイッチ用トランジスタ(2)と可飽和リアク
トル(3)との直列回路はトランジスタ(7)のベース
、エミッタ間を短絡することによりトランジスタ(1;
のベース電流をしゃ断しているが、其他の動作は第1図
の場合と同様であるので重複した説明は省略する。
FIG. 3 is a connection diagram showing another embodiment of the present invention. The same reference numerals as in FIG. 1 indicate the same or corresponding parts. In the embodiment shown in FIG. ) by shorting the base and emitter of transistor (7).
The base current is cut off, but the other operations are the same as in the case of FIG. 1, so redundant explanation will be omitted.

また上述の実施例でスイッチ用トランジスタ(21を用
いたところは、トランジスタに限定されずサイリスタ、
G T O(gate turn−off zl*yr
istor)、F E T (field effec
t transistor )等一般のスイッチ装置を
用いればよく、ま次回飽和リアクトル(31を用いたと
ころは、可飽和リアクトルに限定されず普通のりアクド
ル等一般に電流遅延装置を用いればよいことは明らかで
ある。
In addition, in the above embodiment, the switching transistor (21) is not limited to a transistor, but may be a thyristor,
G T O (gate turn-off zl*yr
istor), FET (field effect)
It is clear that a general switching device such as a ttransistor may be used, and the use of a saturable reactor (31) is not limited to a saturable reactor, but a general current delay device such as an ordinary glue reactor may be used.

以上のようにこの発明によれば回路構成が簡単で小形か
つ安価に製造できるトランジスタの保獲装置が得られる
As described above, according to the present invention, it is possible to obtain a transistor storage device that has a simple circuit configuration, is small in size, and can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す接続図、第2図はオ
五図の回路の各部の波形を示す波形図、第3図はこの発
明の他の実施例を示す接続図である。 ill・・・保護の対象とするトランジスタ、+21・
・・スイッチ用トランジスタ、(3)・・・可飽和リア
クトル。 なお、図中同一符号は同−又は相当部分を示す。 代理人 葛 野 信 − 第2図 (a) 第3図
Fig. 1 is a connection diagram showing one embodiment of this invention, Fig. 2 is a waveform diagram showing waveforms of each part of the circuit in Fig. 5, and Fig. 3 is a connection diagram showing another embodiment of this invention. . ill...Transistor to be protected, +21.
...Switch transistor, (3)...Saturable reactor. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 2 (a) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 保護の対象とするトランジスタのコレクタ、エミッタ間
電圧を測定する手段と、上記コレクタ、エミッタ間電圧
が所定値以上に達した時オン状態となるスイッチ装置と
、このスイッチ装置に直列に電流遅延装置を接続した回
路により上記保護の対象とするトランジスタのペース、
エミッタ間電圧を上記スイッチ装置がオン状態にある期
間だけ短絡する手段とを備えたトランジスタの保護装置
A means for measuring the voltage between the collector and emitter of the transistor to be protected, a switch device that turns on when the voltage between the collector and emitter reaches a predetermined value or more, and a current delay device connected in series with the switch device. The pace of the transistor that is subject to the above protection depending on the connected circuit,
A protection device for a transistor, comprising: means for short-circuiting a voltage between emitters only during a period when the switch device is in an on state.
JP56187247A 1981-11-20 1981-11-20 Protective device for transistor Pending JPS5888908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56187247A JPS5888908A (en) 1981-11-20 1981-11-20 Protective device for transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56187247A JPS5888908A (en) 1981-11-20 1981-11-20 Protective device for transistor

Publications (1)

Publication Number Publication Date
JPS5888908A true JPS5888908A (en) 1983-05-27

Family

ID=16202618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56187247A Pending JPS5888908A (en) 1981-11-20 1981-11-20 Protective device for transistor

Country Status (1)

Country Link
JP (1) JPS5888908A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5551072U (en) * 1978-09-29 1980-04-03

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5551072U (en) * 1978-09-29 1980-04-03

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