JPS5886754A - Lead pin for integrated circuit device - Google Patents
Lead pin for integrated circuit deviceInfo
- Publication number
- JPS5886754A JPS5886754A JP56185790A JP18579081A JPS5886754A JP S5886754 A JPS5886754 A JP S5886754A JP 56185790 A JP56185790 A JP 56185790A JP 18579081 A JP18579081 A JP 18579081A JP S5886754 A JPS5886754 A JP S5886754A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead pin
- pin
- lead
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 229910052737 gold Inorganic materials 0.000 claims abstract description 11
- 239000010931 gold Substances 0.000 claims abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000919 ceramic Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005219 brazing Methods 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000003466 welding Methods 0.000 abstract description 3
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000009864 tensile test Methods 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- DMFGNRRURHSENX-UHFFFAOYSA-N beryllium copper Chemical compound [Be].[Cu] DMFGNRRURHSENX-UHFFFAOYSA-N 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1031—Surface mounted metallic connector elements
- H05K2201/10318—Surface mounted metallic pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、集積回路装置用リードピン（以下型）にリー
ドピンと称す）の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in lead pins (hereinafter referred to as lead pins) for integrated circuit devices.
従来、メタライズしたセラミック基板にリードピンをろ
う付けするには、第１図ａ、 ｂ、 ｃ、に示す如
くリードピンｌ及び金ろう２を、夫々ｆ４２図ａ、
ｂ、 む、に示ず如くセラミック基板３にセットして
ろう付けしていた。しかしながら、ろうの濡れ不１・分
によるろう付は不良が生ずる欠点があった。Conventionally, in order to braze lead pins to a metallized ceramic substrate, the lead pins 1 and the gold solder 2 are soldered as shown in Figures 1a, b, and c, respectively.
b. It was set on the ceramic substrate 3 and brazed as shown in . However, brazing due to insufficient wetting of the solder for 1 minute has the drawback of causing defects.
本発明名は、−ト記欠点を解消せんがために鋭意攻究の
結果、ろう付は不良の原因は、コバール。The name of the present invention is - As a result of intensive research to eliminate the drawbacks mentioned above, Kovar was found to be the cause of poor brazing.
鉄−ニソケル合金、ベリリウム−銅合金等から成るリー
ドピンｌの保管中にできる酸化皮膜にあることを見いだ
したのである。They discovered that the problem lies in the oxide film formed during storage of lead pins made of iron-nisokel alloy, beryllium-copper alloy, etc.
本発明は、かかる不良の原因を解消し、長期保管にも耐
える得るリードピンを提供せんとするものである。The present invention aims to eliminate the causes of such defects and provide a lead pin that can withstand long-term storage.
本発明は、第３図ａに示す如くリードピン１の少なくと
もろう付は面１ａ又はフィレットを形成する部分１ｂに
予め金ろう２をタイトに取付けたことを特徴とするもの
である
本発明に於いて、リードピンｌの少なくともろう材面１
ａ又はフィレットを形成する部分１ｂに予め余ろう２を
タイトに取付ける理由は、保管中にろう付けする部分の
酸化を余ろう２によって防止するためである。The present invention is characterized in that a gold solder 2 is tightly attached in advance to at least the brazing surface 1a or the fillet-forming portion 1b of the lead pin 1, as shown in FIG. 3a. , at least the filler metal surface 1 of the lead pin l
The reason why the surplus solder 2 is tightly attached in advance to the portion 1b forming the fillet is to prevent the portion to be brazed from being oxidized during storage.
本発明の効果を一層明瞭ならしめるために実施例及び従
来例について述べる。In order to make the effects of the present invention clearer, embodiments and conventional examples will be described.
第３図ａに示す如く直径０．４５鶴、長さ８寵の鉄−ニ
ッケル合金より成るリードピン１のろう付は面１ａに厚
さ０．０５鶴のＡｕ３３．３％−Ａｇ４４．５−Ｃｕ２
２．２％合金より成る金ろう２をスパッタリングによっ
て取付けたリードピンをポリエチレンの袋に入れて３ケ
月間保管した後、第３図すに示す如くメ多ライズしたセ
ラミック基板３上に１０００本セットしてろう付けし、
それを引張試験したところ、４．５ｋｇ〜６．０ｋｇ、
平均５．１ｋｇであった。As shown in Fig. 3a, a lead pin 1 made of an iron-nickel alloy with a diameter of 0.45 mm and a length of 8 mm is brazed to the surface 1a with a thickness of 0.05 mm of Au33.3%-Ag44.5-Cu2.
The lead pins to which gold solder 2 made of 2.2% alloy was attached by sputtering were stored in a polyethylene bag for 3 months, and then 1000 lead pins were set on a mercury ceramic substrate 3 as shown in Figure 3. Teru-brazed,
When it was subjected to a tensile test, the weight was 4.5 kg to 6.0 kg,
The average weight was 5.1 kg.
第１図すに示す如くリードピン及び金ろうを夫々用意し
てセントする以外は、実地例と全て同一条件にてろう付
けし引張試験を行ったところ、２，５に、〜５．６ ｋ
ｇ、平均４．２ｋｇであった。As shown in Figure 1, lead pins and gold solder were prepared and soldered separately, but brazing was performed under the same conditions as in the actual example, and a tensile test was conducted.
g, average weight was 4.2 kg.
以上のことから明らかなように本発明の実施例にて得ら
れたろう付強さは、従来例のそれに比し極めてばらつき
が少なくかつ高く安定していることが判る。As is clear from the above, the brazing strength obtained in the examples of the present invention has extremely less variation and is highly stable compared to that of the conventional examples.
尚、実施例ではリードピン１のろう付は面１ａである先
端面にのみ金ろう２を取付けていたが、これに限るもの
ではなく第４図ａＡ−１のようにしてもよいものである
。また実施例では余ろう２をスパッタリングにて取付け
たが、これに限るものではなくめっき、溶接、圧接、か
しめ、溶融などリードピンｌに金ろう２がタイトに取付
けることができるものであれば、いかなる方法でもよい
ものである。Incidentally, in the embodiment, the gold solder 2 was attached only to the tip end surface 1a when soldering the lead pin 1, but the present invention is not limited to this and may be done as shown in FIG. 4 aA-1. In addition, in the embodiment, the extra solder metal 2 was attached by sputtering, but the method is not limited to this, and any method can be used as long as the metal solder 2 can be tightly attached to the lead pin l, such as by plating, welding, pressure welding, caulking, or melting. Any method is fine.
以上の説明で判るように本発明は、リードピンの少なく
ともろう付は面又はフイシン）を形成する部分に金ろう
をタイトに取付けているので、リードピンの保管中の酸
素が防止でき、ろうの濡れを雌実にすることができる。As can be seen from the above explanation, in the present invention, the gold solder is tightly attached to at least the part of the lead pin that forms the brazing surface or fillet, so oxygen can be prevented during storage of the lead pin, and the solder can be prevented from getting wet. It can be made into a female fruit.
またろう付はセットが容見てかつリードピンと金ろうと
の位置ずれのないものである。従って従来のリードピン
にとって代る画期的なものと言える。。Also, brazing is done so that the set looks good and there is no misalignment between the lead pin and the metal solder. Therefore, it can be said to be an epoch-making alternative to conventional lead pins. .
第１図ａ乃至Ｃは従来のリードピン及び金ろうの斜視図
、第２図ａ乃至Ｃは第１図ａ乃至Ｃに示すリードピン及
び金ろうをヤラミック基板にセットした状態を示す断面
図、第３図ａは本発明のリードピンを示す断面図、第３
図すは第３図ａに示すリードピンをセラミック基板上に
セットした状態を示す断面図、第４図ａ乃至ｉは本発明
に係るリードピンの他の例を示す断面図である。
１−一−リードピン、ｌ ａ −−−−−一ろう付は面
、１ｂ−−−一一一フィレソトを形成する部分、２−・
−・・金ろう。
出願人 田中貴金属工業株式会社
第３図
（ＣＩ） （ｂ）
第４図1A to C are perspective views of conventional lead pins and solder metal; FIGS. 2A to C are sectional views showing the lead pins and solder metal shown in FIGS. 1A to C set on a Yaramic board; Figure a is a cross-sectional view showing the lead pin of the present invention;
This figure is a sectional view showing the lead pin shown in FIG. 3a set on a ceramic substrate, and FIGS. 4a to 4i are sectional views showing other examples of the lead pin according to the present invention. 1-1-Lead pin, la-----1 brazing surface, 1b----111 Part forming the fillet, 2-.
---Gold wax. Applicant: Tanaka Kikinzoku Kogyo Co., Ltd. Figure 3 (CI) (b) Figure 4
Claims (1)
ンに於いて、該リードピンの少なくともろう付は面又は
フィレットを形成する部分に予め金ろうをタイトに取付
けたことを特徴とする集積回路装置用り−１′ピン。A lead pin for an integrated circuit device to be brazed to a ceramic substrate, characterized in that gold solder is tightly attached in advance to at least a portion of the lead pin that forms a surface or a fillet for brazing. 'pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185790A JPS5886754A (en) | 1981-11-19 | 1981-11-19 | Lead pin for integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185790A JPS5886754A (en) | 1981-11-19 | 1981-11-19 | Lead pin for integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5886754A true JPS5886754A (en) | 1983-05-24 |
Family
ID=16176936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56185790A Pending JPS5886754A (en) | 1981-11-19 | 1981-11-19 | Lead pin for integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5886754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60181046U (en) * | 1984-04-28 | 1985-12-02 | 藤好 克聡 | Terminal for ceramic layer package |
| JPS60194347U (en) * | 1984-06-01 | 1985-12-24 | 福井鋲螺株式会社 | lead pin |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132278A (en) * | 1974-09-13 | 1976-03-18 | New Nippon Electric Co | KIMITSUTAN SHINOSEIZOHOHO |
| JPS51130860A (en) * | 1975-05-10 | 1976-11-13 | Nichiden Kikai Kk | Method of manufacturing wire rods |
-
1981
- 1981-11-19 JP JP56185790A patent/JPS5886754A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5132278A (en) * | 1974-09-13 | 1976-03-18 | New Nippon Electric Co | KIMITSUTAN SHINOSEIZOHOHO |
| JPS51130860A (en) * | 1975-05-10 | 1976-11-13 | Nichiden Kikai Kk | Method of manufacturing wire rods |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60181046U (en) * | 1984-04-28 | 1985-12-02 | 藤好 克聡 | Terminal for ceramic layer package |
| JPS60194347U (en) * | 1984-06-01 | 1985-12-24 | 福井鋲螺株式会社 | lead pin |
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