JPS5886651A - Byte reference of word array memory and memory system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to random access memories, and more particularly to random access memories, and more particularly to random access memories, and more particularly to random access memories, and more particularly to random access memories, which store a digital word of one or more bytes during one memory cycle. ) or from l or more memory locations.

A data processing system typically has a memory subsystem having multiple memory locations for storing digital words consisting of a specific number of bits, for example 8.16.24 or 82. A typical 82-bit general register computer architecture uses variable-length instructions represented by a series of bytes, with a first byte specifying the operation to be performed and subsequent bytes specifying the operaside. Consists of. Each operand is 8.16
．． It consists of 82 and further 64 bits. 82 Pit War
By storing a mixture of variable-length instructions and data in a memory, for example, a portion of an 82-bit instruction or data word can be stored in the same location as a 16-bit instruction or data word, and the remainder can be stored in the next memory location. It is possible to make maximum use of the memory H storage space available when storing data in the memory.

Traditionally, efficient utilization of memory space has been achieved by combining hardware and software techniques. However, when part of an instruction or data word was stored in one memory location and other part in another, more than one memory cycle was required. As a result, efficient use of memory space was achieved, but the processing speed of the computer was reduced. The present invention utilizes local storage associated with a central processing unit (CPU) for primary storage in a data processing system;
Conventional primary storage can still be used with the access benefits.

The present invention provides a memory for storing digital words of different lengths in different addressable locations, each addressable location comprising a plurality of byte locations, the first byte location being located within the plurality of bytes. Disclose memory starting from any location. The storage elements are either read-write random access memory arrays or preprogrammed read-only memory arrays that require no writing means. A read-write memory includes a means for addressing any one or more bytes within a memory location and one or more bytes of a digital word during a memory cycle. one or more bytes of the digital word from the first memory location of the memory array during a memory cycle;
means for reading the remaining bytes of the second memory location. Furthermore, means are provided for aligning the bytes in a preferred order when writing to or reading from the memory, the means comprising an alignment decoder and a bidirectional multiplexer. The memory further includes an adder that increments the address of the memory location during a memory cycle, and a decoder that determines the number of bytes in a specified digital word. The capacity is to write or read eight bytes of a digital word to or from eight memory locations in the memory array within two memory cycles. It is given as follows.

The present invention also provides a memory for storing digital words of different lengths in different locations, each of the locations comprising a plurality of byte positions, the first byte position being a memory for storing digital words of different lengths in different locations, wherein Disclosed in Memo IJ' starting from here.

The first digital word of the memory represents the most significant bit of the memory location address, the second digital word represents the least significant bit of the memory location address, and the "eighth digital φ word represents the memory reference ( reference) represents the number of bytes. The memory includes: means for incrementing a first digital word to provide one or more memory location accesses during a memory cycle; first decoding means for generating a control signal;
second decoding means for providing a column enable signal for selecting a particular byte location in the memory in response to the second digital word and the eighth digital word; eighth decoding means responsive to generating a control signal for ordering the bytes to or from the memory; and an eighth decoding means responsive to the byte order control signal from the eighth decoding means to or from the memory means for transferring memory data words;
including. Means are also provided for incrementing the first digital word at least twice during two memory cycles to write or read eight bytes of the digital word from or to eight memory locations of the memory array. Each memory data word location is comprised of a plurality of bytes, and the number of least significant bits forming the second digital word is determined by loglN, where N is the number of bytes in the memory data word location.

The invention further provides for storing digital words of different lengths in different addressable locations, each of the locations comprising a plurality of byte positions, the first byte position starting anywhere among the plurality of byte positions. store and increment the address of a memory location to access more than one memory location during a memory cycle; write, reading one or more bytes of a digital word from a memory location during one memory cycle; writing one or more bytes of a digital word to a first memory of a memory array during one memory cycle; ′ location, write the remaining bytes to a second memory location of the memory array, and during one memory cycle, write one or more bytes of the digital word from the first memory location of the memory array;
and reading the remaining bytes from a second memory location, and aligning the bytes in a proper order when written to or read from memory. Disclose. Writing to or reading from a memory location during one memory cycle consists of incrementing the word address of the first memory location. Incrementing the word address of the memory location includes using an adder. The step of aligning the bytes in the proper order is done digitally using an alignment decoder.
It consists of generating control signals to arrange the byte order of the word.

Aligning the bytes in the proper order further includes a bidirectional multiplexer for forwarding and aligning data from and to the memory in response to an alignment decoder control signal.

The present invention will be explained in detail below according to examples.

Referring to FIG. 1, a block diagram of a word-organized, byte-addressable random access memory 126 is shown. The storage element or memory array 106 of the preferred embodiment includes a plurality of semiconductor random access memories (
RAM). Information in the form of 82-bit parallel digital words is passed through bidirectional multiplexer 104 to memory play 106 on 82-bit (4-byte) memory data bus RO2 and to memory array 10.
Transferred from 6. The digital word size of a storage location in memory array 106 is 4 byte references (BR) per location.

82 bits in one memory location (byttt reference) can vary depending on the size of the RAM used in memory array 106 and the requirements of various applications.
Two memory locations are shown to accommodate a mix of instructions and data of variable or different word lengths. memory·
Array 106 is word-organized and byte-addressable with instructions and data aligned in arbitrary byte ranges.

The location in memory to be addressed or referenced is the word address MSBS 118, memory
Address LSBS 120 and word byte size 1
22 Determined by human power signal.

The number of memory address LSBS120 signals is log2N
(N is the number of memory location words). In the preferred embodiment shown in FIG. 1, there are four bytes per word, and the Memory Address LSBS120 signal consists of the two least significant bits of the memory address.

Up to four (items) can be referenced during one memory cycle.

The remaining memory address bits are word address M
Forms the SB3118 signal. The word byte size 122 signal determines the number of bytes of a particular memory location to be addressed in memory, which is typically 1, 2 or 4 bytes. However, as explained later, 2
8) items can be addressed during a memory cycle. The word address MSBSl18 signal is connected to each of adders 110.112.114 and 116. The memory address LSB 3120 and word node size 122 signals are sent to the word range decoder 124.
, the decoder 124 determines when the digital word to be addressed is partially stored in two consecutive memory locations requiring a second memory location to be addressed. .

Memory address LSBS120 and word byte
The size 122 signal is also connected to an alignment decoder 2100 whose output is connected to a bidirectional multiplexer 104. The combination of alignment decoder 100 and bidirectional multiplexer 104 controls the order of bytes in digital words transferred to and from memory array 106. Furthermore, memory address LSBS1
The 20 and word byte size 122 signals are connected to column enable decoder 108, which selects the column or byte within the memory location of memory array 106 that is being addressed.

Referring to FIG. 2, 12 bytes of digital information are shown, representing a typical mix of variable length instructions with variable number of operand specifications and variable size data, stored in memory array 106 at 8.16.82. , or 64 pits in length.

The memory map of word address location 0, word address location 1, and word address location 2 shown in FIG. 1 represents a typical example of a useful storage arrangement for mixed information.

Each instruction includes an operation code (COP code) indicating the specific operation to be performed. Additionally, an instruction may include one or more operand specifications depending on the type of instruction.

Although the length of a particular instruction or data word varies in number of bytes as shown in FIG.
The location has 4 bytes or 82 pits. This means that some of the instructions or data are stored in one memory location and the remainder in the next memory location;
The total memory storage capacity obtained can be effectively utilized.

As shown in FIG.
is addressed by one column independently of the other columns. The word address MSBS118 signal of the memory location to be referenced consists of all memory address bits except the least significant pit of log2N;
They are added to the input of each of adders 110-116.

In this example where one memory location word contains 4 bytes, N=4 and log no. 4) is not 2, so the two least significant bits are the memory address LSB.
8120 signal. Each of the adders 110-116 either passes through the word address MSB 8118 signal unmodified or carries-in # from a word range (boundary) decoder 124 that decodes the memory address LSB 8120 signal and the word byte size 122 signal. Increment the word address by one via 128-184.

The preferred embodiment consists of 4 bytes per memory location, so when 8 bytes are stored in 8 consecutive memory locations: 8 bytes in 2 memory cycles.
Bytes can be referenced. Referring again to FIG. 1, see BR'l.

BH3, BH3, B'R5, BH3, B R7, BH3
, and an 8-byte string located in BH3 is referenced, then in the first memory cycle ζ until BH3, B
See H3, BH3, 73R5. When control signal lNC148 is output during the first and second memory cycles, it causes word address MSBS118 to increment twice and byte references BR6, BH3,
Address BH3, BH3.

Referring now to FIG. 8, memory array 106 has nine
Four 64x4 random access memory CRAMs such as 8419 type integrated circuits>150.152.154.15
Each RANG has multiple storage locations. If implemented with larger memory, each RAM
is replaced by multiple RAM banks. Each RAM (or RAM bank) receives one byte of data from bidirectional multiplexer 104 during write operations and outputs one byte of data to bidirectional multiplexer 104 during read operations. RAM reads and writes are performed using column enable.
Controlled by decoder 108. RAM word address 140.142.14 given by adder
4.146 is connected to the most significant address bits (,40 and AO) of RAM 150 through n156. Those skilled in the art will appreciate that the number of address bits is determined by the number of memory storage locations used for the RAM or RAM bank. It is understood that in FIG.
Only two address bits (AO and AI) of 56 are used, but other bits can easily be connected.

- Adder 110.111.114.116 details
As shown in the figure. These address each word address in memory array 106 under the control of word range decoder 124.
RAM word for addressing location
Generate address 140.142.144.146.

Each adder may be constructed from a 5482 type integrated circuit, for example, if only two address bits are required.

Carry from word range decoder 124 to each adder
The IN signal causes the word address MSBS 118 signal, represented by lines u, 40160 and MA, 162, to have one added to perform two memory references during a memory cycle. The INC signal causes all RAM word addresses to be incremented by one at the same time, so that all eight RAM addresses are generated to reference eight byte instructions or data.

Each adder in the Model 5482 integrated circuit is capable of adding two 2-bit binary numbers. It will be apparent to those skilled in the art that if the memory space requires more RAM, word address pits, high density integrated circuit adders or combinations thereof are readily available. .

Referring now to FIG. 5, word range decoder 124
A logic circuit is shown. NOR gate 164 and NAN
This decoder, consisting of a D-gate 166, includes an adder 110
.about.11'6 as a function of the LSB of the memory address and the byte size of the instruction or data memory reference. 1 If memory address LSB MA and MA are both true, then the carry-in is on line 128.18 to adder o5 adder l and adder 2.
o and 112 and the associated word address MS
Add 1 to BS118. If only LSBF)MA is true, the carry-in is Adder 0 and Adder 1.
is generated on lines 128 and 180 to add one to the associated word address MSBsl18. If LSB
MA, only true is root, carry in is adder 0
The associated word address MSB occurs on line 128 to
Add 1 to S118. The carry in on line 184 to adder 8 is always false. INc14 of this example
The 8 signal is one of the word byte size 122 signals. During the second half of the two-cycle 8-byte memory reference, a control signal is generated to add 1 to all associated word addresses.

The detailed logic of column enable decoder 108 is
Diagram A (gates 21O to 230, inverters 228 to 28
0) and FIG. 6B (gates 240-256 and inverters 258 and 260). This decoder provides write enable and write enable for each of the RAMs 150-156 shown in FIG. Generates output or chip enable. Control signal 1 byte 170.2 bytes 17
2.4 bytes 174 are given by word byte size 122 words and represent the number of bytes in a memory reference. The first memory byte location is specified by the memory address LSB8120 signal;
In this embodiment, it consists of MAt and M4. When information stored in a memory location in memory array 106 is to be read, an output such as CB RAM[RJ or a chip enable signal is generated to cause the RAM to perform a read cycle' (where "R" indicates RAM Reference display number is 0, ■, 2, or 8). Information is stored in memory array 1
06, the output signal and WRITE PL
It is ANDed with Sl 78, causing a load cycle to occur.

Referring to FIG. 7, the detailed logic circuitry of aligned decoder 100 consisting of gates 270-280 and inverter 282 is shown. Alignment decoder 100 generates an output signal when the memory reference is not 1-byte or 4-byte information, as if 2 bytes were requested. Aligned decoder 1
00 is select A for bidirectional multiplexer 104.
and select B signal to memory address LSBS12
0 signals (MAR and MA, ) and word byte size 122 signals (1 byte 170 and 4 bytes 174). Input-output MUX EEL, 4
The 180 signal is used for both the input multiplexer 190 and the output multiplexer 192 of the bidirectional multiplexer 104, and the input MUX 5ELB 184' signal is derived from the output MUX SEL B2S3 signal and the input-output MUX SEL, 4180 signal.

The input multiplexer 190 and output multiplexer 192 that make up the bidirectional multiplexer 104 are shown in FIG. 8, and Table 1 shown in FIG.
1, showing connections to C2 and C1.

Bidirectional multiplexer 104 rotates bytes into the preferred order during memory reference read and write operations.

The output multiplexers 192 are activated during memory read operations and are comprised of eighty-two 4:l multiplexers, each of which may be constructed from a 74LS85B type integrated circuit. Control signal READ 194 is connected to memory array 106
is performing a read cycle and is used to control the output enable of output multiplexer 192. Select A19 of output multiplexer 192
6 and select 8198 are controlled by alignment decoder 100, the input-output MUX EELA 180 signal is connected to select A 196, and the output MUX SEL
Z? 182 signal is connected to stem B 198. The input multiplexers 190 are activated during memory write operations and are comprised of thirty-two 4=1 multiplexers, each of which can be constructed from a 74.5'15B type integrated circuit. The alignment decoder 100 has an input multiplexer 19
0 select lines A200 and B2O2. The input-output MUX SEL Al2O signal is connected to the select left line 200 and the input MUX SEL
The E184 signal is connected to select B line 202. Table 1 also shows which memory bus bits are connected to each input multiplexer 190 and which RAM data output bits are connected to each output multiplexer 192.

The operation of the byte-addressable memory of the present invention as shown in FIG.
The following is an example of a 4-item data string in a memory cycle located in BR'1, BH3, and BiF3. separated,
These portions are referred to as the word address MSBS118 signal and memory address LSBS120 signal, respectively. The word address MSBSl18 signal is added to the adder 110.1.
12.114.116 and selects a word address location in memory array 106, e.g.
and where BRl is located.

To select the desired number of bits (such as BH3 and BRl), use the word byte size 122 signal power; This is important because the referenced memory address information is located in two separate memory locations, namely BH3 and BR'1H'7-). ” - BR8 and U B R9 in address location 1 and Howard address location 2. The word address MSBS18 signal passes through adder 114 and adder 116 to word address location
Reference is made to BH3 and BR'l. Same memory
During the cycle, the word address MSBS 118 signal is incremented by one by word range decoder 124 as it passes through adder 110 and adder 112;
As a result, it is referenced from BR8 and BR9 column address location 2. It is determined by column enable decoder 10B to read or write the appropriate number of information bits from or to a location in memory array 106. The reader receives an output enable (read) signal, such as CERAMO149.
, or a write enable signal, e.g. WE R
AM O14? occurs. When the output enable (read) signal is generated, the referenced byte is
BH3, BH3, 13R in array 1060 people boat
6. Appears in the order of BR'l. Bidirectional multiplexer 104 then aligns and reorders the 82-bit (4-byte) memory data under control of decoder 100.
BH3, BR'l, BH on bus 102 interface
3. Give in the order of BH3. First BH3, BH3, B
The contents of H3 and BH3 are written to the memory by the write operation.
When stored in array 106, the information appearing on 82 bit (4 byte) memory data bus 102 is in the order BH3, BR'l, BH3, BH3.

The bidirectional multiplexer changes the byte order to BH3, BH3,
BH3, immediately rearrange to BH3 and write the word address.
BH3, BH3 in the second half of location l, word
Lead BH3 and BH3 to the first half of address location 2.

When an 8-byte string of information located BH3, BH3, BH5, BH6, BR'l, BH3 and BR9VC is read from memory array 106, the operation of retrieving byte references BE2, BH3, BH3, BH3 is performed in the first memory - Performed as described above during the cycle. During the second memory cycle, control signal 1NC148 is generated and an additional 1 is added to the word address MSBS118 signal that passes through adder 110.112.114.11-6, causing BH3, BR'1, BH3, BH3 to Once addressed, the bidirectional multiplexer 104 reorders them into the proper order as described above.

Although the preferred embodiment of this invention has been described, it will be apparent to those skilled in the art that many other changes and modifications are possible within the scope of this invention. For example, although the embodiment uses read-write random access memory (RAM) play, read-only memory (ROM) integrated circuit chips could be used. In this case, no write control signals are required and the speed and storage efficiency of the present invention can also be achieved. The total storage capacity required for RAM or ROM will vary depending on the application, and the number of bits or bytes in a word will also vary depending on the total number of words. As storage capacity increases, so does the need for multi-bit adders or adder banks to increment memory reference addresses.

Furthermore, it is also possible to configure all of the integrated circuits necessary to implement the present invention in one large-scale integrated circuit CLSI>chip.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the byte addressable memory of the present invention. FIG. 2 is a byte reference memory map illustrating variable length instructions with a variable number of operands and instructions of different byte sizes. FIG. 8 is a block diagram of the memory array shown in FIG. FIG. 4 is a block diagram of the adder shown in FIG. 1. FIG. 5 is a logic circuit diagram of the word range decoder shown in FIG. 6A is a logic circuit diagram of the first part of the column enable decoder shown in FIG. 1, and FIG. 6B is a logic circuit diagram of the first part thereof. FIG. 7 is a logic circuit diagram of the alignment decoder shown in FIG. 1. 7 FIG. 8 is a block diagram of the bidirectional multiplexer shown in FIG. FIG. 9 is a connection table for the bidirectional multiplexer (FIG. 8) showing that the memory bus bits are connected to each input multiplexer and the RAM data output bits are connected to each output multiplexer. (Description of Codes) 100: Alignment Decoder 102: Memory Data Bus 104 = Bidirectional Multiplexer 106: Memory Array 108: Column Enable Decoder 110.112.114.116: Adder 124: Word Range Decoder Patent Applicant' Raytheon・Company (4 people)

Claims (1)

Claims: (1) Each of the locations consists of a plurality of byte locations, and the first byte of the digital word is different in different addressable locations in memory starting at any of the plurality of byte locations. access one or more memory locations during one memory cycle by incrementing the address of a memory location, and storing one or more digital words of length from a memory location. reading bytes in one memory cycle, reading one or more bytes of the digital word from the first memory location of the memory play and the remaining bytes of the digital word from the second memory location of the memory play. A method for referencing one or more bytes of a word-organized memory, comprising the steps of: reading during one memory cycle, and aligning the bytes in the proper order when read from memory. 2. The method of claim .alpha., wherein the step of reading from one or more memory locations during the 17 molar cycle comprises incrementing the word address of the first memory location. <8) Claim 2, wherein the step of incrementing the word address of the memory location is performed by an adder.
'the method of. 4. The method of claim 1, wherein the step of aligning the bytes is performed by a decoder that generates a control signal to align the order of the bytes of the digital word. 5. The method of claim 1, wherein the step of aligning the bytes is performed by a bidirectional multiplexer that transfers and aligns data from memory. (6) A memory for storing digital words of different lengths in different addressable locations, each of said addressable locations consisting of a plurality of byte locations, the first byte of the digital word starts at any one of said byte locations; apparatus for addressing any one or more bytes within said memory location; l
a memory system comprising: an apparatus for reading a remaining byte of or more bytes from a second memory location of a memory array during a memory cycle; 7. The memory system of claim 6, wherein said memory comprises an arithmetic unit for incrementing the address of a memory location during one memory cycle. (8) Claim <6i! wherein said byte addressing device comprises a decoder for counting the number of bytes of the referenced digital word. Memory system as described.