JPS5886597A - Electronic musical instrument - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a specific note (for example, the lowest note) of the loincloth pressed on the melody tone playing keyboard or key range IIm!
The present invention relates to an electronic musical instrument that produces a note having the same note name as a key pressed on an accompaniment sound playing keyboard or key range together with the sound of a key pressed on the melody sound playing keyboard or S end.

Conventionally, this type of electronic musical instrument was first filed by the same applicant in Japanese Patent Application No. 55-49958, titled "Electronic Musical Instrument".
There is a device described in the specification of

This device relates to the preceding sound of a specific key (for example, the lowest note) pressed on the upper keyboard, and uses the sound of the same note name as the key pressed on the lower keyboard as a melody additional sound. It was pressed! [47] It is something that is pronounced along with a sound (melody sound). By the way, the above-mentioned melody additional sounds are meant to supplement the melody sounds, and are merely additive to the melody sounds, so if a large number of melody additional sounds are sounded at the same time, the melody sounds will become blurry. I don't like it because it gets stored away. Therefore, a configuration is proposed in which the number of pronunciation channels for melody-added sounds is limited to a small number, such as "3", and the melody-added sounds are assigned to these sound generation channels to be produced, thereby limiting the maximum number of simultaneous pronunciations of melody-added sounds. However, with such a configuration, it becomes a problem how to select the notes to be produced (to be assigned) according to the order of priority. If the notes are assigned in the order in which they occur, the notes assigned in this way may not necessarily harmonize with the melody notes.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an electronic musical instrument in which the selection of melody-added tones is performed in a predetermined order of priority in consideration of harmony with the reference melody tones. do.

According to this invention, the melody-additional tones are prioritized based on a predetermined melody-tone, and the melody-additional tones to be generated are selected in accordance with the priority order.

Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.

FIG. 1 is a schematic block diagram showing an embodiment of an electronic musical instrument according to the present invention. This embodiment has an upper keyboard l for playing melody sounds, a lower keyboard 2 for playing accompaniment sounds, and a pedal keyboard 3. The upper keyboard IK plays melody sounds, and the lower keyboard 2 and pedal keyboard 3 play accompaniment. In addition to being able to perform each sound independently,
By operating the additional melody sound selection switch 4 and the additional melody sound mode designation switch 5, additional melody sounds associated with the pressed keys on the upper keyboard 1 and the pressed keys on the lower keyboard 2 can be generated. Note that the melody additional sound selection switch 4 is a switch for selecting whether or not to generate the melody additional sound, and the melody additional sound mode designation switch 5 is for selecting two generation modes of the melody additional sound, which will be explained next, namely close mode and open mode. This is the choice.

Here, the melody-added note is a predetermined key range on the bass side of a specific fi of the keys pressed on the lower keyboard 1 (in this example, the key corresponding to the lowest note of the pressed keys on the upper keyboard 1). Includes
This is a note with the same note name as the key pressed on the lower keyboard 2, and is automatically produced along with the melody note.The close mode of the melody-added note is a note that has the same note name as the key pressed on the lower keyboard 2. 3rd to 11th keys on the bass side for the lowest key.
The open mode is a mode in which the key range is up to #, and the open mode is a mode in which the predetermined key range is a key range from the 6th key to the 17th key on the bass side relative to the lowest key pressed by the clay figurine 111.

The keys pressed on the upper keyboard 11, lower keyboard 2, and pedal keyboard 3 are
Detected by the key press detection port 136, the key press detection circuit 6 generates a 4-bit 6 note code N4 to Nl indicating the note name of the lower key in response to the detection of the key press, and a 3-bit note code indicating the octave note. Upper keyboard signal U1 indicating octave codes B3 to B1 and the keyboard to which the pressed key belongs Lower keyboard signal L1 Pedal keyboard signal P
t occurs.

Note codes N4 to N1 and octave code B3 are used in this example for understanding the detailed circuit described later.
~Bit- Tables 1 and 2 are shown.

Table 1 Table 2 Note codes N4-Nl and octave codes B3-Bl generated from the pressed key detection circuit 6 in response to detection of a pressed key
and the keyboard signals U and L%P are applied to the sound generation assignment circuit 7. pedal!
11111 dedicated channel PK, 1 deyannel spare channel AR are set), keyboard signal U%L generated from key press detection circuit 6, key press detection circuit 6 corresponding to PC
The sound generation assignment circuit 7 performs control to allocate the note codes N4 to Nl and octave codes B3 to Bl' generated from the key press detection circuit 6 to any one of the dedicated channels corresponding to them, respectively. Code N4
~N1, octave code B3~B1 and am signal U
, L%P is monitored, and a key-on signal KO1 which becomes 11m when the key corresponding to the signal is being pressed is generated for each channel. Then note codes N4 to N1 and octave codes B3 to B1 are assigned to each channel.
The key-on signal KO is multiplexed into 4-bit key code signals KCI to KC4 and output in a time-division manner as shown in FIG. , @11.1
1” was used as the synchronization signal SY, @1111
The note codes N4 to Nl of the C sound corresponding to -1100" is returned to -1111", which represents the C note. Also, in Fig. 2(a), three time slots represent the contents of one channel, and the contents of the synchronization signal SY1 pedal keyboard channel PK are , upper keyboard dedicated channel UKI~U
The contents of K7, the lower keyboard dedicated channel LKI - the contents of LK7, and the contents of the spare channel AR - are output. In this embodiment, the preliminary tone and LE AR are especially used.The output of a dump switch 8 for selecting a dump effect is added to the sound generation assignment circuit 7, and the output of the dump switch 8 is (Dump signal DMP) is assigned to the signal KC''2 of the first time slot of the upper keyboard dedicated channel UKI and output from the sound generation assignment circuit 7. Note that such a sound generation assignment circuit is well known, so In this specification, detailed explanation thereof will be omitted.

Key code signal KCI output from the sound generation assignment circuit 7
~KC4 is an upper keyboard melody sound formation circuit 9, a lower keyboard accompaniment sound formation circuit 10, and a pedal keyboard accompaniment sound formation 1! IN 11
K is added to the key code signals KC1 to KC4 to form musical tone signals representing upper keyboard melody tones, lower keyboard accompaniment tones, and pedal keyboard accompaniment tones, respectively. These musical tone signals are then added to the sound system 16 via the melody tone tone circuit 13, the lower keyboard accompaniment tone circuit 14, and the pedal keyboard accompaniment tone tone circuit tSt, as the upper keyboard melody tone, lower keyboard accompaniment tone, and pedal keyboard accompaniment tone. pronounced nru. Here, the formation circuit 9.10.11 and the tone circuit 13.14.
15 and the sound system 16 can each be constructed from well-known circuits, so a detailed explanation will not be given.

Output key code signals KC1 to K of the sound generation i guessing circuit 7
C4 is added to the melody additional tone forming circuit 12. The melody additional sound forming circuit 12 receives key code signals KCI to KC.
Note codes N4 to N1 assigned to upper keyboard dedicated channels UKI to UK7 included in 4, octave codes B3 to Bl, note codes N4 to N1 assigned to LK7 to lower keyboard dedicated channel LKI, upper keyboard dedicated channel UKIK assignment A musical tone signal indicating a predetermined melody-added tone is formed based on the dump signal DMP and the outputs of the melody-added tone selection switch 4 and the melody-added tone mode designation switch 5. The operation of this melody additional sound forming circuit 12 differs depending on whether the closed mode is selected by the melody additional sound mode designation switch 5 or the open mode is selected, and the dump signal DMP is 11'' (dump mode is selected),
@0" (when the dump mode is selected), the way it is pronounced differs.

First, if the closed mode is selected, the keys pressed on the upper keyboard 1 will be pressed from the 3rd to j111th keys on the bass side starting from the key that indicates the lowest note of the 9 keys, that is, adjacent to the key that indicates the lowest note. Up to three notes with the same note name as the key pressed on the lower keyboard 2 and selected according to a predetermined priority order are added to the melody in the bass Ill octave keyboard range excluding 2 keys. Specified as . Here, the predetermined priority is to give top priority to the note with the same note name as the note name of the third key on the bass side from the lowest note above, and below, the notes on the bass side have lower priority. Temeru.

In other words, regarding the case where the F note is pressed, to explain using Figure 3, the sounding range of the melody-added note in this case is from the 3rd key to the 11th key on the bass side with the F4 note as the standard.
This is the key range up to the th key, that is, the key range from the ri note to the Fφ note. Your name here C% E% 0%
For example, if a key of Aφ, C, E1, G1, or Aφ1 is pressed on the lower keyboard 2, a note with the same note name as the key pressed on the lower keyboard 2 and included in the above keyboard range will be played. , that is, the Gs sound, Aφ1 sound, and cm sound are selected as the melody addition sounds.

In this case, the number of notes specified as additional notes for the melody is three notes, so the above priority order does not matter. If the key is pressed in the same way, it will be a D note, or a Cφ note.

The top three tones in the order of priority, such as C note - h, are designated as melody addition tones.

In addition, when the open mode is selected, the bass note 6th note is selected from the lowest note of the keys pressed in the clay figure Ill.
The key range from the th key to the 17th key (i.e., the lowest note above) is also a key range from the key half an octave below to the bass @ l octave, and is the same note as the key pressed on the lower keyboard 2. Up to three tones selected by name and according to a predetermined priority order are designated as melody addition tones. Here, the predetermined priority order is such that a note having the same name as the third key from the lowest note is given the highest priority, and below, notes on the bass side are given lower priority. However, in this case, the priority is set to be low regardless of the above priority order for the tonesha with the same note name as the key indicating the lowest note and the two keys on the bass side adjacent to this - in total. .

For example, if we consider a case in which the F4 note is pressed in the clay figure Ill in the open mode i in the same way as in the above-mentioned closed mode, the melody additional note in this case - the tone range is the 3rd note.
As shown in the figure, the key range is from the 6th key of the bass to the 17th key, that is, from the B note to the Cm note, based on the F note.

Here, if the four keys Cm note, E1 note, Gs note, and Aφaii are pressed by the lower key 112, then the note included in the above keyboard range with the same note name as the key pressed by the lower keyboard 2 , that is, the Cm note, Ea note, Gs note, and Aφ1 note are candidates for the melody addition note, but as mentioned above, the note that is the same as the key adjacent to the lowest note of the upper keyboard (Fa note in this case), which is the standard. Since the name sound (Bs sound in this case) is set to have a low priority, the E1 sound is not specified as a melody addition sound.
Three sounds are designated as melody-added sounds: C-gone %Gl sound and A4km sound.

4. The melody-added sound forming circuit 12 has three sound generation channels chi to ch3, and the melody-added sound is assigned to one of the three sound generation channels chi to eh3 for sound generation. DMP is @
Depending on whether it is 1# or @0# (depending on whether the dump effect is selected and is 9), the manner of sounding differs as follows. In other words, when the dump signal (■) is 11" and the dump mode is selected, when the tone assigned to the sound channel chi~eh:lc is considered to have been released (attenuated), the corresponding note will be played. - New assignments to that sound channel are prohibited for a certain period of time from the moment the key is considered to be a key.This means that if a new note is assigned before the sound of a good key has sufficiently attenuated because it is considered a key release, This is because a sharp pitch difference may occur between the already-produced sound and the newly assigned sound, resulting in a click sound.

When the dump mode is selected, the sound that is considered as a key release will rapidly attenuate, so new assignments to that sound channel will be prohibited for a certain period of time from the time that the key is considered as a release. If the above-mentioned click sound is configured and this fixed time is set appropriately (in this embodiment, it is set to 25 m+s), the above-mentioned click sound can be completely removed.

Also, if the dump signal DMP is @0'' and the dump mode is selected, there will be a new sound generation assignment.
When the sound generation is delayed for a certain period of time, the sounds that have already been assigned are attenuated rapidly. In general, even if the dump mode is selected and the key is released, the sound will not decay rapidly, so if the dump mode is selected and the key is released, the key will be released. If we adopt the above-mentioned configuration in which assignment to that channel is prohibited for a certain period of time from when it is determined that a sound has been The sound is not attenuated to the extent that no click sound is generated, and the click sound cannot be sufficiently eliminated.Therefore, in the case of V1 where the dump mode is not selected, if a new sound is assigned, this It is configured to delay the sound production for a certain period of time and forcibly attenuate the sounds that have already been assigned.

The details of the melody-added sound forming circuit 12 are shown in FIG. 4 and below.
11t-, the outline of this melody additional sound forming circuit N112 will first be explained in accordance with the fourth @, and then the detailed circuit will be explained below.

In FIG. 4, the key code demultiplex circuit 21 receives key code signals KCI to KC sent from the sound generation assignment circuit 7.
The key code demultiplex circuit 21 performs 4'i demultiplexing for each channel (
Note codes N4-N1, octave code B3- assigned to PK, UKI-UK7, LKI-LK7)
a1. A key-on signal KO and a dump signal DMP indicating whether or not to select a dump effect are output. The timing signal generation circuit n generates various timing signals (FIG. 2 (b) to (0)
) and a pulse P of a predetermined period are generated by a sound generation assignment circuit 7.
It is also formed based on the key food signals KCI to KC4 sent out.

UK lowest sound detection circuit 23 Mori, key code demultiplex circuit 2
Upper keyboard dedicated channels UK1 to UK7 output from 1
The key corresponding to the lowest note IIc of the keys pressed by the clay figurine Ill is detected based on the note codes N4 to Nl assigned to and the octave code B3=-Bl. (
And note code UN4 indicating the note name of this detected key.
~UN1t-output. t7'tUK lowest note detection path 2
Note codes UN4', UN3 to UNI and octave codes UB3' to UBI' for determining the range of the melody-added notes O to be formed in three loops are shifted forever. This note code UN4', UN3~UNI and octave code U
B3' to UBI' are different depending on whether the melody additional sound generation mode is closed mode or open mode, and in closed mode, note codes UN4 to UNI and Octave code UB3 ~ UBIK equal, half an octave lower than the key corresponding to the lowest note above the butterfly when in open mode -
Corresponding to note chords and octave chords -
Ru. Furthermore, as is clear from Table 1 above, the note codes N4 to N1 with the pitch name KTo and the note codes N4 to N1 with the pitch name half an octave different from this pitch name are equal in the first bit Nl or the third bit N3t. Since only the 4-bit N4 is different, the rounded note code that determines the melody additional notes and range is represented by UN4', UN3 to UNI, and 8f!
, tell.

The above two-tone code output from the lowest sound detection circuit to U-
1'UN4'% UN3 to UNI are added to the sound source 1124. The resource department generates a regular pitch Q sound source signal (
H) and the sound source signal of this regular pitch (H) Yoshi 4 pitch is 1
The H/L sound source clock generation circuit 241 generates two types of sound source signals, the low octave sound source signal (L), and the note code UN4 outputs the sound source signal (H) or (L) from the above UKK bass detection circuit. ' , UN3~UN
Each channel chi-e is switched by note name corresponding to I.
12 sound source signal generation circuits 242 and 243 that output separately for h3
．． Equipped with 244. The corresponding switching between note codes UN4' and UN3 to UNIK in this sound source section is as follows:
For pitch names that are lower than the note names indicated by note codes UN4' and UN3 to UNI, the sound source signal (H) has the normal pitch.
? For the pitch name on the high pitch side, a sound source signal (L) lower by one octave is output. In other words, if we look at this relationship with reference to the example shown in Figure 3 in which the lowest key on the upper keyboard is the pa note, in the case of close mode, the octave for determining the melody (A) - addition O octave. Codes UB3' to UBI' indicating the fourth octave are output from UK/lowest note detection circuit 4, but as mentioned above, note names Fφ to C higher than note name F are output from the sound source section Sae. Since the sound source signal (L) that is one octave lower is selected and output, the octave codes UB3' to UBI' indicating the fourth octave are used to select the F tone of the third octave, that is, the F tone of the fourth octave from the Fφ1 tone,
In other words, you can specify sounds in the range up to F4.

In the case of open mode, the octave code indicating the third octave to which the B1 note, which is a half-otatalower note than the F note, belongs, is output from the UKt-tone detection circuit O as the octave code UB3' to UBI' of the melody additional note. However, for the B note and the high note CK, the sound source signal (L) that is one octave lower is selected in the sound source section 24, so the octave codes UB3' to UBI indicating the third octave are selected. ' allows you to specify the tones in the range from the second octave C note, that is, the Cm note, to the third octave OB note, that is, the B1 note.

Priority circuit δ is below! l! It assigns a predetermined priority to the name of the 'fi-key pressed on keyboard 2, and the note codes UN4 to UN1t-base that indicate the note name of the lowest note on the upper keyboard are output from the UK lowest note detection circuit trace. The lower keyboard dedicated channels LKI to LK are output from the key code demultiplex circuit 21.
Signals corresponding to notebook foods N4 to M1 assigned to No. 7 are taken in with a predetermined priority. In the case of the closed mode, the priority circuit 5 is prohibited from receiving signals indicating the names of two adjacent pitches of the lowest pitch of the upper keyboard.

The LK note temporary memory station selects up to three note codes in order from the one with the highest priority among the note codes N4 to Nl prioritized by the priority circuit 5 and stores them as codes LN4 to LNI. This note code L
N4 to LNI designate the note names of the melody addition tones.

Note code LN stored in LK note temporary memory
I~LN4 are added to the LK note data memory 27,
Also, the octave codes UB3'' to UBI' output from the UKfiK note detection circuit O are added to the UK otatave data memory 28.The LK note data memory γ and the UK octave data memory 6 are each connected to three time-division sounding channels e h 1 - ch 3 is set, and the added note codes LN4 to LNI and octave codes UB3' to UBI' are respectively assigned to any channel (chi-ch3) [note data NN4 to NNI, octave data NB3 to This LK note data memory and the allocation in the UK octave data memo 928 are output in a time-division manner as NBI.
It is controlled by K. Also, key-on memory 4 is LK above.
Note data NN4 to NNI and octave data NB3-I- assigned to each channel chi to eh3 of note data memory n and square octave data memory.
It stores the key-off signal KON'(11" when key-on) indicating whether or not the sound corresponding to NBI is during key-on, and the key-on signal KON is generated based on the above-mentioned load signal LO and key-off detection by the assignment control circuit. ', and outputs this to each sound channel in a time-division manner in synchronization with the channel time corresponding to ehl-eh3. Note that key-on and key-off here do not necessarily correspond to the actual key press,
Note codes LN4 to L, Nl and octave codes UB3' to be assigned do not correspond to key release.
If UBI' is present, the key is on, and note codes LN4 to LNI and octave code UB to be assigned.
The key is turned off when 3' to UBI' disappear.

In addition, the allocation control circuit 313KLK note data memory n
Signals NCEQ %QCEQ and KON' applied from the %UK Otterp data memorizer, key-on memory device
allfi note code LN4~LNI
and a signal for determining whether or not the octave codes UB3' to UBI' have already been assigned; LK; a signal indicating that the signal LK added from the note temporary memory j is assigned to the notebook hoods LN4 to LNI to be assigned; U.K.
The signal UKCG applied from the lowest note detection circuit is a signal indicating that the lowest note of the upper keyboard has changed.The details of these O signals will be explained in detail in section a of the detailed circuit.

LK note data memory 27. Note data NN4 for each channel chi to eh3 outputted from the UK octave data memory hammer and key-on memory device in a time-sharing manner.
~NNI, octave data NB3 ~NBI, and key-on signal KONFi are added to the sound source selection opening/closing section 31. The sound source selection opening/closing section 31 includes note selection circuits 311, 312, 313, and note selection circuits 311, 131, 311, 312, 313, and 311, 313, which select, for each channel, a sound source signal corresponding to a desired note name from among the sound source signals output from the sound source section Sae. , Octave selection step $3 in which a sound source signal in a desired octanib range is selected for each channel from the sound source signals corresponding to the desired note name selected in steps 313
14.315.316 and octave selection circuit 114
．． Opening/closing time for each channel of the sound source signal output from 315 and 316 (amplitude envelope control) jl
1317.318.319, the note selection circuit 311 is provided.

312, 313 are controlled by note data NN4 to NNI applied from LK note data memory n, and octave selection circuits 314, 315, 316 are controlled by octave data N applied from UK octave data memory path.
Controlled by B3~NB1, switching circuit 317.31
8.319 is controlled by a key-on signal KON applied from a key-on memory. This opening/closing circuit 317.
The outputs of 318 and 319 are combined into one line and applied to the sound system 16 via the melody tone tone color circuit 13 shown in FIG.

By the way, the recognized sound source signal generation circuits 242, 243, 244 of the sound source part Sae in the melody addition sound forming circuit 12 and the note selection circuits 311, 312 of the sound source selection opening/closing part 31
．． 313, octave selection circuit 314.315.31g
, Open vII 4th 18!17.31B, 319 WCla
VsCu? Y? Data UN4', UN3 to UN are sent from MI11 circuit n by O ratte signal LA or LBK.
t, NN4 to NNI, N83 to NBI, and KONt. That is, the latch signals LA and LB are not generated.%All1! Therefore, even if the output of the UK lowest note detection circuit n, the output of the LK note data memory n, the output of the UK octave data memory device, and the output of the key-on memory device change, the melody additional tone generated does not change. The latch signal LB from the control circuit 32 is the new key-on signal N output from the key-on memory device.
Generation is controlled based on KO. In addition, the latch control surface #! Latch signals I and A from I32 are periodically generated signals. The second key-on signal NKO output from the key-on memory device is formed based on the load signal LO generated from the allocation control circuit (9) when the dump mode is selected (DMP=@1'). If the dump mode is not selected (DMP="0"), the allocation control plane w! 30 is generated based on the pseudo new key-on signal NKO'. This pseudo new key-on signal NKO' keeps the load signal LO for a predetermined period of time (12,
5ml1l) is delayed and is a good signal.

Further, the allocation control circuit generates the shunt decay signal SD' in synchronization with key-off when the dump mode is selected, and in synchronization with the generation of the load signal LO when the dump mode is not selected.

This OV w -) Decay signal SD' is stored in the key-on memory 4 on the condition that the dump signal DMP is @1'';
17.318.319 and rapidly attenuates the musical tone being produced. In addition, the short decay signal 8D generated when the dump effect is selected is controlled by the allocation control circuit (
9) serves as a prohibition signal for the load signal ILO generated from
Prohibits generation of O.

Next, each part will be explained in detail.

Figure 5 shows the details of the key code demultiplexing circuit 21 and the UK lowest note detection circuit.
0tsubu (hereinafter referred to as 079717071 circuit) 212,
C note chord change circuit 213 and AND circuit Ml
, the part containing the music 2t constitutes the key code demultiplexing circuit 21, and the other part constitutes the UK lowest tone detection circuit 23.
The 4-bit key code signals KCI to KC4 output from the 0 sound assignment circuit 7 are multiplexed with data for one channel for every three time slots, as shown in Fig. 3. Of the time slots, octave codes B3 to B1 and key-on signal KO are assigned to the second time slot, and note codes N4 to N1 are assigned to the third time slot.In addition, three time slots correspond to the upper keyboard dedicated channel UKI. The signal KC2 in the first time slot includes the dump signal D.
MP is assigned. A synchronization signal 8Y consisting of "1111" is assigned to the first time slot of the three time slots corresponding to the channel PK dedicated to the M9 pedal keyboard. Each channel PK is multiplexed into these three time slots.

UKI-UK7, LKI~L, ni7 data are pedal keyboard dedicated channel PK, clay figure board dedicated channel UKI~
They are repeatedly generated in the order of UK7, lower keyboard dedicated channels LKI to LK7, and reserve channel ARO.

D flip-flop circuit 212 and latch circuit 211
are note codes N4 to N1 and octave code 83 among the data included in the key code signals KCI to KC4.
The key code signals KC1 to KC4 released from the 0 sound assignment 1 path which demultiplexes the ~B1 and key-on signal KO are directly applied to the latch circuit 211 and are also applied to the D flip 1011 circuit 212 for one time slot. The latch circuit 211K is added after polishing. The latte circuit 211 receives the strobe electronic Bvc timing signal 72Y3 (a signal that becomes @1'' in the third time slot of the three time slots corresponding to each channel) shown in FIG. AND circuit A to which ivy pulse-2 (Fig. 2(b)) is input
The output signal of I is added. Therefore, the wrap circuit 211 has note codes N4 to N1 assigned to each channel PK-LK7, and the latch circuit 211 has an octa code.
The latch circuit 211 forms a melody additional tone based on the note codes N4 to N1, octave codes B3 to Bl, and key-on signal KOK latched in the latch circuit 211.
The optical signals N4 to Nl, 83 to B1, and KO are the key code signals KCI to generated from the sound generation assignment circuit 7.
It is delayed by one channel with respect to the channel indicated by KC4. Figure 2 (b) shows this relationship, where the time PT, UIT~U7T% shown in Figure 2 (6)
LIT-L7T%ART is defined as false pedal board processing timing PT, upper keyboard processing timing UIT-U7T1, lower keyboard processing timing LIT-L7T, and preliminary processing timing ART, respectively.

The latch circuit 214 latches the dump signal DMP included in the key code signal KCI~04. Second bit signal K of key code signals KCI to KC4
C2 is applied to latte circuit 214. Latch circuit 21
4 is a timing signal 'I'3 (a signal that becomes 1" in the first time slot of the three time slots corresponding to the upper keyboard channel UKI) shown in FIG. 2(d) IC to the strobe S. The dump signal DMPt is latched at the timing when the output signal of the AND circuit A2 is added to the output signal of the AND circuit A2 inputted with clock pulses φ2-5 and becomes @1''.

Note code N4 latched by latch @1I211~
N1 is added by C note code change times M213K. Cf [Give the corresponding note code N4 to Nl ``1
Change from 100” to @1111” and output. The reason for this change is the same as mentioned above. C sound change circuit 21
Note codes N4 to Nl output from 3 are priority circuits 5
and is added to the A inputs of the latch circuit 231 and the comparison circuit 232 as the lower 4 bits. Also, the octave code B inserted into the latch circuit 211
3 to Bl are added to the latte circuit 231 and also added to the comparator circuit 232 as the upper three bits.

In addition, the latch circuit 211 K latched key-on signal K
O is added to the latch circuit 231 and also added to the AND circuit 3 for 6t.

The circuit consisting of the latch circuit @ 231 and the comparison circuit 232 is assigned to the upper site dedicated channels UKI to UK7) and corresponds to the lowest note among the octave codes N4 to Nl and the octave codes 83 to B1, and also corresponds to the signal KO.
is 11" (the one that corresponds to the lowest note of the key being pressed on the upper keyboard > 1* output. The strobe terminal 8 of the latch circuit 231 is connected to AND circuits A3 and A4'.
, A5, OR circuit ORI, OR2 and inverter IN
A strobe signal SS formed in a logic circuit consisting of I is added. This strobe signal SS can be expressed as a logical expression as follows.

s s = (tco, Ko, xo*+i electric sea mountain y+
Ur)・φ Niconi, the signal CO is the output of the comparison circuit 232, and this comparison @11232 is the B input K 5 y Chi times M2
311C9y? A signal has been seen in which the lower 4 bits are the note codes N4 to N1 that are input, and the upper 3 bits are the octave codes B3 to 81. When A and B are established, a signal CO which becomes @1' is output. Also, the signal KO is the latch time M2
The key-on signal KO'' latched in the latch circuit 231 is a key-on signal KO1 latched in the latch circuit 231 - a signal delayed by one processing timing in the D flip-flop 233 (the D7 flip-flop 233 is Synchronous glue σtsuku pulse φj corresponding to processing timing
It is driven by φk. )・No signal iτ* company The above signal KO*t Inverter ■N'1 inverts the optical signal, and the signal Uwv is the upper keyboard processing timing U as shown in the second diagram.
Signal that becomes S i m from 2i to U7T, signal U
As shown in FIG. 2(i) K, g is a signal that becomes the function @1'# of the upper keyboard processing timing UIT.

Therefore, the wrap circuit 231 first unconditionally latches the contents of the upper keyboard dedicated channel UKI (note codes N4 to N1, octave hoods B3 to B1 and key-on signal KO) according to the signal UIK, and then latches the latched contents. If the key-on signal KO is not @l'', the contents of channel UK20 to be added next are latched unconditionally, and if it is @l'', M<B is established at gll1232, and the addition at 9 is seen. Latch the contents of the next channel UK2. This operation continues while the signal Un is "1", that is, from the upper keyboard processing timing U2T to U7Tt. As a result, the latched content of the latch circuit 231 corresponds to the lowest note of the key pressed at the upper*m position at the end of the upper keyboard processing timing U7T under all conditions that there is a key pressed down on the upper keyboard. Become. Latch circuit 231 K-wrapped notebook hoods N4 to Nl and octave codes B3 to B1 are applied to the company latch circuit 233 and to the A input of the comparison circuit 234.

The latch circuit 233 has an output signal from an AND circuit A6 to which the key-on signal KO latched by the latch circuit 231 and the timing signal L1 are input to its open terminal S. Here, the signal L1 is the lower one that occurs next to the upper one rainbow processing timing U7T as shown in FIG.
This signal is the function 11'' of the board processing timing LIT.

Therefore, the latch circuit 233K is the upper keyboard exclusive channel UKI-UK7KIR assigned note code N4~
Nl, the one corresponding to the lowest note among the octave codes B3 to Bl, and the one with KO=@1'' (corresponding to the lowest note of the key being pressed on the upper keyboard) is latched. Latch circuit 233 K latched note code N4
~Nl is sent to the priority circuit 5 as the upper keyboard lowest note code UN4~UNI.

It is also latched at latching times 11233 and the nine note code U
N4 to UNI and octave codes UB3 to UBI are sent to the tone generator part and the UK octave data memory in different manners in the open mode and in the closed mode O. Among the note codes UN4 to UNI latched in the latch circuit 233, the lower "beep" UN3 to UN
I is sent as is to the source section 24 regardless of whether it is in open mode or closed mode. Among the note codes UN4 to UNI latched in the latch circuit 233, the most significant bit signal UN4 and the octave code UB3 to UBI signal UN4t - the 4-bit signal UB as the least significant bit
3 to UN4 are added to the A input of the subtraction circuit 235. This subtraction circuit 235 is seen to be -111 when the open mode is selected for the B input, and when the open mode is selected, the above 4-bit signal @
Subtraction is performed by subtracting "l" from "UB3, UB2, UBI, UN4". In the case of rose mode, the signal 0PEN is subtracted by "@0" and the above subtraction is not performed. The subtraction circuit 235
The least significant bit signal of the output is sent to the sound source part as UN4', and the upper 3 bit signal is UB3'-UB3'.
It is sent to the UK octave data memory 4 as I'.

That is, when the close mode is selected, the note codes UN4 to U latched by the latch circuit 233
The NI meeting is sent to the sound source section as UN4', UN3 to UNI as it is, and the octave code UB3 to UB1t is sent to the UK octave data memory 4 as tUB3' to UBI', but if the open mode is selected, note Signal U of the most significant bit of code UN4 to UNI
Subtracting @1'' from a total of 4-bit signals UB3-UN4 consisting of N4 and octave codes UB3-UBI yields tfflA and note codes UN4-UNI.

The octave codes UB3 to UBI are processed and sent to the sound source section 1 and UK octave data memory. The modified note codes UN4 to UNI and octave codes UB3 to UBI are converted to note codes UN4', UN3^UNI and octave codes UB3' to UBI' corresponding to half-octave low notes. In other words, as is clear from Tables 1 and 2 above, KUN4 is ``11''.
In this case, by changing this to 3t"O", it is converted to a sound that represents the semi-otatarp low-note name in the same octave range, and if UN4 is m Oa+, this is changed to t-'"l". and octave code UB3~UBI to @1″
is subtracted and converted into a note representing the semi-otaku I-p-treble note name in the l-octave low i-octave range.

The comparison circuit 234 is a latch circuit 233 that detects a change in the lowest note of the note being pressed on the upper keyboard. The comparison circuit 234 has note codes UN4 to UNI and octave codes UB3 to UBI wrapped in the latch circuit 233 added to its B input, and the output signals (83 to 83) of the latch circuit 231 added to the A input described above. Bl, N4 to Nl), and the non-secondary output thereof is applied to the set input S of the flip-flop 2360 via the AND circuit AV and A8. The AND circuit A7 has the key-on signal KO latched by the latch circuit 231K applied to the other input, and the AND circuit A8 has the signal U (see FIG. 2 (j)) and the clock pulse φj applied to the other input. I get angry. Therefore, when the latched contents of the latch circuit 233 change, 7 lip 70 lip 2 is generated at the timing of clock pulse φj at upper keyboard processing timing U7T.
36 is set. The set output of this flexible flop 236 is sent to the assignment control circuit (equipment) as the upper keyboard lowest note change signal UKCG. Furthermore, when the signal U1 is applied to the reset input R of the flip 70 knob 236, the upper keyboard processing timing UIT4Il is reset.
Ru.

Latch circuit 231 Latched key-on signal K
O is latched to the latch circuit 237 at the timing of the signal L1.
8, and is sent to the priority circuit as the upper keyboard key-on signal UKO.

Figure 6 shows the details of the priority circuit 5 and the LK note temporary memory addition.The priority circuit 5 is the UK lowest note code UN output from the UK bass detection circuit.
A subtraction circuit 251 that calculates difference data between 4 to UNI and note codes N4 to Nl output from the key code demultiplex circuit 21, a decoder 252 that decodes the output of the subtraction circuit 251, and a lower keyboard amount among the outputs of the decoder 252. It is equipped with a difference data temporary memory 253 that temporarily stores information related to the difference data, and a parallel/serial converter 254 that converts all the stored contents of the difference data temporary memory 253 into serial data and sends it to the temporary memory base. .

The subtraction circuit 251 adds to the A input note codes UN4 to UNI indicating the note name of the lowest note of O in the middle of A, which is pressed on the upper keyboard 1 and is generated from the UK lowest note detection path.
A note code N4^Nl indicating the note name generated by the key code demultiplex circuit 21 is added to the B input.
Note code UN4~U for calculation of data that is incorrect when added to input.
Add the most significant bit (MSB) K"1" of NI, add @O" to the most significant bit (MSB) of note code N4-Nl, subtract it as 5-bit data, and calculate the lower 4 bits of the calculation result. )1-outputs 0 according to the v=5 method.For example, if the d note codes UN4 to UNI are G-ft-indicated@1001'' and the note codes N4 to N1 are EilYt-indicated-0101'', then ``11 (11
Subtract “00101” from 011r and get the calculated value”
``Data of lower 4 bits of 10100m'' 010
Output G'. The twisted note code UN4~UNI is -1001" indicated by the Gil tube, and the note code N4~UNI
Assuming that it is "1111" indicated by N11IXCitt, -011,11 is fully subtracted from "11001", and the lower 4 bits of the calculated value @01010 are the data @1.
010", that is, note codes N4 to N
When l indicates a pitch name on the bass side for the note codes UN4 to UNIK, subtraction is performed as is, but when it indicates a pitch name on the treble side, subtraction is performed by lowering this by l octave.

Here, note code N4 ~ NIK Based on the corresponding key, note code N4 ~ N from this key on the bass side than this key.
Table 3 shows the number of keys P up to the key corresponding to IK in relation to the calculated value Q of the subtraction circuit 251.

Table 3 The output of subtraction circuit 251 is applied to decoder 252.

Decoder 252t'i 16-bit decoder with subtraction port j
The calculated value (Q) of 18251 is connected to 16 output terminals (4) to (
15) Decode to any of (0) to (3) and output. Here, output terminals (4) to (15) of the decoder 252
(0) to (3), the calculated value (Q) of the subtraction circuit 251 is 10
-0 corresponding to each expressed in base number For example,
The calculated value (Q) of the subtraction circuit 2.1 is -0100" (10
When converted into 4) in base numbers, an output terminal (4) K signal ``1 m'' is generated.The arrangement of the output terminals of this decoder 252 indicates the priority order of melody-added sound formation, as will become clear from the explanation below. The output of decoder 252 is added to difference data temporary memory 253.

The temporary difference data memory 253 has 16 memory locations M4 to M15 and MO-M3' corresponding to the output terminals (4) to (15) (0) to (3) of the decoder 252, respectively. The configuration of locations M4 to M15 is represented by memory location M15, and the configuration of #I3 storage locations (0) to (3) is represented by memory location fil(3). That is, storage locations M4 to M15 of the difference data temporary memory 253
are each composed of two human-powered AND circuits AIO and a seven-lip, 70-tub FFI, and the two human-powered AND circuits AIO have a signal and a clock pulse at their inputs, ! The output of the AND circuit A9 that takes the AND condition and the signals of the corresponding outputs (4) to (15) of the decoder 252 are added, and the flip 70 tube FF'1 inputs the AND circuit AI to its set input S.
The output of O and the reset input RK signal Uv are respectively applied. Furthermore, the memory locations MO to M3 each consist of a 3-man-powered AND circuit All and a 7-lip 70-tub FF2, and the 3-man powered AND circuit A11 has its inputs connected to the output of the AND circuit 9 and the corresponding output terminal (0) of the decoder 252. ) ~
(3) signal and the output of inverter IN2 are added Ds
The 7-lip 70-tube FF2 receives the output of the set input BK AND circuit All, and the reset λ signal and the BK signal U drop. Here, the signal becomes 11" during the lower @l1iI processing timing LIT-L7T as shown in Figure 2 (0). The signal becomes 11" when the close mode is selected. 5 output signal CL
The output of a latch circuit 255 that latches O8E in accordance with the timing signal T shown in FIG. -0" if angry, -11" if open mode is selected.
Outputs a signal that becomes . Therefore, when the open mode is selected, the difference data temporary/Mo9253O each [1
1st place 11tM4-M15, MO-M3 AND circuit A
10 and All are lower-difficult processing timing LIT-L7
The opening operation of T is now possible, and this lower keyboard processing timing LI
A signal output from the decoder 252 during T-L7T sets the flip 70 knob FF1t or FF2 at the corresponding storage location. When the lt close mode is selected, the AND circuit 10 at the memory positions M4 to M15 can open the lower health cycle termination timing LIT-L7T, but the AND circuit All at the memory positions -MO to M3 is connected to the inverter IN2. The seven lip-flops FFI at storage locations M4 to M15 are only set by the signal output from the decoder 252 at the lower keyboard processing timing LIT-LET. In this close mode, the 7-lip 70-tube FF2 of the memory location MO-MS is not set to 4 even if there is a corresponding output from the decoder 252.
The 7-lip 70-tube FF, 1 and FF2 of MO-M3 are reset each time the signal υg is generated. In this way, the difference data temporary memory 253 corresponds to all the signals of the output terminals (4) to (15) and (0) to (3) of the decoder 252 at the lower keyboard processing timing LIT-L7T if it is open. Each memory location M4 to Mis, MO-M
Output terminals (4) to (4) excluding output terminals (0) to (3) of the output terminals of the decoder 252 that are stored in S and in the closed mode, the lower keyboard processing timing LIT-L7TKm is stored.
The signals in (15) are stored in the corresponding storage locations M4 to M15.

For example, what are the note names represented by the upper keyboard note codes UN4 to UNI? So, on the lower keyboard 2, note names C%E, G.

When the four llls of mm φ are pressed, the subtraction circuit 251
is 1011 during the lower keyboard processing timing LIT-L7T.
1", '0001', g"1101', 1100
1", and in the open mode, the storage locations M7, MO, Ml3, and the difference data temporary memory 253 are output.
@1” signal is stored in Ml, and in the closed mode, storage to the stored value 11M1 is prohibited, so the stored value 11
The @l'' signal is stored in 1M7, MO, and Ml3.

Each memory value 11M4 to [15
, MO-MS memory contents (each 7 lips 7a FF'l
, FF2 output) is connected in parallel to the parallel/serial converter (P/S converter) 254 at the generation timing of the signal Ts shown in FIG. The read signal is then output as a serial signal that represents the contents of memory location M4. Each time slot of this serial signal is synchronized with the time slot determined by the clock l<rus φ11φ2.
4, the timing at which the contents of the storage location M4 are first output is l time slots later than the signal Ts, that is, four time slots later than the signal T. The output of this P/8 converter 254 is applied to the LK note temporary memory 26 via an AND circuit A12. By the way, the AND circuit A 12 has the output of the AND circuit A 13 O added to other inputs, and the AND circuit 13 has the output of the latch circuit chamber S 6 which latches the output of the latch circuit 255 at the timing of the signal UvO and the latch circuit 2.
Take the exclusivity layer condition with the output of 55. Exclusive OR circuit E
A signal obtained by inverting the output of XI by an inverter INS, that is, a signal that becomes "O" when the melody-added tone formation mode changes, and an upper keyboard key-on signal UKO applied from the UK lowest note detection circuit are added. Therefore, the acid circuit A12 is activated when the melody-additional tone formation mode changes and when the upper trowel Ill is pressed, all i* keys are released.
If rL is large, it will not operate. 5. P/S: It is prohibited to add the output t-LK of the y parter 254 to the note memory.

The LK note memory has three storage locations MPI and a down counter 2611 that generates a corresponding note code in synchronization with the output serial signal, and down counter 2611 generates a corresponding note code in synchronization with the output serial signal. The corresponding note code generated from the counter 261 is stored in each memory location MPI, MP2, MP3KN primary memory fb.
.

The down counter 261 is composed of 4 pitch F kakuntas corresponding to the note chord. A, UK lowest note detection 11182
Note code UN4 indicating the UK lowest note output from 3
~UNi (Set at the timing of signal T, with this note code UN4~UN1 as the starting point, clock pulse *1
It sequentially counts down in synchronization with the two-phase tarokk pulse consisting of 11s φ2. Therefore, when the first signal (contents of storage location M40 of the difference data memory 253) is outputted from the P/8 converter 254 to zero, the down counter 2
61 is obtained by subtracting 4 in decimal from the note data UN4 to UNI, and the count value of the down counter 261 is completely synchronized with the output of the P/8 converter 253. Memory location MP1゜MP2,
Each MP3 consists of 4 bits, and the details of each bit are shown representatively with respect to the first bit. That is, although the structure from the second bit to the fourth bit is not shown in the figure, it will be discussed that they are structured in the same way as the first bit.The explanation for the second bit to the fourth bit (0) is shown in the first bit for convenience. This is done using the same symbol tJ11vh as that of each element.

The serial signal output from the P/S converter 254 is applied to the AND circuits 14, A18, and A22. By the way, as will become clear from the explanation given later, all D flip 7 clips DFI to D in the KLK root temporary memory
Since the IP6 is reset (sfL) upon completion of the shift operation (data sending operation) of the LK note temporary memo 9, the serial signal from this P/8 converter 254 is output from the LK note.
At the time when the temporary memory 211/C is added, the output of all D flip-flops DFI to DF6;
”ToL With this, andii road AI4, M18,
Of the modules n, only the AND circuit AI4 becomes operable. Therefore, the @1# signal first output from the P/8 converter 254 (storage location M4 of the difference data memory 253
~ M15, which corresponds to the "1" signal with the highest priority among the signals stored in MO-M3) is connected to the AND circuit A15WC of each bit of the storage location MPI via the AND circuit A14.
The AND circuit A15 is activated. At this point, the note code i output from the down counter 261 corresponds to the name associated with the above "1" signal,
This note code is passed through the AND circuit A15, OR circuit OR3, AND circuit A16, and OR circuit OR4't of each bit of the memory location MPI to the D flip 70 tube DFIK.
The output of the D flip 70 tube DPI is applied to the OR circuit OR3 and held. That is, by the @1# signal first output from the P/8 converter 254, the note code corresponding to the 11# signal is first stored in the storage location MPI.

Further, the output of the AND circuit A14 is applied to the D flip-flop 7σ tube DIP2 via the OR circuit oR5, the AND circuit jI A17, and the OR circuit 0R6t-, and the output is applied to the D flip-flop DIP2.
The output of F2 is added to the OR circuit OR5 and held.

The output of D7 lip 70 tube DF2 is inverter lN.
4t- when added through the AND circuit A I4K and 4
hK is added to AND circuit AI8 to disable AND circuit 14 and enable AND circuit 181 to operate.

2nd @″1 from P/8 converter 254 in ζO shape ■
``When the signal 11m is output, the 11m signal is sent to the storage location MP2! through the AND circuit A18 which is enabled.
0 is added to each bit's AND circuit AI9 to enable AND circuit 19. As a result, the signal of each bit of the notebook food output from the down counter 261 at this point is sent to the AND circuit A of each bit F of the memory location MP20.
19, OR circuit OR7, AND circuit M addition, OR circuit 0R
8t- is added to D flip-flop DF3 through D
The output of flip 70 tube DF80 is applied to OR circuit OR7#C and held. That is, P/8 converter 254
According to the second output "l:t'L11" signal from
This @11 will be remembered.

Further, the output of the AND circuit A18 is applied to the D flip 70 tube DF4 via the OR circuit OR9, the AND circuit A21, and the OR circuit OR10.
The output of is applied to an OR circuit OR9 and held. Further, the output of the D flip-flop DF4 is applied to the AND circuit AI8 via the inverter IN5 and also to the AND circuit A22, so that when AND@M A 1g is disabled, AND circuit jlA22t'm is enabled.

Subsequently, when the third 11" signal is output from the P/S converter 254, this "l" signal is output to the ANDRO path A2.
AND circuit A2 for each bit of memory location MP3 through
3KIXJ can be seen and the AND circuit can be operated.

As a result, the signal of each bit outputted from the down counter 261 at this point is an AND operation of each bit of the storage location MP3! It is applied to the D flip 70 tube DF5 via NlA23, OR circuit 0RII, and andro path A24, and the output of the D flip 70 tube DF5 is applied to the OR circuit 0R11.
added to and retained. In other words, P/S converter 2
According to the 11" signal outputted from 54 in the third writing, the note food that makes this @"1"1" signal is stored in the storage location MP3.

Also, the output of AND circuit A22 is OR circuit 0R12, Ay
The output of the D flip-flop DF6 is applied to the D flip-flop DF6 via the loop 5, and the output of the D flip-flop DF6 is connected to the OR circuit 0RL.
I! added to and retained. In addition, the output of the D-flip flop DF6 is connected to an AND circuit A via an inverter INS.
In addition to 22, 71. <And circuit A22 is fixed ff! Make it.

The first three "1" signals included in the serial signal output from the P/S converter 254 as shown in the CO.
1" signal, the note code corresponding to this @"1" signal is transferred from the down counter 261 to each memory location MPI.
%MP2 and MP3 are stored sequentially.

Dogu with the above action! The mysterious lowest health or F that is pressed by l,
The # pressed on the lower keyboard 2 is the C1 note, the Ea note, and the C note.
The case where the open mode is designated as the 1st note, 1st note, and the mode is A will be explained with reference to FIG. 7 as follows.

The down counter 261 inputs Fi at the timing of the signal T6.
rCorresponding note code @0110' (6 in decimal)
t-set, this value as the initial value, and the clock pulse φ
1. Count down in synchronization with φ2. That is, as shown in FIG. 7, the count value (content) of the down counter 261 becomes 6 in decimal notation at the timing of the signal T0, and then decreases to 5, 4, 3, etc., and when OK, the next [
15, and thereafter it becomes smaller as 14.13.12, etc.

Also, the difference data memory 253 has storage locations M7, M9, M
l3, Ml K@1" signal is memorized, and Jin's @1" signal is sent to P/S converter 1 at the timing of signal Tj! $4
1CI! ! Input A%P/8 Koni/From A-1254, 1II4 time slot, 6th time slot, 10th time slot
11 in timeslot F%4114 timeslot
A serial signal that becomes 1 is output. Therefore, when the first @11 signal arrives in the LK note temporary memory 26, the content of the down counter 261 is 15, which is the overnumber ttto, and the notebood indicating the C note corresponding to this 1o overnumber 15 is stored first. It is read into position MP1. Similar KP
/S converter 254 outputs the second 0@1'
The content of the down counter 261 when the signal arrives is 1.
The note code, which is 13 in 0 base and indicates the A sound corresponding to 13 in coto base, is then read into storage location MP2, and the third 11" signal arrives and the contents of down color/re 261 at 9 are as follows. The decimal number is 9, and the note code indicating the Q sound corresponding to the decimal number 9 is finally read into the storage location MP3. Note that the output of the P/S converter 254 causes the 411th note code to arrive at the 411th '''l''. No storage operation is performed depending on the signal Vh.

The note codes stored in the memory locations MPI%MP2 and MP3 in this way are set to the lower keyboard processing timing IIT%I.
, 4T, and L6T are sequentially shifted at the timing of the signal T Y Hatake, and the lower l11m note code I, N4 to LN
Output as I. This lower keyboard note code LN4~
LNI e) The output I# will be as shown in Figure 118.

The LK note temporary memory 26 stores the note code at the storage value f1MP1 at this storage location MPI.

The note code stored in the lower keyboard note code LN4 ~
Output as LNI. At the same time, D flip 70 Tsubu DF
2 outputs a signal LK indicating that the note code has been stored in the storage location MPI. Lower keyboard processing timing becomes L2T, lower keyboard processing timing L2TS L4T
, L6TO is @''11 only between signal AP (Fig. 2 (r
When @1-ms is output from the AND circuit A28, which takes the AND condition of the signal TYs (see Figure 2 (@) 11), the @-1' signal is output to the memory location MPI, M
It is added to the AND circuits A26, A27 and AND circuits *m, A30 of each bit of P2, and the ant circuits jlA26, A
27, A29, make the system operational. The output of the AND circuit input is inverted by the inverter IN7 and stored at the memory location MPI.

MP! , AND circuit AI6% of each bit of MP3, A
24 and AND circuit AI7% A21. Added to A25, 7yF111! A16, A20, A241A1
7, A21.

Make system 3 inoperable. From this k, the contents of memory location MP2 are moved to memory location 11MPIK, the contents of memory location MP3 are moved to memory value 11MP2, and from the note temporary memory device to I, the note written in memory value tMP2 is transferred. The codes are output as note codes LN4 to LNI, and a signal LK is output indicating that the note code is stored in the memory value ftMP2. Similarly, when the timing of the signal T*YsO of Shimoken Iwa processing Meimin fL and 4T comes, the AND condition of the AND circuit A28 is satisfied again, and the contents of the memory location MP3, which has been moved to the memory location MP2, are further transferred to the memory location MPIK. , LK note temporary memory j to memory location MP! The note codes stored in 1 and i are outputted as lower keyboard note codes LN4 to LNI, and a signal LK indicating that the note codes are stored in memory position MP3 is outputted. Continued below am
When the AND condition of the AND circuit is satisfied at the timing of the signal T*Ya of the heating timing L6T,
Due to the appearance of this AND circuit, 1F of the false memory value tMP3 that is moved to the memory location MPIK is cleared, and from this K, the lower keyboard note codes LN4 to LNI output from the LK note temporary memo 926 and the signal LK disappears.

FIG. 9 shows the LK note data memory 27. UK Octave Data Memory 28. This figure shows the details of key-on memory 4. LK note data memory, selector 271
．． A 4-bit, 3-channel (chi to eh3) time-sharing memory consisting of a 3-stage, 4-bit shift register 272, a comparison circuit 273 that compares the input/output data of this time-sharing memory, and a low-speed time 111 that compares the output of this time-sharing memory. A latch circuit M274t for converting into a signal is provided. To explain the LK note data memory 27 and m operation, first, when the cy-)' signal LO from the allocation control circuit (equipment) described later is @O, the selector 271
The input signal #IiA is selected, and the contents of the shift register 272 are held through this selector 271tP. When the load signal LO becomes '1'' and becomes 9 in relation to a certain channel time of the Vht shift register 272, the selector 271 selects the B input signal and adds this B input signal to the shift register 272. ,
The corresponding channel of the shift register 272 (ehl~
Rewrite the contents of eh3). In addition, the selector 271 of the comparison circuit 273 compares the signal applied to the B input with the output of the shift register 72, and outputs the λ-cannot code LN4.
Note code same as LNI is shift register 27
If the signal is stored in one of the two channels (i), a coincidence signal NCIQ is output at this channel time. Further, the output of the shift register 272 (high speed time division signal synchronized with the tarlock pulses φ1 and φ2) is applied to the latch circuit 274. In the latch circuit *2ia, the output of an AND circuit A31 which takes an AND condition of the clock pulse φβ and the clock pulse φ2 shown in FIG. 2 (-) is added to its stop terminal S. By synchronously latching the output of the shift register !!72, the output of the shift register 272 is converted into a low-speed time division signal consisting of four times as many time slots.

The UK octave data system is comprised of a selector 281, a circuit 283, a latch circuit 284, an inverter IN9, and an AND circuit A32. In this UK octave data mesori path, each circuit has octave codes UB3' to UB.
It has the same configuration as the LK menu memory 27 except that it has a 3-bit configuration corresponding to I'. However, U
In the K octave data memory column, the match signal output from the comparator circuit 283 is the signal 0CEQ.

Key-on memory 2g has 3 channels (ehl to eh3)
The shift register 291 includes two 3-stage 1-bit shift registers 291 and 292 and a latch circuit 293 that constitute a time-division memory, and the shift register 291 receives the load signal LO via the OR circuit 0R13 and performs The data is stored in a time-division manner for each channel via the circuit A33. The memory of each channel chi to ch3 of this shift register 291 is stored when a key-off detection signal No. 1 KOFF is added corresponding to a predetermined channel from an allocation control circuit (material), and this key-off detection signal KOFF is inverted by an inverter lN10. Joining AND circuit A33,
It is cleared when the AND circuit A33 becomes inactive. The output of the shift register 291 is the key-on signal KON
' and is added to the latch circuit 293.

Furthermore, when the dump mode is selected, the shift register 292 receives the load signal LO via the AND circuit A35 and the OR circuit OR14, and when the dump mode is selected, the shift register 292 receives the load signal LO via the AND circuit A35 and the OR circuit OR14.
The second key-on signal NKO' generated from the assignment control circuit (9) is received via the OR circuit OR14. The signals applied to this shift register 292 are time-divisionally stored for each channel via an AND circuit A34, and this memory is periodically cleared by a clock pulse φβ applied to the AND circuit A34 via an inverter INII. . The output of the shift register 292 is applied to the latch circuit 293 as a second key-on signal NKO'.

Further, a signal DMP indicating dump mode selection applied from the key code demultiplex circuit 21 is inverted by an inverter lNl2 and applied to an AND circuit A36. Therefore, when the dump mode is selected, the AND times *A36
is operable, and a short decay signal SD', which will be described later, output from the allocation control circuit (9) is applied to the latch circuit 293 via the AND circuit A36.

The latch circuit *293 is an AND n path A3 that takes an AND condition of its strobe terminal SK clock pulse φβ and φ2.
7 outputs are added to the output of the aforementioned latte circuit 274.
It performs the same function as H.284.

That is, the latch circuit 293 is the shift register 291.2.
The key-on signal KON', which is a high-speed time-division signal output from the AND circuit A36 and the AND circuit A36, converts the key-on signal SD' into a low-speed time-division signal, and converts the key-on signal SD' into a low-speed time-division signal, which It is output as a signal KON, a nee-keo/signal NKO, and a short decay signal SD.

This figure shows details of the first ov4#i allocation control circuit section. @Application control circuit part is LK note data memory n%
Each channel of the UK octave data memory column ehl-
The operation of this allocation control circuit (9), which controls the allocation of note codes LN4 to LNI and octave codes UB3' to UBI' to eh3, can be divided into a search mode and a load mode.

In search mode, LK note data memory n%U
K octave data memory each channel ehl-e
A note code LN4- is added by searching for a channel to be allocated among h3, and in load mode, generating a load signal LO in synchronization with the channel time of the channel to be allocated searched in search mode. LN
I and octave codes UB3' to UBI' are assigned. LK first output from LK note temporary memory addition
The search mode for the note code stored in the memory location MPI of the note temporary memory is executed at the lower keyboard processing timing LITK, and the load mode is executed at the lower keyboard processing timing L2T. Also, the second output LK note temporary memory 210 storage location MP2
The search mode for the note code EIl stored in is executed at the lower keyboard processing timing LSTKk-, and continues in the load mode. The search mode for the note code stored in the third output LK note temporary memory memory location MP3 is executed at the lower-hard processing timing L5T, and the a-do mode is executed at the subsequent lower keyboard processing timing L6T. In other words, as shown in FIG.
The load mode is performed at %L5T, and the load mode is performed at lower processing timings L2T, %L4T, and L6T.

First, let me explain while in search mode. In search mode i, note codes LN4 to L'NI are added to the LK note data memory 27 and octave codes UB3' to UB are added to the UK octave data memory 27.
I' is either channel chi to ch3 of LK note data memory I and UK octave data memory section
If the comparison time wI of the LK note data memory n is already allocated to the channel time of the current channel,
A discrete signal NCgQ of 11# is generated from 273, and a discrete signal OCgQ of "1" is generated from the comparison circuit 283 of the UK octave data system 4. Also this note code LN4
~LNI and the keys corresponding to octave codes UB3' to UBI' are considered to be pressed, the key-on signal KON' of shift register 291 of key-on memory 4 outputs 1 to 11'' is generated. When the signal is turned on, the above-mentioned signals NCgQSOCEQ, KON' and the signal BP shown in the axis of the second figure (which becomes 1# in the search mode) are added, and the AND condition of AND@*A40 is established, and this AND circuit A40 The output of is applied to the D7 flipflop DF7 via the OR circuit jlOR16, and
The output of the 0 block DF7 is added to the AND circuit 41 and held.The output of the OD circuit block F7 is added to the note codes LN4 to LNI and octave codes UB3' to UBI' that have already been assigned. It shows a certain benevolence. It should be noted that the good signal held in this D flip 70 tube DF7 is added to the AND@om 41 via the input terminal I-N 15 at the timing of the signal CL6 shown in FIG. 'Cleared every time the mode ends.

The load mode is performed by generating the load signal LO from the AND circuit A42. This AND circuit A42
The logical expression for the AND condition is as follows.

W UeF・Story・Niwa■′・As・Nta・Tasashi CG・TR・1W
・S “Here, the signal AP is at the processing timing L2T, L4T.
.

The signal LK shown in FIG. 2(m) is 11# only during LIT, that is, during the load mode, and the signal LK is a signal indicating that there is a melody additional tone to be assigned, which is output from the LK note temporary memory. ON' is a signal obtained by inverting the key-on signal K ON' output from key-on memory 4 by an inverter IN14, and a signal obtained by inverting the output signal As of the signal As#iD flip-flop DF7 by an inverter IN16. LN4～LN
This is a signal indicating that I and octave codes 1JB3' to -UBI' have not been assigned yet. Further, the signal NA8 is a signal obtained by inverting the output signal NA8 of the D flip 70 tube DF8 using an inverter IN13. AND circuit A43 to which signal CL6 is applied via
It is maintained by applying the output to the OR circuit 0R17. In other words, the output of D7 lip 70 tube DF8 is the added note code LN4~
LNI and octave chords UB3'~UBI' are OII this time! The signal NA is an inverted version of the output signal NA8 of this D7 lip 70 tube DF8.
S indicates that the added two-conid LN4-LNI and octave chords UB3'-UBI' are still very loud in this assignment. Further, the signal UKCG is generated from the UK lowest tone detection circuit n.
The lowest tone change signal Uxcat is a signal inverted by the inverter IN21, indicating that there has been no change in the UK lowest tone.

In addition, the signal TR generated by the truncate circuit 302 corresponding to the channel to be truncated will be briefly explained, but before that, key-off detection related to the operation of the truncate circuit 302 will be explained in detail. Note that the key-off here does not necessarily correspond to the actual key-off as described above, and the key-off detection in this implementation is based on the fact that the note codes LN4 to LNI and octave codes U B 3' to UBI' to be assigned are The false deviation between the output of the AND circuit A40 indicating that the load is approximately allocated and the load signal LO (output of the AND circuit A42) instructing a new allocation has expired for a predetermined time or more.k%
is detected as a key-off. The outputs of AND circuits A40 and A42 are OR circuit 0R15 and AND circuit M3.
3 stays via B”) 1-bit shift register 3
01, and the output of this shift register 301 is applied to an OR circuit 0R15. Therefore, note codes LN4 to LNI and octave code U should be assigned.
If B 3' to 'U B 1' have already been allocated or a new load signal LO is generated, 1 is associated with this channel (chi to eh3).
01 K″l ” signal is stored. This signal 111 is cleared at every processing timing ART by a signal AR (see FIG. 2 (b)) applied to the AND circuit Mua via an inverter IN22. The output of shift register 301 is applied to AND circuit A39 via inverter IN13.

Signal AR and key-on signal v to the input of AND circuit 1
, oW, and signals UKCG are applied, and a key-off signal KOFFt indicating key-off detection is output. The logical conditions for this AND circuit are expressed as follows.
.

KOFP=AR-AA-KON'-UKCG where signal AA is the output of inverter IN13.

That is, at the processing timing ART, the signal KON'
' occurs and both signals MMU and UKCG do not occur, AND condition ll1 of AND circuit A39
11IIt and outputs a key-off signal KOFF'.

The key-off signal KOFF is the key-on memory 2 mentioned above.
9 (added to the eleventh inverter lNl0, clears the memory of the shift register 291 in the channel, and sets the key-on signal KON' of the channel to ``0#''.

Truncate circuit 302 Fi above key-on signal KON
The above key-off signal KOFF' which is generated after ' becomes @O# is counted for each channel, and the channel with the largest count value is detected as the channel for which the arrival time has elapsed since the key was released, and the channel of this channel is A truncate signal TR is output at the time.

” Critical key-off signal KO output from AND rotation MA39
The FF is applied to the 3-stage 1-bit shift register SRI of the truncate circuit j13302, and the output of each stage of this shift register 5lLI is ORed by an OR circuit 0R18 to extend the pulse width to 3 channel times and sent to the adder ADloB. added to the input. Adder ADI
has a 3-stage i72-bit shift register 8 at its large input.
The output of R2 is added to the input of the shift register 5R20 via the gate circuit GAI which becomes inactive due to the addition output tkey-on signal head', and is added to the input of the shift register 5R20.
The key-on signal KON' operates only with respect to the channel @O1'', and constitutes a 2-bit time division counter that counts the key-off signal KOFF for each channel.

The output of the shift register SR2 is applied to the A input of the comparator circuit COMI and also to the M input of the selector SEI. Selector SEI has selector 8E1 on its B input.
A D-plip 70-tub circuit DCIO output is added that delays the output of the shift register 8 by one channel time.
The output of R2 is added to the input of the D flip circuit DCIO, which is thicker than the output of the D flip circuit DCIO.The output of shift register SR2 is selected and added to the D flip 70 block circuit DCIK, and the output of shift register 8R2 is added to the D flip 70 block DCIK. Select the output of the DCI which is smaller than the output of the D-flop and which is added to the B input, and select the output of the D-flop that is smaller than the output of
Add to CI. That is, when the output of shift register SR2 is larger than the output of D flip 70 tube circuit DCI, the output of shift register 8R2 rewrites the memory contents of D7 rib 70 tube circuit DCI, and shift register SR2
If the output of the D flip 7a block circuit DCI is smaller than the output of the D flip 70 block circuit DCI, the output of the D flip 70 block circuit DCI is applied to the B input of the selector Sgl again and held.

Note that the selection of the selector SEI is performed based on the comparison output A>H of the comparison circuit COMI. That is, the comparator circuit COMI has one D flip probe circuit DCI at its B input.
If the output of the shift register SR2 applied to the h input is larger than the output of the D flip-flop circuit DCI applied to the B input (A>B), “
1" comparison output cam > B? Send, this t selector SEl
In addition to A person select terminal 8A, selector 8 gtA
Enter input selection mode. On the other hand, when the output of the D flip 70 tube circuit DCI is larger than the output of the shift register 8R2, the comparison output cam〉B of ratio wRb noodles C0M1u-0'' is sent out, and this 177 times is sent to the selector 5EI via MNR1.
oB input selector SBK addition, selector SE1't
B Set to input selection mode.

The above operation K11l is performed during the search mode of the control circuit (9) (between the lower keyboard processing timings LIT, L3T, and LET), and the memory contents of the D flip-flop circuit DCIO are shifted at the end of the f-chi mode. Register 8R2
This is the maximum value among the count values of each channel chi to ah3 outputted in a time-division manner from .

The following load mode (lower keyboard processing timing L2T).

L4T, L6T), D flip-flop circuit D
The maximum value stored in CIK is compared with the output tube comparison circuit COMI of shift register 8R2, and when both values match (A = B), that is, the truncate signal TRt is output at the channel time when the maximum value is reached. do.

It should be noted that each time the load operation is completed, the output a"o" of the NOR circuit NRI is output by the signal CL6, and the value stored in the D flip-flop circuit DCIKE is cleared.

In this way, the truncate circuit 302 outputs the key-on signal K.
Key-off signal KO for channels whose ON' is @0"
While counting FFt, the maximum value of this counted value is detected for each serve mode, and a truncate signal TRt is outputted at the channel time of the channel determined to be the maximum value for each a-do mode.

Further, the signal DMP-8D' is the output of the NAND circuit NAI which takes the NAND condition of the dump signal DMP indicating selection of the dump mode and the stamp decay signal SD' output from the timer circuit 303. In order to explain the quality of the output of the NAND circuit NAI, the operation of the timer circuit N303 will be explained next.

The operation of the timer circuit 303 differs between when the dump mode is selected (DMP=@1'') and when it is not selected (DMP=''Oa). In other words, when the dump mode is selected responds with key-off 11+KOFPK, and this key-off signal K.

A signal 8D' which is a function 112 of a predetermined time (in this embodiment, time) is generated from the rise of the FF. In addition, when the dump mode is selected and the load signal LOK is selected, the load signal LOK is responded to, and the signal 8D'1 which becomes 11# is generated for a predetermined time (12.5 m5 in this embodiment) from the rise of the load signal LO, and the load is The tool-key-on signal NKO' is generated with a delay of IL5ms from the signal LO. This timer circuit 303 is arranged separately for each channel eh1-eh3 and operates separately for each channel. however,
In FIG. 10, only the first channel ehlK is representatively illustrated.

f! 111L29-Yannel eh2, t1g3''f The circuit related to Jannel ek3 uses the signal 'ray, %TsYa t in place of the signal T I Y a as a timing signal.
- Similar to the circuit shown, except that it is used. The operation of only the circuit related to the first channel chi will be described below.

First, the case where the dump mode is selected will be explained. When the dump mode is selected, the signal DMP becomes '''
1” and 6), Jin’s 112 signal DMP is the selector 804.
When the selector 304 enters the 8-manpower selection mode and the key-off signal KOFF is generated from the AND circuit A39 during the cut channel time, this signal KOFF is connected to the B input of the selector 304 and the signal T*Y.
It is applied to the set input S of the RS flip 70 block FF3 via the AND circuit A44, which is enabled to operate in the channel time of the first channel chl by S.
7 lip 70 tab FF31 set. And again
The output of IA44 is differentiated at the rising edge by a differentiation circuit IIDFFI, and is added to the reset manual power R of the counter COI.

Counter C0IH has a pulse signal PO of a predetermined period generated from timing signal generation circuit n at its count input CK.
By counting this pulse signal POi, a pulse signal is output 115 m5 and 25 rns after the output of the differential circuit MDFF1 is applied to the reset terminal R, and 12, . 5mm 1kK generated pulse signal P1
is applied to the AND circuit A45, and the pulse signal P2 generated 25 m- later is applied to the AND circuit A46. By the way, in this case, since the dump signal DMP#i@1'' is applied, the AND circuit A46 to which the dump signal DMP is added is operable, and the AND circuit A45 to which the signal inverted by the dump signal DMP't inverter 1N2O is applied is inoperative. Therefore, the pulse signal P2 output from the counter COI is applied to the reset human power RK of the flip-flop PF3 via the AND circuit A46 and the OR circuit 0R19 to reset the flip-flop FP3t.That is, the flip-flop FF3 is reset by the key-off signal KOFF. It is set for 25m5 from the rising edge of , and then reset.The output of this flip 70-tube FF3 is outputted as a signal 8D' via the AND1lfI6A47.OR circuit 0R20, which is enabled by the signal TsYs. The signal SD' is 25 seconds from the rising edge of the key-off signal KOFF.
This is a signal that becomes sim only during the channel time of the first channel @h1 during m5. Similarly, other channels ($125F Junonel eh2. 3rd channel ch3)
When the key-off signal KOFF is generated in the channel time of the second channel @h2 and the third channel eh3 for 25 m5 from the rise of the key-off signal KOFF, a signal that becomes @1'' is generated from another circuit, and the OR It is output from circuit 0R2Q.

Next, we will explain what happens when dump mode is not selected. If dump mode is not selected, the signal DMP
is "ol", and this 0 signal DMP is (inverter l
It is inverted at N19 and applied to the A input select terminal SA of the selector 304, setting the selector 3e4t-A input selection mode. In this state, from AND times jl A 42 to the first
When the load signal LO is generated in synchronization with the channel time of the y-yannel ehl, this load signal LO is applied to the A input of the selector 304, the flip-flop FF31C via the AND circuit A44t-, and the flip-flop FF
Set 3f. Further, the output of the AND circuit MA 44 is applied to the counter COI via the differentiating circuit DFFI, and the counter COI is reset in synchronization with the rise of the load signal LO. By the way, in this case, the dump signal DMPFi
Since the signal is ``O'', the AND circuit A45 is inoperative and the AND circuit A45 is operable.

Then, the output of the flip-flop FF3 is added to the AND circuit a4sacy via the D-flip 7σ block DFG.
- The AND condition is satisfied 12.5m+s after the rise of the LO signal LO, and the output of the AND circuit jlA45 is applied to the 7-lip 70-tub FP3C) reset input RK via the OR circuit 0R19 to reset the flip-flop FF3t. . Also, the output of the AND circuit WtM5 is the signal TYs
The AND circuit and the OR circuit 0R21 are operable as shown in the table below. The NKO' signal is outputted as the NKO' signal. 17 from the rise of load signal LOO! ,
The output of the flip-flop FF3, which is set for 5 ms+, becomes operational as the signal T r Y aKi and is outputted as the signal SD' via the AND circuit A47 and the OR circuit 1130B20. Timer circuit 303 like C
If the dump mode is selected, the load signal is L.
The slope decay signal S becomes @1” during the channel time of the relevant channel for 12.5m5O from the rise of O.
At the same time as D' is generated, a near key-on signal NKO' which becomes ``1#'' in the channel time of the relevant channel is generated after ILJmm has elapsed from the rise of the load signal LO.

The NAND circuit NAIK receives the start decay signal SD' and the dump signal D generated from the timer circuit 303.
MP is added. As a result, the NAND circuit NAI outputs the key-off signal KOFF when the dump mode is selected.
The key-off signal KO occurs at the channel time when the key-off signal KO occurs.
Generates a signal that is 10" for 25m10 from the occurrence of FF. Note that if dump mode is not selected, NAND rotation j
The output of l NAI is always ``1''.

Therefore, when the dump mode is not selected, the AND circuit A42 generates the load signal LO when the condition AP-LK-KON-As-NAS-UKCG-TR is satisfied based on the various signals explained above. If the mode is selected, even if the above conditions are met, the load signal LO will not be generated for 25 mm from the generation of the key-off signal KOFF for the channel in which the key-off signal KOFF has been generated.

In other words, when the dump mode is selected, for the channel where the key-off signal KOFF is generated, the load signal L is output for 25 nm after the key-off signal KOFF is generated.
The occurrence of O is territorialized.

The load signal LO generated from the earned circuit A42 is then added to the LK note data memory n% UK data memory and the key on memory 4, and
Note code LN4 generated from note temporary memory addition
~LNI, channel assignment control of octave codes UB3' to UBI' generated from the UK lowest note detection 111123, and formation control of key-on signals KON, low-key-on signals 8D, and two-λ key-on signals NKO are performed.

The 11th aill shows details of the latch control 1 circuit 320. The latch control circuit m:u receives the good signal AR and the second key-on signal NKO output from the key-on memory 4 in synchronization with the processing timing RTK, and outputs two types of latch signals LA (LA-1, LA-2, LA-3) and (LB-1, LB-2, LB-1) in relation to the channel time of the low-speed time-division data output from the LK note data memory n% UK octave data measuring device, key-on memory 4. Occur. As mentioned above, the channel time of the low-speed time-division data is determined by the latch timing of the latch circuits 274, 284, and 293 shown in FIG. -- and 0III section, it becomes k as shown in Figure 1 (-(g)).

In FIG. 11, the signal AR is applied to the D flip-flop DF10 via the OR circuit 0R22, and the output of the D7 flip-flop DF10 is applied to the OR circuit 0R22 via the D flip-flops DFII and DF12. . Also, D flip-flop DF 10, DF'l
1 and DF12 are driven by clock pulses φq and φβ, respectively. Therefore, the output signal R1 of the OR circuit 0R22, the output signal ARI of the D flip 70 block DF10, and the output signal AR3 of the D7 flip-flop DFII are as shown in FIG. 12-(c), (d), and (e). Become.

These signals ARI%AR2, AR3 are AND circuit INl! A
49, M group, and M51 perform an AND condition with the signal φ, respectively, and output them as latch signals LA-1% LA-2 and LA-3. Latch signal LA-1%I, A-2, LA
-3 is shown as happy itawω, 佽, (i)K. As is clear from FIG. 12, the latch signals LA-1, LA-2, L
A-3 is synchronized with the low speed channels ehl, eh2, and eh30 channel times, respectively. Also, latch signal b
Mu-1, LA-2, I, A-3 are And- Michihito Nozomi, Mu5
, A- are respectively ANDed with the key-on signal NKO, and the latch signals LB-1, I, B-2, I, B
-3 is output. That is, the latch signal LB-1,
LB-2, 1, B-I are latch signals LA-1, LA
- 2,5 people - 3 and synchronized with perfection, 2nd time - key-on signal N
This is a signal that is generated only when KO enters the channel time numbered by @''1-.

Figure 1113 shows details of the sound source section.

The sound source section S is an H/I that shifts the sound source signals H and L of the S11 class that are in an octave relationship corresponding to the 120 note names C to C, the sound source clock generation circuit 241, and the resource signals (H) and (L). ) is the note code tN4' output from the UK minimum detection circuit n, UNS to UNI.
Corresponding to the channel e h 1- e h 3jjI
12 sound source signal generation circuit 242 that selects and outputs IK;
Composed of 34.244 snow.

The H/L sound source clock generation circuit 241 consists of 120 circuits corresponding to each pitch name Cφ to C, and in FIG. 13, only the circuit corresponding to the pitch name CK is representatively shown in detail. . This circuit includes a counter CO2 driven by a clock pulse φ2, and a predetermined value detection circuit that generates one pulse P each time the count value of the counter CO2 reaches a preset predetermined value.

a pulse width expansion circuit PW that expands the pulse width of the pulse P into a pulse of a predetermined width and outputs the pulse width, a shift register 8R3, an adder AD2, a D flip-flop DF.
13, AND circuit A53, A54, OR circuit 0R23,
A kakunta circuit consisting of an inverter IN22 and adding "1" to the total every time a pulse P occurs, and :t7DOjl
OR24, 0R25, game) times MGA2 and -
Ru. When the count value of the counter CO2 reaches a predetermined value and a pulse P is output from the predetermined value detection 111iVD, this pulse P is seen by the pulse width expansion circuit PWK211, and the pulse width expansion circuit PW shifts this pulse P to the shift register 8R3. The output is expanded into a pulse with a pulse width corresponding to the number of stages. The output of this pulse width extension 816PW is applied to the shift input 8 of the shift register 813, the AND circuit S1, and the enable terminal EN of the gate (1111GA), setting the shift register 8BB to shift mode and the side of the input circuit S1. , the gate circuit GA2 and the gate circuit GA2 are enabled. The nine pulses P are applied to the summation D20 carry input CIK via the OR circuit 0R23, and are also applied to the gate circuit GJIK via the OR circuits 0R24 and 0R25. Gate circuit ωU is OR1 0124.0R2
5, the 2 O signal CH%CL is opened and closed in response to the signal CH.

As for CLK, a pulse P is first generated. Shift register 5IL
s becomes the diazi mode, shift register 5
The signal first output from the aso final stage is applied to the adder A of the adder AD2 via the aid circuit S. The adder AD2 has the addition input BK multiplied signal 0'' added thereto, and the carry input C1K has the pulse P added thereto as described above.

Therefore, adder AD2 first uses shift register SB
Signal @l'' is added to the signal first output from m. Addition output S of adder AD2 is added to shift register SR.
Added to the first stage of 3. When a signal "1" is generated at the carry output CO of the adder AD2 due to this addition, this signal "1" tiD flip knob D F 13
, is added to the carry power C1 of the adder AD2 via the AND circuit A54 and the OR circuit 0R23, so that the adder AD2 also adds @1'' to the second signal output from the shift register SR3. Note that if the signal @1'' is not generated at the carry output CO due to the addition, the adder AD2 directly adds the signal output from the shift register 8R3 to the first stage of the shift register SR3. The same operation as above occurs when the output of the pulse-stretching plane PW continues for a period of @1'', and the output of the pulse width expanding circuit PW continues for a period of ``
At the time when the value changes to 0', the values indicated by the contents of each stage of the shift register SR3 have been added by "1" as a whole. When the output of the pulse width expansion circuit PW becomes "0#", this signal is applied to the hold input H of the shift register 8R30 via the inverter IN22, and the shift register SR3 enters the hold mode and the contents of each stage remain unchanged until the pulse P occurs again. That is, the contents of each stage of the shift register SR3 are shifted every time a pulse P occurs, and "1" is added to the value represented by the entire contents of each stage, and this operation is repeated. . In the shift mode, the signal output from the final stage of the mi/ft register SR3 is applied to the gate circuit GA2 via the OR circuit 0R24, and the signal is applied to the gate circuit GA2 through the OR circuit 0R24.
is output as a signal CH. Mayu shift register 8
R3 also outputs a signal from the stage before the final stage,
``This signal is sent to the gate circuit GA2 via the OR circuit 0 and 5.
, and is output as a signal CL. Signals CH and CL
When compared, the signal CH is a signal Qr that changes at the period of the pulse P with pulse P at the beginning, a signal Qx that changes at the period twice the period of the pulse P, and a signal CH that changes at the period four times the period of the pulse P. Q1% Signal Q that changes at a period 8 times that of pulse P
, . . . are signals generated in a time-division manner.

That is, the signals P1Q1, Ql, Ql, Q4...
becomes a signal that repeatedly occurs every time the pulse P occurs. On the other hand, the signal CL has pulse P at the beginning and pulse P 4.
Signal -2 that changes at twice the period of the pulse P, signal Qs that changes at the period of 8 times the pulse P, signal Q4 that changes at the period that is 16 times the pulse P, etc. are the signals generated in a time-division manner. That is, the signals P%Q*, Ql, Q4-=... are signals that repeatedly occur every time the pulse P occurs. Although the above explanation has been given to the circuit corresponding to the pitch name CK, the circuits corresponding to the other pitch names have the same configuration except for the setting value of the predetermined calculation detection circuit VD.

In this way, the H/'L sound source clock generation circuit 241 is
Corresponding to each note name Cφ~C, the signal H(
CH) and L(CφL
1DL, . . . -CL) are generated and applied to the 12 sound source signal generation circuits 242, 243, and 244.

12 sound source signal generation circuits 242, 243, and 244 respectively correspond to channels ahl, eh2, and ch3, and note codes UN4' and UN3, which serve as standards for forming melody-added sounds output from the UKK bass detection circuit Oka.
~UNI is latched in response to latch signals LB-1, LB-2, and LB-3 generated from the latch control circuit 32, and signals H or L are generated for each note name in response to the latched note code of UNI. Vl deviation is selected and outputted as 12 signals. In Figure 13, i is channel chi.
Only the corresponding circuits are representative and their details are shown.

Note that the other circuits 243 and 244 are configured similarly to the circuit 242.

Note code UN output from UK lowest note detection circuit trace
4', UN3 to UNI are the latch circuits L based on the timing of the latch signal LB-1 generated from the latch control 1 circuit 32.
It is latched into system 1 and added to H/L tone generator control memory TCMK. H/L sound source control memo 9 TCM consists of read-only memory.

The selection pattern of signals H and L in the H/L sound source selector TCE is stored with note codes UN4' and UN3 to UNI as addresses. H/L sound source system - Memory contents of memory TCM with note code UN4', UN3~U
Table 4 shows the relationship between NI and the pitch name represented by NI.

Table 4 In Table 4, @1" means that signal H is selected by H/L sound source selector TCg, and 10# means that signal H is selected by H/L sound source selector TCE. For example, if the note codes UN4', UN3 to UNI output from the UK lowest note detection circuit trace represent the note name F, the H/L sound source control memory TCM will correspond to this note code. Among the signals output from the sound source clock generation circuit 241, the signal H is selected for note names Cφ to F and the signal L is selected for note names Fφ to C. Add to TOE.H/L
The tone source selector TCE selects and outputs the signal H or Lq)Vh for each tone name in response to the output of the H/L tone source control memory TCM. In other words, the H/L sound source selector TCE selects signals CφH and D, which are signals H for pitch names C to F.
H,Dφ1(,EH.

FH is selected, and the signal FφL%GL%GφL%AL%ASUL%BL is the signal for the note names F+ to C.

Select CL and output.

FIG. 14 shows the details of the sound source selection opening/closing section 31.
Separately, note selection circuits 311, 312, and 313 corresponding to each channel chi to eh3 select a desired one of the 12 signals output from the sound source section, and octave selection circuits 314, 315 .316 extracts and selects the signals of 2 feet, 4 feet, 8 feet, and 16 feet of the desired octave included in this selected one signal, and the open/close circuits 317, 318, and 319 apply the key-on signal KON to the sound source signal of each foot. , the output decay signal SD, and a predetermined envelope based on the dump signal DMP are added thereto, and these are outputted as open/closed. In addition, the first
In Figure 4, a circuit 311 corresponding to channel chi
．． The details of only 314.317 are shown as a representative. In the following explanation, for convenience, the same reference numerals as 9 used in the circuits 311, 314, and 31y will be used for the ring circuits.

The decoder ogci receives note data NN4 to NNI output in a time-division manner from the LK note data memory n, decodes this into 12 signals corresponding to each note name,
Each latch circuit LA of note selection circuit 311, 312, 313! Add to. Each latch circuit LA2 has latch signals LB-1, L at its strobe terminal 8 from the latch control circuit proverb.
B-2 and LB-3 are added, respectively, and the outputs of the decoder DEC1 are latched separately for channels chi to ch3.

The magnification decoder DgC2 receives octave data NB3 to NB outputted in a time-division manner from the UK octave data memory device.
I, decodes it into five signals corresponding to each octave, and sends the octave week IF circuit 314, 315.
316 latch circuits LA3. The latch circuit Lm3 connects the above latch signal LB-1% to its strobe terminal S.
I, B-2%L, B-3 are added, p, decoder D
Latch the output of EC2 to channels chi~*h3.

Note selection circuits 311, 312, and 313 each have a note code! Equipped with MCI, latch circuit 2
Based on the latched signal, a desired one signal is selected from among the 12 signals corresponding to the name of the musical tone output from the sound source section. As described above, the signal selected by the note selector NCE is a signal in which the pulse P is first I1IIK, and square wave signals having a frequency division by 1 are successively followed in a time-division manner. This signal is the octave selection circuit 314.315.31
6 shift register SR4.

In addition to the shift register SR4 and latch circuit LA3, the octave selection circuits 314, 315, and 316 include an octave timing control circuit OTC and a latch circuit LA4. Output from shift register SR4.

forming a latch signal with a timing corresponding to the signal latched in the latch circuit LA3 based on the applied pulse P;
This is added to the strobe terminal S of the latch circuit LA4, and the latch circuit LA4 is connected to this octave timing control circuit O.
Shift register SR4 responds to the latch signal from TC.
By latching a part of the parallel output, sound source signals (square wave signals) corresponding to 2 feet, 4 feet, 8 feet, and 16 feet of a desired octave are extracted and selected. 2 feet latched by this latch circuit LA4,
The sound source signals corresponding to 4 feet, 8 feet, and 16 feet are applied to analog switching circuits ASW of switching circuits 3175, 318, and 319, respectively.

The analog switching circuit ASW uses the charging/discharging characteristics of the capacitor CI to perform envelope control on the sound source signal corresponding to each foot to open/close the sound source signal.

That is, the sound source signal corresponding to each foot applied to the analog switching circuit ASW is envelope-controlled in accordance with the voltage generated in the capacitor CI. 7 This envelope control is performed based on the key-on signal KONK, and its mode is based on the key-on signal SD and the dump signal DM.
It varies depending on the contents of P.

First, the decay signal SD and the dump signal DMP are
Let us explain the case where the #vh deviation is also @O''. Now, if the key-on signal KON output from the key-on memory 4 rises from -e'' to ``''l'' with respect to the first channel chi, this signal diagram) is turned on. The latch control circuit 3
The latch signal LA-1 generated from the latch circuit LA-1 is latched by the latch circuit LA5 and applied to the gate of the transistor TRY. This turns on the transistor TRI, and the capacitor C1 is charged via the transistor TRI and the resistor R3 at a predetermined time constant corresponding to the resistance value of the resistor R3. After that, the first channel chi becomes key-off and the key-on signal KON becomes "0°", and the key-on signal KON output from the latch circuit LA5 becomes 10°.
When the value becomes 1, the transistor TRI is turned off, so that the charge in the capacitor C1 is discharged via the decay control variable resistor R4 with a time constant corresponding to the resistance value of the variable resistor R4. Note that at this time, the transistor TR2,
TR3 is off. In this case, capacitor C at Vl
When the voltage waveform generated at I is shown in relation to the key-on signal KON, it becomes as shown in Fig. 15 (Sakika). In other words, when the signals SD and DMP are both K"0", in addition to the analog switching circuit/8W The generated sound source signal is shown in Figure 15 (b
) is envelope controlled according to the waveform shown in ).

At some point after the key-on signal KON reaches 10", the switch-on signal 8 for channel chi is activated.
When D rises from K"0' to 1" as shown in FIG. 15 (d) ->fI-, this signal SD becomes the latch signal LA
-1, it is latched by the latch circuit LA5 and applied to the gate of the transistor TR2. As a result, the transistor TR2 is turned on), and the charge of the content tCt is transferred to the transistor T in addition to the path via the variable resistor R4.
It is also discharged through R2 and resistor R1, and the capacitor C1
The voltage shown by the voltage decreases dramatically. That is, the sound source signal opened and closed by the analog switching circuit ASW rapidly attenuates. The relationship between jin and jin is shown by the broken line in Figure 15 (b). Note that the resistance value of the resistor R9 is set to be 4 sufficiently smaller than the resistance value of the resistor R4.

Next, if the dump signal DMP is 11", this signal DM
P is added to AND circuit A56. AND circuit A56
A signal obtained by inverting the key-on signal KON outputted from the latch circuit LA5 by an inverter IN23 is added to the other input. Therefore, the key-on signal KON of the AND circuit A56 becomes 10", which enables operation after 9 seconds, and its output is applied to the gate of the transistor TR3, turning on the transistor TR3. As a result, the transistor TR3 is connected to the discharge path of the capacitor C1. A path via the resistor R1 is added, and the charge in the capacitor CI is transferred to the key-on signal KO.
When N reaches '''0°, a sudden discharge occurs.

The resistance value of the resistor R is set to be sufficiently smaller than the resistance value of the resistor R4, but the resistance value of the resistor R+ is also slightly larger.

Capacitor C when dump signal DMP is @1”
The voltage waveform generated at , is like a mountain in FIG.

Note that when the dump signal DMP is 1'', the short decay signal SD is inhibited by the AND circuit A36 shown in FIG. 9, so the signal 8D does not rise to 111.

Each analog switching circuit A8W of switching circuit 31f, 318.319 channel e'h 1 = c h 3 separate K
The sound source signals corresponding to 92 feet, 4 feet, 8 feet, and 16 feet are controlled to open and close at the top of the engine, and the sound source signals corresponding to 92 feet, 4 feet, 8 feet, and 16 feet are resistively mixed, respectively, to produce 2 feet sound 2', 4 feet sound 4', and foot sound %16. It is output as a musical tone signal indicating the foot note 16'.

In the above embodiment, musical tones of 2 feet, 4 feet, 8 feet, and 16 feet are generated as melody addition sounds, but 2! -Thailand~,
3) It can also be configured to generate sounds such as Sa feet. In this case, the note selection circuit 311 described above.
Note data NN in selection in 312.313
For the note names shown from 4 to NNl0, a signal corresponding to the note name of the 5-tone system is selected, and the octave selection fllllK
The note codes UN4', UN3~UNI and note data NN4~N added to the sound source 11s24 in the selection in
The configuration may be such that appropriate correction is applied to the octave data NB3 to NBIK using NI, and the extraction selection operation is performed based on the corrected octave data.

f9, the upper keyboard of the above embodiment (keyboard for playing melody sounds)
It is configured to produce a sound with the same note name as the sound of the 9th key pressed on the lower keyboard (accompaniment sound performance side 1) as a melody addition sound in relation to the range of a predetermined sound among the sounds of the key pressed on the lower keyboard (accompaniment sound performance side 1) However, the single-level keyboard is divided into two key ranges: a key range for playing melody sounds and a key range for playing accompaniment sounds. Relatedly, even if a note with the same note name as the note of the pressed key in the accompaniment note playing key area is configured to be pronounced as a melody additional note, the maximum number of simultaneous pronunciations of mourning melody additional notes will be increased. #li It was composed as 3 notes, but this is limited to 3 notes.

A similar configuration can be made for cases other than three tones.

In this case, a channel for producing melody-added tones corresponding to a large number of simultaneous pronunciations is provided, and a storage location corresponding to the above-mentioned number of channels is also provided in the ELK note temporary memory.

As explained above, according to the present invention, the melody additional sound to be generated is selected according to the predetermined zero priority set based on the reference melody sound, so that the melody sound and the melody additional sound are selected. Musically, you can achieve good harmony.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram showing an embodiment of the present invention;
FIG. 3 is an explanatory diagram showing an example of melody-added sound formation; FIG. 4 is a block diagram showing a schematic configuration of melody-added sound circuit 0III. , Figure 5 is a circuit diagram showing the details of the key code demultiplex III and UK lowest note detection circuit, Figure 6 is the priority circuit, LK note temporary memory ow
Figure 9 shows the circuit diagram showing the circuit diagram, Figure 7 and Figure 8 show the operation of the temporary memory. Circuit diagram shown, No. 10
Figure 11 is a circuit diagram showing details of the allocation control circuit, Figure 11 is a circuit diagram showing details of the latch control circuit, Figure 12 is a timing chart explaining the operation of the latch control circuit, and Figure 13 is the details of the sound source section. FIG. 14 is a circuit diagram showing details of the sound source selection opening/closing section, and FIG. 15 is a waveform diagram illustrating the operation of the sound source selection opening/closing section. l-Upper keyboard, 2...Lower #Rock, 3...Pedal keyboard, 4
... Melody additional sound selection switch, 5... Melody additional sound mode selection switch, 6... Key press detection circuit, 7
- Sound generation assignment circuit, 8- Dump switch, 9 = Upper keyboard melody sound formation circuit, 1o... Lower keyboard accompaniment sound formation circuit, 11 = Pedal keyboard accompaniment tone tone circuit, 12 - Melody additional sound formation Circuit, 13-...Melody tone tone circuit,
14-・Lower keyboard accompaniment tone tone circuit, 15... Pedal keyboard accompaniment tone tone circuit, 16... Sound system, 23-
UKjl bass detection circuit, δ...priority circuit, envy...,
LK note temporary memory, η...LK note data memory, Grave...UK octave data memory, 29...
Key-on memory, (capital) - assignment control ill@ro, 31
-.Sound source selection opening/closing section, 32-...Latch control circuit.

Claims (1)

[Claims] (11th t) #111N or the first key information indicating the sound of the key pressed in the keyboard range and the sound of the key pressed in the second keyboard range t. Based on the second key information indicating
Forming a signal indicating a sound related to the pitch range of the fixed tone among the sounds indicated by the first DII information and having the same pitch name as the sound indicated by the second key information, and assigning the scissors signal a predetermined priority order. a signal generating means for generating an associated signal; a selecting means for selecting a predetermined number of signals in order of priority among the signals generated by the signal generating means; and a signal corresponding to the signal selected by the selecting means. An electronic musical instrument is provided with a musical sound generating means. Q) The signal generating means includes a selection circuit that selects predetermined single key information from the first key information, and a sound indicated by the key information selected by the selection@register, as a reference sound, and a numerical signal generation circuit that detects the interval between the pitch name of a sound and the pitch name of the sound indicated by the second electric information and generates a numerical signal corresponding to the number sound S; A decoding circuit that demarcates and decodes numerical signals according to a predetermined priority order, and a memory that has a plurality of storage locations corresponding to the decoding circuit and each output, and stores each output of the decoding circuit in each storage location. 2. The electronic musical instrument according to claim 1, further comprising: a circuit; and a reading circuit for sequentially reading out the contents of each storage location of the storage circuit. (3) The selection circuit is configured to select key information corresponding to the lowest note from among the first key information. electronic musical instrument. (4) The numerical signal generation circuit subtracts second pitch name information indicating the pitch name of the sound indicated by the second key information from the first pitch name information indicating the pitch name of the reference sound. - The electronic musical instrument according to claim 2). The predetermined priority order set in the decoder is such that numerical signals corresponding to pitch names one and a half lower than the pitch name of the reference tone are given top priority, and the following pitches have higher pitches than the pitch name of the reference tone. Numerical signals corresponding to pitch names are given lower priority, and numerical signals corresponding to pitch names and pitch names of the reference note, and pitch names that are a semitone and a whole tone lower than the pitch name of the reference note, are given the lowest priority. Claim No. 21 (electronic musical instrument according to claim 21). (6) The storage circuit stores storage locations corresponding to a predetermined number of low-priority signals among the output signals of the decoding circuit. The electronic musical instrument according to claim (5), further comprising means for selectively inhibiting the storage of the data. It consists of a shift register having /, reads the storage contents of each storage position of the storage circuit into each stage in parallel, and directly outputs the read contents to the duplexer 1j in descending order of priority through a shift operation. Claim No. 2 (electronic musical instrument according to claim 2). However, the selection means selects a predetermined number of signals on a first-come-first-served basis from among the good signals output from the readout circuit, and stores all key information corresponding to the signals. and a key information temporary storage circuit that sequentially outputs the stored key information, and an allocation circuit that allocates the key information t output from the key information temporary storage circuit to any one of a plurality of sound generation channels. can be,
2. The electronic musical instrument according to claim 2, wherein the musical tone generating means includes a musical tone forming circuit that is assigned to each of the sound generation channels and forms musical tones for each channel based on companion key information. (9) The key information temporary storage circuit has a predetermined number of storage locations, has first pitch name information indicating the name of the reference tone as an initial value, and counts down in synchronization with the readout operation of the readout circuit. a down counter that is selected on a first-come, first-served basis, and sequentially reads the counted value of the down counter into the memory location in response to a predetermined number of signals, and sequentially outputs the read counted value at a predetermined timing. An electronic musical instrument according to claim 1. GO) The musical tone forming circuit includes a tone generator circuit that generates a good tone source signal corresponding to each tone pitch, and a predetermined tone source signal from among the tone source signals generated from the tone generator circuit to a key assigned to each of the tone generation channels. A pre-selection circuit that selects each channel based on information, and the pre-selection IM! The electronic musical instrument according to claim 1, further comprising an opening/closing path that performs oscillating envelope control on a channel-by-channel basis with respect to a sound source signal selected by the method. (11) The sound source circuit includes means for generating two types of sound source signal tubes having an octave relationship tIc corresponding to each pitch, and means for generating two types of sound source signal tubes corresponding to the pitch names of the reference sounds. The electronic musical instrument according to claim 10, further comprising a means for selecting and outputting one of the two, and an odor-containing device. (12) The 10th keyboard or keyboard area is a keyboard for playing melody sounds or a keyboard area for playing melody sounds, and the 10th keyboard or keyboard area is a keyboard for playing melody sounds, and
The electronic musical instrument according to claim α), wherein the keyboard and Fi key range are the keyboard range for playing accompaniment sounds.