JPS588611B2 - Hakeiseikei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a waveform shaping circuit using a bipolar logic system (hereinafter referred to as IIL) that includes a carrier injection mechanism section and uses this section as a base power supply section of an inverter transistor. It is related to.

The feature of IIL is that the substrate or the epitaxial layer formed on this is used as an emitter region, and the base region and collector region are formed into this so-called inverted N.
The base current to the PN type transistor is controlled by using the substrate or the epitaxial layer formed on the base region as the base region.
The base current is supplied by a PNP transistor that uses the base region of the PN transistor as the collector region, and the base current can be supplied by applying a voltage equivalent to the rising voltage between the base and emitter of the PNP transistor. It is possible to operate at extremely low voltages, there is a common structural region between NPN transistors and PNP transistors, and the emitter region of PNP transistors can be a common region, which increases the degree of integration. The effect that can be improved is produced.

FIG. 1 is a diagram equivalently showing a logic circuit configured by connecting two stages of IILs described above, and shows a PNP transistor 17 forming a carrier injection mechanism section.
When a voltage is applied to the terminal 18 so that the emitter of the transistor 17 is positive with respect to the base of the transistor 17 and a current is supplied, the PN
A current is supplied to the collector of the P-type transistor 17, that is, the base of the NPN-type transistor 19, which is an inverter transistor.

At this time, if the base of the NPN transistor 19 is kept at ground or a potential close to it, the NPN transistor 19 is in a cut-off state, and the transistor 17
The collector current flows out from the terminal 20.

On the other hand, when a voltage higher than the base-emitter rise voltage of the NPN transistor 19 is applied to the base of the transistor 19, the transistor 19 becomes saturated and its collector potential becomes almost grounded.

That is, a signal obtained by inverting the signal applied to the base of the NPN transistor 19 is obtained at the collector 21 of the NPN transistor 19.

If the collector 21 of the NPN transistor 19 is connected to the base of a separately arranged NPN transistor 22, the NPN transistor 22 becomes conductive or disconnected in the opposite relationship to the NPN transistor 19, and its collector The obtained signal has an opposite phase relationship with the signal obtained at the collector of the NPN transistor 19.

Furthermore, the time required for a signal to pass through this circuit, that is, the transmission delay time td, is inversely proportional to the power Pd supplied to the emitter of the PNP transistor 17, as shown in FIG. 2, and is the product of both. Pd and td are constant.

By the way, in the past, capacitors were generally used to generate pulses, and the pulse width was determined by the time required to charge and discharge the capacitor, but with current integrated circuit technology, capacitors can be built on chips. This was a problem in terms of price, and external capacitors were often used.

The present invention utilizes the above-mentioned IIL signal transmission delay time to be integrated into a circuit at low cost without using a capacitor, and to output a pulse having a desired pulse width in response to an input signal, which is different from conventional methods. The purpose is to provide waveform shaping circuits with different structures.

The present invention will be described below with reference to the drawings.

3A, B, and C show the respective waveforms of the input signal, the signal generated at the collector 21 of the inverter transistor 19, and the signal generated at the collector 23 of the inverter transistor 22 in the equivalent circuit of IIL shown in FIG. 1. Therefore, when the pulse applied to the terminal 20 attached to the base of the transistor 19 changes from a low level to a high level (a1 in A in the same figure), the transistor 19 starts from this point with a delay time t.
It becomes saturated after df (a2 in figure B)
, the current supplied to the base of the transistor 22 passes through the collector 21 of the transistor 19 to the transistor 19.
(a2 in Figure B).

As a result, the transistor 22 is cut off after the delay time tdr has elapsed from the time when the transistor 19 is saturated.

(a3 in Figure C). On the other hand, when the input pulse changes from high level to low level (b1 in Figure A), the delay time td
Transistor 19 is cut off after r has elapsed (
b2 in Figure B).

Therefore, the transistor 22 becomes saturated after the delay time tdf has elapsed from the time when the transistor 19 is cut off (b3 in FIG. 3C).

That is, the pulse signal applied to the input terminal 20 is delayed in the transistors 19 and 22, and the pulse signal is delayed in the transistors 19 and 22.
The delay time required for the signal to be transmitted to the collector 23, which is the output terminal of 2, is (tdf+tdr).

The above is the delay time when two stages of inverter transistors are connected, but when k transistors are connected (k is an integer of 3 or more), first of all, when an even number of transistors are connected,
The delay time is k(tdf+tdr)/2, and the output waveform is the same as the input waveform.

Next, if k is an odd number, the delay time when the input pulse changes from high level to low level is tdr+(k-1)(td
f+tdr)/2, and the delay time when the input pulse changes from low level to high level is tdf+(k-1)(tdf
+tdr)/2, and the output waveform is the inverse of the input waveform.

An embodiment of the waveform shaping circuit of the present invention obtained from the delay time relationship described above will be described below with reference to FIGS. 4A to 4E.

FIG. 4A is a diagram showing the configuration of a waveform shaping circuit according to an embodiment of the present invention, in which the transistor 17 is a PNP type transistor forming a carrier injection mechanism section, and the signal source 24 in FIG. The input pulses shown are transmitted through transistors 25 and 29, which are inverter transistors.
are applied to the base of each.

In this embodiment, the inverter transistor is transistor 2.
The circuit is composed of a circuit in which transistors 5, 26, 27, and 28 are connected in cascade in four stages, and a circuit in which only transistors 29 are connected in one stage.

The emitter 18 of the transistor 17 is a terminal for supplying power and supplies constant power, and the collector of the transistor 17 is connected to inverter transistors 25, 26, 27, 28, 29, and inverter transistors that do not constitute a cascade connection circuit. Furthermore, the collectors of inverter transistors 28 and 29, which are the final stages of the two cascaded circuits, are both connected to the base of inverter transistor 32.

First, the pulse applied to the transistor 25 is sequentially transmitted to the transistors 26, 27, and 28, and the input to the collector 30, which is the output terminal of the transistor 28, is delayed by 2 (tdf+tdr) as shown in FIG. A signal with the same waveform as the coupler appears.

Further, at the collector 31, which is the output end of the transistor 29, a signal appears that is inverted with respect to the input pulse and delayed by tdr or tdf, as shown in FIG.

Here, if we pay attention to the base of the transistor 32, when the transistors 28 and 29 are cut off, the collector 30
When 31 and 31 are at a high level, the current supplied from the collector of the transistor 17 flows into the base of the transistor 32 and saturates the transistor 32, so that the output terminal, the collector 33, becomes a low level.

On the other hand, when at least one of transistors 28 and 29 is saturated and at a low level, transistor 17
The current supplied from the transistor 28 or 29 flows to the saturated transistor and no longer flows to the base of the transistor 32, so that the transistor 32 is cut off and the collector 33 becomes a high level.

That is, when the inputs from the transistors 28 and 29 are both at high level, the output terminal of the collector 33 of the transistor 32 is at a low level, and at other times, the output is at a high level.

Therefore, when the input pulse shown in FIG. 6B is applied from the signal source 24, the collector 33 of the transistor 32 receives
As shown in the figure, an output pulse signal is obtained which is delayed by tdr from the rising edge of the input pulse signal and has a pulse width of (tdr+2tdf).

By the way, the pulse width of this output pulse signal is determined by the delay characteristics and the number of transistors used, that is, by the circuit elements, regardless of the input pulse signal.

In this embodiment, the number of even-numbered stages is greater than the odd-numbered stages, but conversely, when the number of odd-numbered stages is greater than the even-numbered stages, an output pulse is obtained at the rising edge of the input pulse signal.

Therefore, in general, the output pulse width obtained from a waveform shaping circuit composed of m even-numbered stages and odd-numbered n stages of inverter transistors is (■) when m>n.

Now, as already mentioned, the delay times tdf and t
dr is P forming the carrier injection mechanism section.
Since it is inversely proportional to the power supplied to the emitter 18 of the NP transistor 17, in the past it was not possible to continuously control the pulse width determined by the circuit constants, but once the circuit is manufactured, the pulse width of the output pulse can be controlled. By simply controlling the power supply, it is possible to control the power continuously and electronically as desired.

As explained above, there is a circuit formed by connecting an odd number of inverter transistors in cascade, each of which is supplied with a control current from one main electrode of the transistor forming the carrier injection mechanism, and an even number of inverter transistors. one main electrode of the inverter transistor in each final stage of the circuit formed by cascade-connecting the inverter transistors is connected to the control electrode of the other inverter transistor, and each input of the two cascade-connected circuits is the same, Furthermore, the waveform shaping circuit of the present invention is characterized in that an output pulse is extracted from one main electrode of the other inverter transistor by supplying power to the other main electrode of the transistor forming the carrier injection mechanism section. It does not require a capacitor and has a completely different structure from conventional ones. Moreover, it can be integrated at low cost by using conventional manufacturing technology as is, and furthermore, it can be easily integrated into a continuous circuit by simply controlling the power supply. It is possible to obtain a pulse waveform having a desired pulse width, and is of very high practical value.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram for explaining the principle of IIL, Fig. 2 is a diagram showing the relationship between IIL supply power and transmission delay time,
3A to 3C are diagrams explaining the principle of the waveform shaping circuit of the present invention, and FIGS. 4A to 4E are circuit diagrams and operation diagrams showing one embodiment of the waveform shaping circuit of the present invention. 17... PNP transistor forming carrier injection mechanism section, 18... Power supply terminal, 24... Input signal source, 25 to 29, 3
2... Inverter transistor, 33...
...Output terminal.

Claims (1)

[Scope of Claims] 1. A circuit formed by cascading an odd number of inverter transistors, each of which is supplied with a control current from one main electrode of a transistor forming a carrier injection mechanism, and an even number of the inverter transistors. a circuit formed by connecting two inverter transistors in cascade;
and another inverter transistor different from that for forming two cascaded circuits, and one main electrode of the inverter transistor in each final stage of the two cascaded circuits is connected to the control electrode of the other inverter transistor. and each input of the two cascade connection circuits is the same,
Furthermore, by supplying power to the other main electrode of the transistor forming the carrier injection mechanism section, the other main electrode of the other inverter transistor has a pulse width shorter than the input signal. A waveform shaping circuit characterized by extracting delayed output pulses. 2. The waveform shaping circuit according to claim 1, characterized in that the power supplied to the main electrode is made variable.