JPS5885995A - Storage device - Google Patents

Abstract

PURPOSE:To protect a storage device from a high voltage terminal, by having a series connection among the 1st protecting resistance, a voltage supply terminal connected to a writing circuit via the 1st protecting resistance, a gate which conducts in case no writing is required to all writing circuits, and the 2nd protecting resistance respectively. CONSTITUTION:A series matter of the 2nd protecting resistance 61 and N type MOSTR62 and an NOR gate 63 are added to a 2-bit PROM circuit containing a high voltage supply terminal 10, the 1st protecting resistance 20, writing data input terminals 31 and 32, and storage unit elements 41, 42, 51 and 52. When the terminals 31 and 32 are set at a low level with the TR41 and 42 turned off and a mode in which no data is written, the TR62 is turned on since the input of the gate 63 is at a low level. Thus the voltage divided by the resistances 20 and 61 is applied to the TR41 and 42. As a result, a storage device can be protected from a high voltage terminal even in case the writing is not required for all writing data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and more particularly to a protection circuit for a high voltage terminal in a programmable read-only memory integrated circuit that writes data using a high voltage.

Traditionally, programmable read-only memory (hereinafter referred to as FR)
(abbreviated as OM), a protective resistor is inserted between the high voltage terminal and the internal circuit to protect the input of the high voltage terminal.

FIG. 1 is a circuit diagram of an example of a conventional FROM.

The circuit is a FROM part with a storage capacity of 2 bits made up of N-type MO8 (metalized oxide semiconductor) transistors, and only the parts necessary for writing high-voltage data are written, and other reading Necessary parts are omitted. By this, NIIMO for writing
8) Programmable Nl for transistor 41 and memory! A pair with MOS transistor 51 becomes one memory unit element. High voltage input terminal 1 ohm, protection resistor 2 ohm
This is for applying a high voltage internally during data writing. Nl for writing! MOS) transistor 4
1.42 has its source connected to the common protection resistor 20, and its gate is connected to the write data input terminal 31.3.
2, respectively. Programmable NIIMOS) transistor with floating gate 51.52
Both have their gates connected to the protection resistor 20, their drains connected to the sources of N-type MOS transistors 41 and 42, and their sources both connected to ground (GND). These transistors 51 and 52 have floating gates, and once the transistors are turned on with a high voltage, charges are accumulated in the gates and are subsequently released by ultraviolet rays. Since the ON state continues unless the switch is turned on, data can be stored. When a high voltage is now applied to the input terminal 10, this high voltage is applied to the drains of write N-type M0.8) transistors 41 and 42 and the gates of programmable N-type MO8) transistors 51 and 52 through the protection resistor 20. Ru. At this time, N type MO8 for writing? If the transistor 41 is ON, the programmable NllMOS transistor 51
A high voltage is applied between the source and drain of the device to write data. If writing N type MO8) transistor 41
If it is OFF, no data will be written to it. Also, write NIIMO8) transistor 42 is ON.
If so, programmable MO8) transistor 52,
Data is written. As described above, a high voltage is applied to the input terminal 10, and the write data input from the input terminals 31.32 is applied to the write N-type MO8) transistor 41.4.
Program data by turning 2 ON and OFF. In a mode in which either one or both of the write N-type MOS transistors 41 and 42 are turned on, that is, in a mode in which data is written to one or both, noise of several volts or more is applied to the input terminal 10 for a short time. Even if the protection resistance 2
゜, writing N-type MO8) transistor, programmable N-type MOS transistor 41.51 or 42.5
2 or the equivalent resistance when both are turned on, a divided voltage is applied internally, so the internal circuit can be prevented from being destroyed. However, when both write N-type MO8) transistors 41 and 42 are OFF, that is, when all write data is in a mode in which no data is written, the protective resistor 20 and the ground (GND) are disconnected, so the number of When noise of volts or more is applied, it is applied directly to the inside without being divided, so the protective resistor 2o becomes useless and the internal circuit may be destroyed.

As described above, the conventional FROM has a drawback in that when data is written by applying a high voltage, the overvoltage protection of the high voltage terminal may depend on the written data and the protection resistor may not be useful.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to effectively perform input protection regardless of write input data, for example, by adding a protective resistor electrically connected between the write circuit and GND to the conventional circuit. More specifically, the present invention provides a storage device for a programmable read-only memory integrated circuit.

The present invention includes a plurality of memory unit elements, a terminal for inputting a write voltage for writing data to the memory unit elements,
A first interposed between these terminals and each memory unit element.
In the storage device, a series body of a gate and a second protection resistor is connected in parallel with the storage unit element and is conductive when there is no need to write data to all of the storage unit elements. A storage device characterized in that it is connected.

That is, the present invention provides a connection between a first protection resistor, a write voltage supply terminal connected to the write circuit via the first protection resistor, and the write circuit and, for example, GND only when all write data inputs do not involve a write operation. and a control circuit for electrically connecting the second protection resistor to the first protection resistor.

The present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram of one embodiment of the present invention. This circuit is a 2-bit FROM part composed of N1MOS) transistors, and includes a high voltage supply terminal 10, a first protection resistor 20, write data input terminals 31 and 32, and NaNO
2) Two memory unit elements consisting of transistors 41 and 42 and N-type MOS transistors 51 and 52 having a 70-ring gate are connected in the same manner as in FIG. A NOR gate 63 connected in series with the N-type MOS transistor 2 is added. When N-type MOS) transistor 2 is turned on, the sources of write NIIMO 8) transistors 41 and 42 are connected to the first transistor.
A voltage divided by the protective resistor 20, the second protective resistor 61, etc. is applied. The output of NOR gate 63 is N type MO8)
It is connected to the gate of transistor 2, and its input is connected to input terminals 31 and 32.

Now, high voltage is supplied to input terminal 10, and input terminal 3
When 1 or 32 is applied, the output of NOR gate 63 becomes low level and 62 is turned off.
No current flows through the second protection resistor 61, and the write N! M
O8) When the transistor 41 or 42 is ONL, data is written to the programmable N-type MO8 transistor 51 or 52. However, if the input terminals 31 and 32 are both at low level, the writing NIIMO8) transistors 41 and 42 are both turned off, and the mode is such that no data is written. However, since both input terminals of the NOR gate 63 are at low level, Its output is high level (9N type MO8)
Ranjistaro 2 turns on. When all the write data is in mode 0 where no data is written, even if noise of several volts or more is applied to the input terminal 10, the internal voltage is divided by the first protection resistor 20 and the second protection resistor 61. Since the reduced voltage is applied to the device, it is protected and can avoid destruction.

As described above, in the past, the protection device did not play its role when it was not necessary to write all of the write data, but with the present invention, it is particularly effective when it is not necessary to write all of the write data. By adding a working protection circuit, it is possible to obtain the effect that no matter what the written data is, it is protected from the high voltage terminal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a conventional FROM, and FIG. 2 is a circuit diagram of an embodiment of the present invention.

Claims (1)

[Claims] The memory unit comprises a plurality of memory unit elements, a terminal for inputting a rounded write voltage for writing data to these memory unit elements, and a first S resistor interposed between these terminals and each of the memory unit elements. In the memory device, a series body of a gate and a second protection resistor, which is conductive when there is no need to write data to all of the memory unit elements, is connected in parallel with the memory unit elements. storage device.