JPS5885844U - communication circuit - Google Patents
communication circuitInfo
- Publication number
- JPS5885844U JPS5885844U JP18003281U JP18003281U JPS5885844U JP S5885844 U JPS5885844 U JP S5885844U JP 18003281 U JP18003281 U JP 18003281U JP 18003281 U JP18003281 U JP 18003281U JP S5885844 U JPS5885844 U JP S5885844U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay
- transmitting
- delay time
- band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の１実施例に係る通信回路の回路構成図
でａは送信回路、ｂは受信回路を示し、第２図は第１図
の送信回路の遅延時間の周波数特性（実線）および受信
回路の遅延時間の周波数特性（破線）である。
１１．１□、・・・、 Ｉｎ、 ！ｈ、 ５□、
・・・、５ｎ：バンドパスフィルタ、２１，２□、・・
・、２ｎ、６．．６□、・・・。
６ｎ：遅延回路、３．７：加算器、４：出力回路。Fig. 1 is a circuit configuration diagram of a communication circuit according to an embodiment of the present invention, where a indicates a transmitting circuit and b indicates a receiving circuit, and Fig. 2 shows frequency characteristics of delay time of the transmitting circuit shown in Fig. 1 (solid line). and the frequency characteristics (dashed line) of the delay time of the receiving circuit. 11.1□,..., In,! h, 5□,
..., 5n: band pass filter, 21, 2□, ...
・, 2n, 6. ．． 6□,... 6n: delay circuit, 3.7: adder, 4: output circuit.
Claims (1)
の周波数帯域に分割する複数個のバンドパスフィルタと
、これらのバンドパスフィルタのそれぞれに接続されそ
れぞれ遅延時間設定が可変の遅延回路と、これらの遅延
回路の出力を合成して出力する加算器とを備えた送信回
路と、この送信回路の出力を伝送する通信路と、この通
信路からの入力に対して並列に接続され前記通信路から
の信号を前記送信回路におけると同様の周波数帯域に分
割する複数個のバンドパスフィルタと、これらのバンド
パスフィルタにそれぞれ接続され前記送信回路における
遅延時間との和がそれぞれの周波数帯域において一定値
となる遅延時間の遅延回路と、これら遅延回路の出力を
合成して出力する加算器とを備えた受信回路とを具備す
ることを特徴とする通信回路。A plurality of bandpass filters connected in parallel to the input and dividing the input analog signal into a plurality of frequency bands, a delay circuit connected to each of these bandpass filters and each having a variable delay time setting, and a transmitting circuit comprising an adder for synthesizing and outputting the outputs of the delay circuits; a communication path for transmitting the output of the transmitting circuit; a plurality of band-pass filters that divide the signal into frequency bands similar to those in the transmitting circuit, and a delay time in the transmitting circuit connected to each of these band-pass filters, the sum of which is a constant value in each frequency band; What is claimed is: 1. A communication circuit comprising: a delay circuit having a delay time of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18003281U JPS5885844U (en) | 1981-12-04 | 1981-12-04 | communication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18003281U JPS5885844U (en) | 1981-12-04 | 1981-12-04 | communication circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5885844U true JPS5885844U (en) | 1983-06-10 |
Family
ID=29976262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18003281U Pending JPS5885844U (en) | 1981-12-04 | 1981-12-04 | communication circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885844U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5039401A (en) * | 1973-07-02 | 1975-04-11 |
-
1981
- 1981-12-04 JP JP18003281U patent/JPS5885844U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5039401A (en) * | 1973-07-02 | 1975-04-11 |
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