JPS5885627A - Analog/digital converting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to data acquisition for digital systems, and more particularly to analog to digital data conversion.

The most important and most difficult of all interfaces between disparate types of systems is usually the link between the analog and digital parts of the system. The interface between digital and analog circuits includes digital-to-analog conversion circuits or D/A converters. Similarly, the interface between Amerolog circuits and digital circuits is
Contains converter. An ideal A/D converter is one that can convert an analog signal to a digital signal without delay or error. Of course, such an ideal converter has not yet been created. However, A/D converters that require some delay and have limited accuracy do exist, but are expensive depending on their accuracy and processing speed fK. Many techniques exist for performing A/D and D/A conversion. Multiple A/D and D/A
One of the papers explaining the conversion technology is Burner R.
1K1 of Circuit Systems, published in July 1978, entitled "Linear electronic device analog/digital conversion structure and its origins, peripherals, limitations, and applications" by Gogen.
There is one published in 1tK newsletter OA vol.8-25. Another passage in the same publication also refers to the MO8 analog-to-digital converter. The paper was published on July 7, 1978.Circuit and System Engineering 1! ! I! XI! ! Newsletter ah
Ball R, Gray and Debits R published in Volume S-25
It is entitled "All MOEI-type Analog-to-Digital Conversion Technology" by G. Hopps. This paper is %
shows the technique used in the present invention under the heading Integrated Circuit Continuous Approximation Conversion Device. This technology is 19
MFIM annual report on solid-state circuits published in December 1975 5a-10
Published in Volume 1, there is also an earlier paper by Paul R, Gray as presented in a paper entitled "All-MOa-type charge resolution distribution analog-to-digital conversion technology" by James L, McCreary and Ball R, Gray. Includes charge resoist repetition technology. This charge resolution distribution technique utilizes a bank of weighted capacitive elements. The problem with using weighted capacitive elements is that the manufacturing accuracy cannot guarantee the accuracy required for the application. In the past, capacitive elements have been trimmed to provide acceptable accuracy. One technique with resistors and capacitive elements that can obtain a higher degree of resolution was published in 1979: OCMM International Journal of Solid State Circuits, page 186, IIl! [INMO Day 1] by Graham Huotohi and David A.
2b monotonic 25 microsecond D/D converter]. This technique discloses the use of resistor banks to efficiently vary the charge of capacitive elements. Another error correction technique is [Error correction 14 bits 20 microseconds 0M0] by Aiya G, & Yashishira, Baselware and Peter D, Deratsugesho.
It is disclosed in a single sentence titled 8M/D Converter J (1981 Engineering KKII! Journal of the International Society of Solid State Circuits).

This technique includes a redundant D/A and an error correction circuit that uses continuous approximation registers.

According to the invention, the reference human power, analog input, binary weighted capacitive element, resistor connected in series within the resistor array, same as the smallest capacitive element in the binary weighted capacitive element array. An analog-to-digital conversion circuit is provided having a least significant bit capacitive element with each 'jit' and a comparator circuit having 24 inputs and an output indicative of the voltage difference between the two inputs. A first switch is connected between the reference input and the upper electrode of the capacitive element array. A second switch is connected between the reference input and the first input of the comparison circuit. 5cale capacitor
) is also connected to the first power of the comparison circuit. A third switch is connected between the least significant bit capacitive element, the analog input and the resistor array. The switch 'I44 is connected between the analog input, the reference input and the lower electrode of the capacitive element array. A data register for storing the digitized value of the analog human input is also provided along with a correction circuit and a microcomputer.

The microcomputer processes the charge by a set of instructions to modify the charge in the element array, and
Any deviation of the capacitance value away from the base weighted value is compensated for. The microcomputer then uses the capacitive element array to determine the most significant bit value of the digitized value of the analog input. Microcomputers also use the same resistor array to determine the least significant bit position of the analog input. The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a diagram illustrating a voltage to digital signal converter. The input to the converter is VRH
(voltage input). Reference voltage VRH and VRL
defines the range of digitally quantized voltages.

That is, if WIN > VRH, the output of the converter will be 3 FFF in hexadecimal, and L WIN
= (VRH-VRL)/2, the output of the converter is 2 data in hexadecimal; if WIN <,
If VRL, the converter output is hexadecimal yy
It is 5sw. The converter uses single-load redistribution technology to transform the voltage input VIN. This converter consists of an array of eight capacitive elements 5-12 and a capacitive index 13 of the second bit from the least significant bit (i.e., a capacitive index 13 whose capacitance tl[is equal to the capacitance of the least significant bit in the capacitive element array). ) in the resistor array 26'.

By the combination of resistor arrangement and capacitive element,
The columns allow an additional 6 bit resolution and the capacitive elements provide an 8 bit resolution. In order to explain the Rezoist distribution technology individually, the reader should refer to 1.
Paul, R. Gray and David A. Hodges, published in the report on IKKK circuits and systems, CAB-25, No. 7, published in July 1978 and published in December 1975. I BEK Solid State Circuit Journal Vol. 5a-10 No. 6 by James L. McCreary and Ball R. Gray [
Please refer to all MOS-type charge resolution (knee analog-to-digital conversion technology). Both of these papers are included here for reference. The circuit in Figure 1 is
In order to correct the charges charged in the capacitive elements in the capacitive element array in cooperation with the 8-bit microcomputer 22 connected through the circuit [21], the addition M of the capacitive elements (or the value of the capacitive elements) is accurate. It has an error circuit 27' which distributes it in binary numbers. In other words, according to the Rezoist distribution technique: 1. The total goodwill of the entire array is C1
In this case, the capacitive element 5 takes the value CT/2, the capacitive element 6 takes the value CT/4, and the capacitive element 7 takes the value CT4, and the following are similarly divided. A circuit 27 and microcomputer 22 connected to the output of the comparator circuit 4 determine the weighting error of each capacitive element in the array and determine the correction value necessary to correct the weighting of each capacitive element in the array. ing.

To perform the correction, the change in each capacitive element is one at a time.
is weighted. First, by applying a voltage to the line 28, the MO8FFiT switch elements 1 and 2 become conductive, and the line #vct is set to 'VR11. When switches 1 and 2 are then closed, line VQ becomes floating. (Therefore, it is effectively set to VRH.) Capacitive element 12
is set to 1, that is, the switch 38 for the capacitor 12 is set to VRH. Meanwhile, switch 31
-37 and 39 are set to VRL. VQ is then reset to VBH via switch 2 as before. The capacitive element 12 is set to VRL K, and the capacitive element 13
are set to VRH via switches 38 and 39, respectively.

If these capacitive elements are made with the same size as planned, the VQ point will not change from VRH'.

However, the deviation of VQ away from VR)I is clearly K from the output of comparator circuit 4, which compares vQ input via line 29 with VRH on line 30.

The correction circuit is initialized to a zero correction coefficient at this point,
It should be noted that any voltage difference created by an error occurring in capacitive element 12 appears on line VQ. The error correction hardware 21 controlled by the microcomputer 22 uses a binary search algorithm. This Al prism changes the voltage of vQ by changing the values of the capacitors 14-17 connected from the resistor array 26 and the error circuit decoding hardware 18. This is stored in an 8-bit word error register 20. by the microcomputer. This is done by loading it into The six most significant bits are connected to a resistor array 26 and provide a VGLK charge via a capacitor 13 through a switch 3!1. bottom 2
The bits are decoded by error decoding bar Vware 18 and provide charge to capacitive elements 14-17. When a corrective charge is added to (or removed from) VQ, the output of comparator circuit 4 becomes invalid or zero. The resulting error word is stored as a correction factor for that particular capacitive element. After capacitive element 12 has been modified, capacitive element 11 is modified using both capacitive elements 12 and 13.

The sum of the parallel capacitive elements 12 and 13 becomes the planned value of the capacitive element 11. A modification factor for capacitive element 12 is used. The capacitive element 11 is set to VRH, and the capacitive element 12
and 13 are set to VRL K.

Historically VQ is reset to VRH as before. Since the corrected charge values for elements 12 and 13 have already been stored, error register 20 is reset to zero.

Capacitive elements 12 and 13 are further set to [VR]I, and capacitive element 11 is set to VRL.

The difference between the value appearing on VQ and VRH indicates an error and the error is zeroed out by microcomputer 22 using a binary search algorithm using error correction coefficients for all eight capacitive elements in the array.

This button completes the error acquisition phase.

There are two sources of error in the structure of the invention shown here. The above error correction factors only calculate the weighted error for one source, ie the individual capacitive element. Another source of error is that caused by voltage changes at P41 during the conversion sequence. Both of these sources are calculated by calculating the error conversion correction coefficients below. i.e. Ot/21-0°1 where C1 is the sum of all error correction coefficients, 1 is the sum of the weights for the individual capacitive elements (in this case MSB = 1, MOB + 1 = 2, LE
IB = 8)01 is the individual error correction factor for the specific capacitive element.

The error conversion correction coefficients are calculated within the microcomputer 22.

The converter is now ready to digitize the analog input voltage applied on line VTN.

The conversion process consists of three stages. namely, sampling, set-up, and resolution distribution.

During the sampling phase, as shown earlier, VQ is V
It is set to Rll. The lower electrodes of capacitive elements 5-13 are connected to VTN via switches 31-391, respectively. During the setup phase, the comparator circuit 4
is cleared, switches 1 and 2 are turned off, and all capacitive elements 5-13 are switched to vRHK. During this initialization period, the voltage at node 41 is VRH+ VRH-
Takes the value of VTN. During the resolution phase, the error value of the capacitive element 5 is loaded into the error register 20 and the capacitive element switch 31 switches the capacitive element 5 to VR.
Connect with I. Whether the voltage at No.P41 is less than the reference voltage (if so, the bit is 1) or is equal to or greater than the reference voltage (if so, the bit is G). This determination is made by a comparison circuit.

If the bit is 1, the capacitive element remains connected to VRL. If it is not 1, the capacitive element is reconnected to the VRH as described in the redistribution technique above. If capacitive element 5 is connected to VRH, error conversion correction coefficients are retrieved from the error register. If capacitive element 5 is connected to VRL, this error conversion correction coefficient is summed with the error conversion correction coefficient of the next capacitive element 6 and input into error register 20. The same steps described above are repeated as described above with the charge reso-rist distribution technique. A capacitive element with a bit value of 1 has its own error conversion correction coefficient taken out from the error register 20, so when the charge resolution distribution sequence is completed, the error register 2
It must be noted that the sum at 0 is:

Here, B indicates a bit value. OT indicates the total error correction coefficient. 1 indicates the weighted position of each capacitive element. (
where M2R=1 and L8B=8) 01ci denotes the error correction coefficient of the individual capacitive element.

Even in the first pressure, the size of the switch 1 and the capacitive element 3 connected thereto is measured in relation to the switch 2 having the capacitive element array. This is required as a means of solving the accuracy problem caused by voltage-dependent capacitive coupling from the r-to-source/F-rain of the MO13 transistor switch. Since the capacitance of the capacitive element array is large, the size of switch 1- is large and the resistance value of switch 1 needs to be low in order to obtain a fast sample "4".

Charge is charged from switches 1 and 2, the capacitive element array switches having a linear relationship to the change in date voltage and a non-linear relationship to the source/bilay in potential of these switches. More generally, the decoupling voltage is a function of the reference voltage and analog human power. Since the analog input is unknown, its effects must be canceled out. This is done by sequentially closing the switches.

By closing switch 2 before all switches 31-39 are closed, charge is accumulated on the upper electrode of the capacitor array. The decoupling voltage, which is a function of the reference input, is made negligible by making the size of the switch 1 and the capacitive element 3 a predetermined ratio to the size of the switch 2 and the capacitive element 5-13 array. I can do it. That is, when capacitive element 3 has a capacitance of IA4 in the arrangement of capacitive elements 5-13, switch 1 is constructed to have f-)/drain capacitance that is l/14 of r-t/drain capacitance of switch 2. It will be done. This is possible by selectively sizing the two switches. #! The combined voltage is then differentiated and applied to the comparator circuit 4, where it is canceled by the common mode blocking function of the comparator circuit.

It should be remembered that resistor array 26 and capacitive element 13 are used during both the error acquisition and correction phase and the transformation phase. The resistor array 26 has 64 intermediate junctions (Ltap) dedicated to the conversion phase, which connects these intermediate junctions via the line 24 to a 6-bit shift register 23 containing the 6 least significant bits of the digitized value of the voltage. It is connected. The resistor array 26 is
It has an additional 64 intermediate points connecting to the middle of the previous 64 intermediate points. The second set of .64 intermediate nodes are connected to the error register 10 via line 19. Two additional bits of error register 20 are connected to error decoder 18 previously described. This configuration allows a single resistor array 26 to perform two separate functions: error acquisition and correction and conversion.

The configuration of this converter differs from the conventional technology in the structure of the capacitive element/resistor. Traditionally, the resistor array is
The capacitor array was used to determine the most significant bit position, and the capacitive element array was used to determine the least significant bit position. An advantage of the disclosed structure is that it reduces loading on the resistor array and increases the speed of conversion.

A drawback of the disclosed configuration is that it may become unstable due to the error in the capacitive element array. This drawback is
This is eliminated in the present configuration by the error correction sequence. The second difference from the conventional technology is that the resistor array 2
6 is fabricated using polysilicon interconnects rather than N-type diffusions.

By using this polysilicon, it is possible to avoid irregularities in operation due to the influence of voltage on conductivity due to the use of N-type diffusion.

FIG. 2 shows converter 51 in block diagram form, with the inputs to converter 51 being 15 volts on line 52, VRH (i4 reference voltage) on line 53, and WI on line 54.
N (voltage input), on es S & CVRIJ (low reference voltage), signal ground potential on line 56 plus line 57
The top has a chip ground potential.

IIM5B and 59 are 8-bit parallel input/output ports, and this port is a human power/output port numbered 60 and 610, respectively, and the microcomputer 63.
Connect to. Interconnected to a microcomputer 63 to allow data and address transfer between converter 51 and microprocessor 63, the output of converter 51 is included in fourteen parallel 1gI lines 62. In operation, the VRH can be set to 2 to 10 delts of darkness according to the preferred embodiment. VRL in the preferred embodiment is V
It is set between 5 volts from Off so that it does not overlap with RH. The voltage input on line 24 is the aforementioned V
It is digitized between the values of P, L and VRH.

FIG. 6 shows the on-chip layout for a test example of converter 51. The B boat is located at position 77 on chip 75 and the C boat is located at 76. B
The board is used as a memory controller for the memory contained in the microcomputer off-chip. The 0 port serves as a multi-address data port for memory addresses and memory data from the off-chip microcomputer. Area 78 represents the 14 line outputs of the converter, and area 79 represents the analog interface, including the previously mentioned ground potential and -DC inputs VRH, VRL. This test structure actually has six separate converters 80, 81 and 82.

Converter 80 includes a metal/RFiOX/Mout type capacitive element that includes a grown phosphorus-containing oxide. Converter 81 is a converter having a polysilicon putative oxide with a high dose implanted channel. Converters 80 and 81 both have resistor arrays. Converter 82 is a polysilicon resistor array converter. The separate separation of the six converters 80, 81 and 82'Y on chip 75 is for experimental purposes. In the manufacture of A/D converters, preferred embodiments include either metal converters or polysilicon converters on a single chip, connected as schematically shown in FIG. Metal converter 80 and polysilicon converter 81 each have eight separate resistors. first two registers 85.8
6 is a control register, which controls the operation of each converter. Polysilicon converter 8
The corresponding registers on 1 are registers 91 and 9.
It is 2.

The next two registers 8T and 8B are data registers corresponding to registers 25 and 23 in FIG. Corresponding registers in polysilicon converter 81 are registers 93 and 94. metal converter 80
The register 89 in is a temporary register that temporarily stores data sent from the microcomputer. The register corresponding to this in the POIJ converter 81 is the register 95. The register remaining at i#*''' in metal converter 80 is register 90, which corresponds to error register 20 in Figure 5g1.

The error register within polysilicon converter 81 is register 96. Polysilicon resistor converter 82
is one register 9 corresponding to register 23 in FIG.
It has 8. All these registers are B boat 77
It can be adjusted by a microcomputer through a C port 76 under the control of the microcomputer. A sent from the microcomputer along with the address through the B boat 77
The LATOH signal is a metal converter 80 or a decoder 97.
Alternatively, it is sent to a decoder 84 to be provided to a polysilicon converter 81. The mu LATCH specifies whether the information sent from the 0 boat is address information or data information. When an address is sent from the 0 port, it is decoded by either decoder 84 or 97 and selects one of six registers in either metal converter 80 or polysilicon converter 81. . Once selected, this register
It is possible to write to and read from the microcomputer through the C port. An additional register 83 is added, which registers the six converters 80, 81,
82 serves as an interpretation register that determines which of the 82 will perform a test operation. Polysilicon converter 82 has register 981 also addressed from the microcomputer through the 0 port.

FIG. 4 shows a preferred embodiment of a semiconductor chip configuration using the converter of the present invention.

FIG. 4 shows a chip 101 with a microprocessor section 99 connected to an analog/digital converter 102.
It shows. This analog/digital converter 10
2 is further connected to a small microcomputer 103. Small microcomputer 103)-1 This microcomputer 103 is a simplified version of the microcomputer 99, and this microcomputer 103 simply uses a small amount of memory or registers, and performs error correction and conversion by executing arithmetic operations in sequence with ALtT. It has a small capacity ROM for control. In this configuration, chip 101 sends an analog voltage input to analog/digital converter 102, and the input data is provided to microprocessor 99, which further converts it into a digital output voltage and sends it out.

FIG. 5 illustrates the B boat interface to chip 75 shown in FIG. The B-Boat corresponds to the B-Boat of a microprocessor.

The special micro 7″9 setter used in this example is disclosed in U.S. Special Application No. (T1-8922).
and is incorporated herein by reference.

Boat B is 8FT, 0NVT/AQI! i,
NR8T, NO8, AL.

It has seven parts marked R/'W, EN. 5IFT Patsuge receives shift commands from the microprocessor. 0NVT/AQIe indicates that the device being tested is in conversion mode, i.e. t pressure at analog input =
It specifies either the mode for converting 0 into a 14-bit digital word or the error acquisition mode described above. NR8T pad V is a reset pad that is an active low potential for the device. NO8O8 is a chip selection pad that is a para-active low potential. Selection of the chip places all input and output ports on the chip into a high impedance state. The AL pad receives a MLATOH signal that specifies whether the information present on the C boat is an address or data.

The R/W specifies whether the information access operation performed by the microcomputer is a read or a write. The KN signal is an active low voltage signal.The logic circuit in area 110 generates a shift signal for either the polysilicon converter or the metal converter or the test converter, which is determined from the shift signal sent from the microcomputer. It generates individual selection signals indicating which converters are selected and a clamp signal, which will be described later. Note that the NO8 line or chip select active low potential line is the input to stop the chip from operating when the chip is not selected. The logic circuit in area 111 generates the VQ line reset signal VQ, R8T and resets SV vQ times in FIG. The reset signal given from this microprocessor generates an internal reset signal together with the converter 4g and chip selection signal. Logic circuitry corresponding to area 112 receives ALATOH, a chip select signal, a read/write signal, and generates a data input signal NPD and a data output signal NPDQ, respectively. These signals are O
Used as input/output control signals sent to the boat.

The NRAlli and NWA1 lines serve as the bus A active and bus A active write signals, both -1 and active low, allowing writes to and reads from the bus within the boat. j! K after 1.

The ALT and ALF lines are used as ALATOH true and ALATOH false signals to feed the control registers for the converter.

FIG. 6 shows the C-vote and selection registers. C
The port has 14 bits and the logic is shown only for D14. The C-boat is connected to a D-bus 120 consisting of 14 lines.

Remember that D14 is loaded onto pad DI4 under the control of the ≠ knob select active low potential signal that puts the board in a high impedance state when no chip is selected? It has to happen. Also,
Also shown is an #i embedded circuit that inputs information onto the A bus on the D path in accordance with a signal indicating HDTA, ie, input high potential data kA, or a signal LDTA, ie, input low potential data kA. Data that is output on the C port by this logic circuit is output through the 0 port when needed. Selection register 1 connected to bus 121
22 is also shown. The selection register 122 is set to ALATO), which is indicated at bit position A51. 7 stored within
Contains bit information. This latch is controlled to read and write the selection register 122 by two signals: the SLF module selected from the A bus and the SL'l'A IC selected for the A path. Note that bit positions have specific output names in selection register 122. NMB is a metal converter selection signal and is an active low potential. NPB is a polysilicon converter selection signal and is an active low potential. NT day is the test converter selection signal and is an active low potential. R]1li13 OL is a decomposition bit. N(3
The MFT is active low on the conversion bit signal. N
8MPSL is a sample selection signal and is an active low potential.

NOF'8TO is an offset selection signal and is an active low potential. These control signals select and test constrained hardware within the comparator circuit.

FIG. 7 shows the C port, which is an 8-bit input/output port that connects to the microcomputer. Each of the 8 bit positions is identical to the bit position shown as C521 with input and output pads. This cy3 position has an NPD input, that is, a hoard data input, and an NP
It includes inputs and outputs controlled by logic connected to the DO or port data output.

FIG. 8 shows the code logic circuit for the polysilicon converter. This decoding logic circuit contains 8 bits (A
Note that an address latch with p-A7) is included.゛These lines connect to the A bus and
T, i.e., ALATOH true, and ALAF, i.e., mu LAT
Controlled by the ALATOH signal in the form of CH false, A
The bus external pressure address can be latched. The address signal is then interpreted by program logic array 130 and outputs signal TZXAP.

TOXAP, I! 1DXAP, 0BXAP, RB
They are XAP, EILXA, and RDAO. Note that each separate signal is a dual output indicating whether the signal is true or false. For example, TZXAP means a register that temporarily registers 0 regarding the pass to the polysilicon converter. This signal further becomes two signals, TZFAP, which indicates a temporary register of 0 from the A path to the polysilicon converter, and j_TZTAP, which indicates a temporary register of O from the polysilicon converter to the bus. As explained later, this causes 0
Input/output to the temporary register becomes possible. T
OXAP does a similar thing with one temporary register, which will also be explained later. Similar to the 0 temporary register line mentioned earlier, the TOXAP K@ portion of the circuit also
There will be 062 lines with FAP and TOTAP. IDX
AP is an error digital/analog converter (DAC)
) Controls register input and output. 0BXAP
is controlling the input to the answer'Jlt cunt pit register. RBXAP controls the input and output of the resistor bit register. SI and XA control the selection register mentioned above. The RDAO controls the manpower and output to the test converter.

FIG. 9 illustrates an address latch and address release circuit for a metal converter. Here this circuit is
It must be remembered that the circuit is identical to that shown for the polysilicon converter of FIG. bus 1
The output signals on 35 are the same as those for the 0 temporary register, the 1 temporary register, the error DAC register, the capacitor bit register, and the resistor pit register.

However, other signals i.e. HDTA and LDTA
controls the loading of the contents on the KD bus onto the A bus so that the data is output through the C port. The HD module mentioned earlier means sending high potential data to the path.
LDTA means sending low-level data to the A path.

FIG. 10 illustrates a resistor arrangement that is identical to either a polysilicon converter or a metal converter.

This array 145 serves the dual purpose of error correction and translation, as previously explained. With respect to performing the conversion, an input is received from the line indicated at 144 and applied to the intermediate junction and to the resistor array, and further to the capacitive element 141.
Note that it is connected to Yes. Capacitive element 14
1 corresponds to the capacitive element 13 in FIG. The error correction side receives a 6-bit input from [143]. Error correction has two functions, 2 times 1i1
Note that 46 is the central line for adding and removing charge from the vQ line (Figure 1).

The output at the intermediate junction of the resistor array 145 used to obtain the error value is connected to an error correction logic circuit 142 which in turn is connected to the capacitive element bank 140 . 1st
The capacitive element bank 140 in FIG. 0 is the capacitive element bank 140 in FIG.
, 15, 16°17. These capacitive elements 14
0 is set to increase the resolution of engineer corrections. 6
Bit 143 controls the aforementioned 6-bit error word and controls the charge passing through capacitive element 141.

The remaining two bits in the error register control error logic 142, described below. The capacitive element array itself is a resistor made by bending polysilicon with a length of 5 microns, and has 64 intermediate contacts on one side of the folded resistor, and 64 - intermediate contacts on the other side. Consisting of polysilicon resistors with

One set of 64 intermediate points is dedicated to the resolution registers and the other set of 64 intermediate points connects to the error correction registers described above.

FIG. 11 illustrates the 8-bit error correction register shown in area 20 of FIG. In Figure 11,
Although the 8-bit register is divided into eight parts, please keep in mind that only the circuit for the seventh or most significant bit is shown. The remaining circuitry of the error bit register is the same. The error register is divided into three sections.

The first part, marked TO, is a register that temporarily stores 1's. The second part numbered 150 is a latch for the 0 temporary register. The sixth part numbered 151 is the error digital to analog -
This is a conversion register.

The temporary zero and error digital-to-analog conversion registers are latches in the circuit. The temporary register 1 is just a switch, but serves as a pseudo-register that can load data sounds on the A bus. Referring back to the explanation of the error correction process, the error conversion correction coefficients are calculated by inputting the correction coefficients of the individual registers into the error register 20 shown in FIG.

These registers have a zero bit output according to the charge resolution distribution technique. However, if the comparator output indicates that the bit value of the capacitive element is 1, the error correction coefficient is retrieved from the error register and the total error conversion correction coefficient for the entire capacitive array is not calculated as described above. must not. If the bit value is 1, the output of the comparator circuit itself is the clan f'i!
-, the circuit shifts the comparison result to the next capacitive element. Furthermore, the data on the A bus passes through one temporary register using the pit line, as shown in the figure: A (TOF'A
) is passed through the 0 register to the error digital/analog register. However, if the bit value is 0, the data in the 0 temporary register will be copied in error into the digital/analog register and will not receive input from the 1 temporary register. The 8 bit output of the error register is divided into 6 bits, which are input to the resistor array described above, and the remaining 2 bits are connected to the error correction software shown at area 18 in FIG. This is explained in more detail in Part 1.
This is shown in Figure 2.

FIG. 12 shows a disassembly hardware that receives two inputs on line 160 from the error register and has outputs on four lines 160 for connecting to the capacitive element shown as capacitive element 140 in FIG. Showing clothing. It should be understood that the primary purpose of this error decomposition hardware, shown in FIG. 12, is simply to add two additional bits to the decomposition function of error correction capability. The logic circuit in FIG. 12 has the configuration shown in FIG.
This is to reduce the number of encoding states required to supply charge to 40.

FIG. 16 shows a reset circuit for the comparison circuit.

Before the operating line cuts off the voltage input via line 172, a reset signal R4 is sent from comparator circuit 170, and switch 11T3 and switch 2175 become conductive and close. This is done by a delay in the execution of the seedance in which the signal coming from R4 passes through switch 2, switch 1 and enters the circuit to activate the line. Please note that the switch 2175 and the capacitive element 176 are sized in proportion to one row of capacitive elements 171 of the switch 1173 as explained above. A capacitive element 174 connected to VQ is used to adjust the offset voltage by providing a line ZOA (zero correction adjustment) voltage.

Figures 14 and 15 are a resistor array resistor and a resistor array resistor, respectively. Referring now to FIG. 14, the capacitive element register is divided into six sections. That is, a capacitive element bit register (OBR), a capacitive element data register (ODR), and a capacitive element switch (OSW).
). The capacitive pit register is a storage latch that connects to the A bus and stores specific bit data during error value acquisition and while performing conversions, and is a storage latch that connects to the A bus and stores specific bit data through the 8-bit locations of the capacitive register. The charge redistribution process is executed so that the charge redistribution process continues. Note that when the potential of the reset signal decreases, the 1 that was initially clocked at [A7] is transferred into the circuit by either the SS1 line or the SS2 line K, which indicates a dual-phase non-overlapping clock. That is,
When a 1 is low F into bit position 7 and an ssl occurs, a 1 rolls into bit position 6VC and a 0 rolls into pit position 7. When ss2 becomes a generator, the 1 in bit position 6 rolls into bit position 5, pit position 6 now contains 0, and all pit positions other than bit position 5 become 0. Make it. This bit register is also connected to the capacitive element data register ODH.

The capacitive element data register also outputs the output from the comparator circuit to line B.
Received from IT or NBIT. This output is used in the capacitive element switch to perform switching of the capacitive element into or out of the array as described above in the charge resolution distribution technique. Note that capacitive element 180 is a weighted capacitive element array that connects to the node. Also remember that the output of the capacitive element data register is connected to the D bus 182 mentioned above. FIG. 15 shows a 6-bit register for a resistor arrangement similar to the capacitive element register of FIG. One difference is that while the circuitry contained within 191 performs error correction,
The second least significant bit capacitive element is disconnected from the resistor array.

FIG. 16 shows a shift logic circuit connected to the capacitive element register 25 of FIG. 1''4 and the resistor array register 23 of FIG.
and 882 signals are generated, which causes 1 to shift through the capacitive element register 25 and the resistor register 23, thereby performing a charge redistribution process.

FIG. 17 shows the comparator circuit 4 of FIG.

The comparison circuit is divided into two parts. That is, l! The first section above line 247 is the preamplifier section and the second section below line 247 is the power amplifier section. The preamplifier section has four amplification stages 230, 219, 220 and 221.
Consists of. The individual stages are illustrated at stage 230.
It consists of a common power differential amplifier with two branches 210 and 211. This structure has differential inputs and the output exhibits a differential voltage gain due to the common Mor rejection function. Two inputs given to the comparison circuit are voltage capacitance elements 202 and 206.
The output entering from above through times @204, 207 is times [20
Appears on 9,210. The circuit 215 is installed to make the comparator circuit receive or not receive the reset signal, and when the reset signal is received, the switches 203 and 205 are turned on.
Since the input is effectively clamped to the potential of the output of this stage, this causes the signals present on capacitive elements 206 and 202 to be passed through the output line to the next stage.

Therefore, circuit 216 now switches on the next amplification stage. This process continues in circuits 217 and 218, and this signal voltage is output from the comparison circuit. The capacitive elements in stages 230 and 219 are
The manufacturing process is different from the five capacitive elements 20 and 221. That is, capacitive elements 233, 234, 235
and 236 is a desorption type M that functions as a capacitive element.
O1371! ! While T devices, capacitive elements 202, 206, 231 and 232 are metal polysilicon capacitive elements using multiple oxide layers as the dielectric.

This offset voltage is created by the current mismatch in branches such as 210 and 211.

Even if the two switches 1 and 2 shown in FIG. 1 are scaled to the same size, a slight offset voltage will still remain.

The signal is the capacitive element 202, 206° 231, 232, 23
3, 234, 235, and 236 and through the comparator circuit, the input affected by the offset voltage is then further divided by the gain of all the differential amplifiers.

Note that circuits 216, 217, and 218 actually act as delay circuits that enable the operation of the next stage, KL, so that the offset voltage of that stage can be passed to the next stage. Components 245 and 246 shown at 216
Similarly, circuits 2) 6, 217 and 218 act as delay circuits by means of similar components shown at 217 and 218. 245 is an enhancement type MO8FIliT that functions as a capacitive element, while device 246
is a depletion mMO8FET device that acts as a resistor. This combination of resistors and capacitors is timed such that the time delay rectangle of these circuits is constant and allows offset voltages to be loaded across the various amplifier stages in a sequential manner.

Another feature of the comparator circuit is that it includes circuitry to filter out noise generated from the power supply.

These two power supply bias current circuits are 201 and 202. The first stage differs from the second, sixth, and fourth stages in that the first stage is connected to the stepped body 230 and the bias circuit 201, and is connected from 213 to vda. V can be anywhere between 5 and 15 volts. circuit 2
v(1(l power) at 01 is common source device 2
Manpower is provided within 0B. By using vd(l in the first stage, the possibility of overdrive occurring in this first stage is reduced, and therefore the possibility of overdrive occurring in each subsequent stage is also reduced. In the fourth stage preamplifier section, the power supply section is VO. numbered 214. The bias circuit 200 has the same purpose as the bias circuit 201 except for the second power supply section V0°. The circuit 222 receives the output from the fourth stage preamplifier section and amplifies the bias level of the signal to within the digital range.This cross-coupled circuit receives the output from the comparator circuit while maintaining the gain of the circuit. The true/false signal output from circuit 222 is amplified by circuits 240 and 241. The output of 240 is NBBIT and the output of 241 is marked as BIT. The circuits at 240 and 241 are
The OI shown in the figure is simply two inverter circuits separated by a switch controlled by the AMP signal. The aforementioned OLAMP signal turns off the output of the comparator circuit only when the converter is in reset mode. After the signal sent from the circuit 222 reaches the circuit 240, this signal #1 passes through two inverters 223 and 225, is input to the Bushdel amplifier 227, and generates an output on the NB T line. Similarly, circuit 241 has two inverters 224 and 226 and a Bushsol circuit 228v. These inverters perform the final stage amplification of the signal applied to the comparator circuit.

This comparator circuit is novel in that it allows the use of power supplies of less than 5 volts. However, the use of a 5 volt power supply necessitates the inclusion of the previously mentioned noise cancellation circuitry.

Another novel feature of the comparator circuit of the present invention is that the offset voltage can be made substantially zero by utilizing the self-biasing process described above.

Therefore, according to the present invention, it is possible to create an A/D converter that is closer to the ideal converter mentioned at the outset, where delay time is shortened and errors are minimized by a correction circuit. Therefore, it is possible to provide a means for ideally connecting the analog section and the digital section, which is an important issue in the system.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an analog/digital conversion circuit and its interface to a microcomputer. FIG. 2 is a block diagram of an analog/digital conversion circuit that interfaces to a microcomputer. FIG. 6 is a layout diagram when the present invention is used in an integrated circuit. FIG. 4 is a layout diagram of an integrated circuit including a microcomputer connected to the MU/D conversion circuit. FIG. 5 is a logical diagram of the B person caboto. FIG. 6 is a logic diagram of the B input/output ports and control registers for the A/D conversion circuit. FIG. 7 is a logic diagram of a C input/output port. FIG. 8 is a logic diagram showing one of the control registers with ** logic for conversion circuit 81 of FIG. FIG. 9 is a logic diagram of the control registers for conversion circuit 80 of FIG. FIG. 10 is a schematic diagram of a resistor arrangement. FIG. 11 is a diagram showing an error bit correction register. FIG. 12 is a logic diagram of a circuit for increasing the resolution of the error correction circuit. FIG. 16 is a logic diagram showing a glue circuit for the comparison circuit. FIG. 15 is a logic diagram showing registers for resistor arrays. Figure 16 shows a shift a agent connected to a cap element resistor and a resistor resistor, shifting 11' bits in the register darkness, and executing the charge resolution repetition and error correction algorithm. Fig, 4

Claims (4)

[Claims] (1) a reference input; an analog input; an array of binary-weighted capacitive elements whose capacitance is measured; and a first and second comparator circuit between the first and second inputs; a comparator circuit generating an output indicative of the sensed voltage difference, the second input being connected to the scaled array; connected between the reference input and the capacitance scaled array; a first switch means connected to the first comparator circuit and having a size set in proportion to the array of capacitive elements added by the binary number; a first switch means connected between a reference input and said first comparator circuit input, the first switch means being proportional to the size of said first switch means being related to the ratio of the size of the metered capacitive element to the size of the metered array; a second switch means whose magnitude is scaled; a third switch means connected between said analog signal and said scaled array; and register means; before disconnecting said third switch means; The first and second switch means are turned off by cutting off the conduction of the first and second switch means
and switch control means for controlling the sixth switch means; selectively and continuously comparing and contrasting the measured array capacitive element with the reference input to obtain a digital approximation of the analog input; an analog/digital conversion circuit having means for storing the digital noise approximation value; (2) a reference input; an analog input; a capacitive array of binary weighted capacitive elements; a resistor array connected in series; equal to the minimum capacitance f of the capacitive element array; and a least significant bit capacitor tIA connected in parallel with the capacitive element array; having first and second comparator inputs and an output indicating the existence of a voltage difference between the inputs; a comparison circuit whose input is connected to said capacitive array and said least significant bit capacitive element; a reference valley connected to said first comparison circuit element; a reference input connected to said first comparison circuit element; switch means for connecting an input to said capacitive array; a supplementary charging circuit connected in parallel with said capacitive array for adjusting the charge stored in said capacitive array; and said comparison orthostatic output;
said switching means and said supplementary charging circuit for adjusting the charge stored in each binary weighted capacitive element to a particular binary weighting, and adjusting with respect to said binary weighted capacitive element and a reference power; An analog/digital conversion circuit comprising: a control means for successively and selectively comparing and contrasting the electric charges obtained by the electric charge, and digitally obtaining an approximate value; and register means connected to the control means and storing the digital approximate value. (3) a plurality of differential amplifiers connected in a stepwise manner for determining the presence of a voltage difference between the first and second input signals and amplifying said voltage difference; and an output means for outputting a signal when a specific input voltage difference occurs;
a plurality of offset voltage correction circuits connected to each other to correct the offset voltage of each of the differential amplifiers and compensate for device mismatch between the differential amplifiers; (4) Reference input; Analog input; Charge array of capacitive elements weighted by 2m number; Resistor array connected in series: Equal to the smallest capacitive element in the charge array, which is 7J111' in binary. , a least significant bit capacitive element connected to the resistor array and also connected in parallel to the charge array; first and second comparator circuits having an output indicating the existence of a voltage difference between the inputs; a comparison circuit, the second input of which is connected to the charge array and the least significant bit capacitive element; a reference capacitor connected to the first comparison circuit element; a reference input connected to the first comparison circuit element; switch means connected to the output of the comparator circuit and the switch means for connecting the analog input to the charge array E; connected to the output of the comparator circuit and the switch means to successively and selectively compare and contrast the charge array capacitive element and the reference input; determine the most significant bit of the digital approximation of the analog input by and compare and contrast the selected charge array capacitive element with the least significant bit capacitive element in series with successive selected resistors in the resistor array. An analog/digital conversion circuit comprising: control means for determining the least significant bit of the digital approximation value; and register means connected to the control means for storing the digital approximation value.