JPS5885533A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5885533A JPS5885533A JP56184570A JP18457081A JPS5885533A JP S5885533 A JPS5885533 A JP S5885533A JP 56184570 A JP56184570 A JP 56184570A JP 18457081 A JP18457081 A JP 18457081A JP S5885533 A JPS5885533 A JP S5885533A
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- etching
- image
- substrate
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000001312 dry etching Methods 0.000 claims abstract description 21
- 238000010894 electron beam technology Methods 0.000 claims abstract description 21
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 28
- 238000007689 inspection Methods 0.000 abstract description 23
- 239000000758 substrate Substances 0.000 abstract description 19
- 238000004453 electron probe microanalysis Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000001228 spectrum Methods 0.000 description 6
- 238000002083 X-ray spectrum Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
(11発明の技術分野
本発明は半導体装置の製造方法に係り、特に1ぐライエ
ノチング工程のインライン検査方法に関する。DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an in-line inspection method for a lie notching process.
(2)技術の背景
半導体装置がL S I 、超LSIとますまず高密度
化し高集積化するに伴い、製造工程のインライン化に適
した反応性スパッタエツチング(リアクティブ・スパッ
タエツチング)法等のドライエ。(2) Background of the technology As semiconductor devices become increasingly dense and highly integrated, such as LSI and VLSI, reactive sputter etching methods, etc., which are suitable for in-line manufacturing processes, are becoming more and more popular. Dreyer.
チング(乾式エツチング)法が導入されて、半導体装置
の製造工程のインライン化が進められている。With the introduction of etching (dry etching) methods, in-line manufacturing processes for semiconductor devices are progressing.
(3)従来技術と問題点
とごろがドライエツチングを終了した被処理試料の検査
工程は従来より作業者か顕微鏡で丹念に被処理試料面を
観蟇し、エノヂングの残渣やオーバーエッチの有無等を
調べるという、高度に熟練した作業者による目視検査に
よらざるを得なかった。そのため−ト述の如くドライエ
ツチング工程自体はインライン化し得ても、その検査工
程はインライン化することかできず、従って半導体装置
の製造工程の完全なインライン化を妨げていた。(3) Conventional technology and problems In the inspection process of a processed sample after dry etching, the surface of the processed sample is carefully observed by an operator or with a microscope to check for engraving residues and over-etching. Visual inspection by highly skilled workers was the only option available. Therefore, as mentioned above, even though the dry etching process itself can be done in-line, the inspection process cannot be done in-line, and this has hindered complete in-line manufacturing of semiconductor devices.
(4) 発明の目的
本発明の目的は」二記問題点を解消して、ドライエツチ
ング後の被処理試料の検査をインライン処理可能ならし
める半導体装置の製造方法を提供することにある。(4) Object of the Invention An object of the present invention is to provide a method for manufacturing a semiconductor device which solves the problems mentioned in 2 above and enables in-line inspection of a sample to be processed after dry etching.
(5)発明の構成
本発明の特徴は、被処理試料にドライエツチング処理を
施した後、前記被処理試料を大気中に取り出すに先立ち
、前記被処理試料の被処理面に電子線を照射して発生せ
しめた二次電子と特性X線を検知し、得られた二次電子
線像と特性X線像とを用いて、前記被処理試料面上に形
成されたパターンを検査する工程を含むことにある。(5) Structure of the Invention A feature of the present invention is that after performing a dry etching process on a sample to be processed, and before taking out the sample to be processed into the atmosphere, the surface to be processed of the sample to be processed is irradiated with an electron beam. detecting secondary electrons and characteristic X-rays generated by the process, and inspecting a pattern formed on the surface of the sample to be processed using the obtained secondary electron beam image and characteristic X-ray image. There is a particular thing.
以下本発明の一実施例を図面により説明する。An embodiment of the present invention will be described below with reference to the drawings.
第1図〜第5図は上記一実施例を示す図で、第1図は上
記一実施例に用いたドライエツチング装置の要部正面図
、第2図〜第5図は上記一実施例の効果を説明するため
の要部断面図及び曲線図である。FIGS. 1 to 5 are views showing the above embodiment, FIG. 1 is a front view of main parts of the dry etching apparatus used in the above embodiment, and FIGS. 2 to 5 are diagrams showing the main part of the dry etching apparatus used in the above embodiment. FIG. 4 is a cross-sectional view and a curve diagram of main parts for explaining the effect.
上記第1図において、■はエツチング室でドライエツチ
ング装置の本体、2は被処理試料を装填するだめの装填
器、3は装填器2とエツチング室1とを連結する連結器
、4はエツチング室lと次段の装置または外部とを連結
する連結器、5はドライエツチングを施した被処理試料
の検査装置、6は第2のエツチング室である。上記中検
査装置6は走査型電子顕微鏡(SEM3及び電子線マイ
クロアナライザ(EPMA)とから構成されている。In FIG. 1 above, ■ is the etching chamber, which is the main body of the dry etching apparatus, 2 is a loader for loading the sample to be processed, 3 is a connector that connects the loader 2 and the etching chamber 1, and 4 is the etching chamber. A connector 1 connects the device to the next stage or the outside; 5 is an inspection device for dry-etched samples; and 6 is a second etching chamber. The medium inspection device 6 is composed of a scanning electron microscope (SEM 3) and an electron beam microanalyzer (EPMA).
次に」1記ドライエツチング装置ににる本実施例のドラ
イエツチング及び被処理試料の検査方法について説明す
る。Next, the method of dry etching of this embodiment using the dry etching apparatus mentioned above and the method of inspecting the sample to be processed will be explained.
まずシリコン(Si)基板等の被処理試料(図示せず)
を収容したカセットと呼ばれる専用の容器を、上記装填
器2に装着し、連結器3を経て被処理試料の3i基板を
エツチング室1内に入れる。First, a sample to be processed such as a silicon (Si) substrate (not shown)
A special container called a cassette containing the 3i substrate is attached to the loader 2, and the 3i substrate to be processed is introduced into the etching chamber 1 via the connector 3.
次いでこの3i基板にリアクティブ・スパッタエツチン
グ法等の所望のドライエツチング処理を施す。かくして
所定のパターンが形成されたSi基板は、次に連結器4
に送られる。本実施例のドライエツチング装置において
は、この連結器4は検査室を兼ねるよう構成され、ここ
でSi、l板表面に形成されたパターンを検査する。This 3i substrate is then subjected to a desired dry etching process such as reactive sputter etching. The Si substrate on which the predetermined pattern has been formed is then connected to the coupler 4.
sent to. In the dry etching apparatus of this embodiment, the coupler 4 is constructed to also serve as an inspection chamber, in which the pattern formed on the surface of the Si, L plate is inspected.
上記連結器4内はエツチング室1と同様に真空に保たれ
、Si基板を人気にさらさないようにしである。この連
結器4内の所定位置に前記Si基板を静置し、連結器4
上部に設けられた検査装置5より微小スポット状の電子
線によりSi基板のパターンを形成した表面を走査する
。このように電子線の照射を受けるとSi基板表面から
は表面の状態に応した二次電子及びX線が発生ずる。こ
れらを上記検査装置6を構成するSEM及びEPMAに
よりそれぞれ検出し、SEM、EPMAのモニタ画面上
に二次電子線像、X線像を互いに対応させて描かせる。The inside of the coupler 4 is kept in a vacuum like the etching chamber 1 so as not to expose the Si substrate to heat. The Si substrate is placed at a predetermined position in the coupler 4, and the coupler 4
The patterned surface of the Si substrate is scanned by an electron beam in the form of a minute spot from an inspection device 5 provided at the top. When irradiated with an electron beam in this manner, the surface of the Si substrate generates secondary electrons and X-rays corresponding to the surface condition. These are detected by the SEM and EPMA constituting the inspection device 6, respectively, and a secondary electron beam image and an X-ray image are drawn in correspondence with each other on the monitor screens of the SEM and EPMA.
上記SEMのモニタ画面上に描出された二次電子線像を
標準のパターンやドライエツチングのマスクに用いたホ
トレジスト膜等と比較することにより、Si基板表面に
形成されたパターンの平面像の良否即ちパターンの線幅
や直線性等を検査することができる。一方EPMAのモ
ニタ画面上に描出されたX線像からは、上記二次電子線
像と対応することにより、パターン各部のエツチングの
残渣やオーバーエツチングの有無を検出することが出来
る。By comparing the secondary electron beam image drawn on the monitor screen of the SEM with a standard pattern or a photoresist film used as a dry etching mask, it is possible to determine whether the planar image of the pattern formed on the surface of the Si substrate is good or not. It is possible to inspect the line width, linearity, etc. of a pattern. On the other hand, by correlating the X-ray image drawn on the EPMA monitor screen with the secondary electron beam image, it is possible to detect the presence or absence of etching residues and over-etching in various parts of the pattern.
この検査方法を第2図〜第5図を用いて説明する。第2
図+al 〜(C1及び第4図+a+ 、 (bl
は51基板lI上にアルミニゆム(AI)よりなる配線
を形成する例を、ドライエツチングが進行する順に示す
要部断面図で、第3図及び第5図は上記各状態に対応し
て描いたホトレジスト膜14のパターンエツジ部(図の
矢印で示す位置)のX線スペクトラムを示す曲線図であ
る。第2図[alはエツチング開始前の状態で、1.1
はSi基板、12はS1基板11表面を被覆する二酸化
シリコン(Sin、)I!、13はアルミニウム(AI
)III、I4は所定のパターンに従って形成されたホ
トレジスト膜である。この状態にお)JるX線スペクト
ラムは、図の曲線21(実線)に見られる如<AIを示
すスペクトルが強く現われる。次にエツチングが進行し
、同図(blに見られる如<AI層13の厚さが減じる
と、X線スペクトルは曲線22(破線)のようにA1の
スペクトルが弱くなり、かわって3iのスペクトルが強
くなる。更にエツチングが進行しSi基板表面が露出す
るようになると、曲線23(一点鎖線)のようにA1の
スペクトルはいっそう弱まり、Sjのスペクトルが非常
に強くなる。This inspection method will be explained using FIGS. 2 to 5. Second
Figure +al ~ (C1 and Figure 4 +a+, (bl
51 is a cross-sectional view of the main parts showing an example of forming wiring made of aluminum (AI) on a 51 substrate lI in the order in which dry etching progresses, and FIGS. 3 and 5 are drawn corresponding to each of the above states. 3 is a curve diagram showing an X-ray spectrum of a pattern edge portion (position indicated by an arrow in the figure) of a photoresist film 14. FIG. Figure 2 [al is the state before the start of etching, 1.1
is a Si substrate, and 12 is silicon dioxide (Sin, ) I! which covers the surface of the S1 substrate 11. , 13 is aluminum (AI
) III and I4 are photoresist films formed according to a predetermined pattern. In the X-ray spectrum in this state, a spectrum indicating <AI appears strongly, as shown by curve 21 (solid line) in the figure. Next, as the etching progresses and the thickness of the AI layer 13 decreases as shown in the same figure (bl), the X-ray spectrum becomes weaker as shown by curve 22 (dashed line), and the spectrum of A1 becomes weaker, and the spectrum of 3i becomes weaker. As the etching progresses further and the surface of the Si substrate becomes exposed, the spectrum of A1 becomes even weaker as shown by curve 23 (dotted chain line), and the spectrum of Sj becomes very strong.
第4図ta) 、 (b)は前記第2図tc)の細部を
強調して示す要部断面図で、同図[a)はほぼホトレジ
スト膜14のパターンに従ってAlpH3が工・ノチン
グされた状態、同図(b)はAl113がオーバーエッ
チされた状態を示す。第5図の曲線24(一点鎖線)2
曲線25(二点鎖線)はそれぞれ上記第4図(al、
(b)に対応する。第4図(a)ではパターンエ・ノジ
部にA1が存在するので、曲線24のスペクトルは八1
が強<Siは弱い。これに対し第4図(b)に見られる
ようにエツチングが過剰になる。と、X線スペクトルは
曲線25のように八lが弱まりSiが強くなる。FIGS. 4 ta) and 4 (b) are cross-sectional views of main parts emphasizing the details of FIG. 2 tc), and FIG. , the same figure (b) shows the state where Al113 is over-etched. Curve 24 (dotted chain line) 2 in Figure 5
Curve 25 (double-dashed line) is shown in FIG. 4 above (al,
Corresponds to (b). In FIG. 4(a), since A1 exists in the pattern edge part, the spectrum of curve 24 is 81.
is strong<Si is weak. On the other hand, as shown in FIG. 4(b), excessive etching occurs. Then, in the X-ray spectrum, as shown by curve 25, 8l becomes weaker and Si becomes stronger.
このように電子線を照射し、発生ずる特性X線を位置に
対応して検知することにより、その場所の表面の材質と
その膜厚を知ることができる。なお3i0.Rgに電子
線を照射した場合には、Siが検出される旨説明したが
、これは上記検出法ではSin、の二つの構成要素の内
、3iは明確に検知出来るのに対し、0.は殆ど検知出
来ないためである。By irradiating an electron beam in this manner and detecting the generated characteristic X-rays corresponding to the position, it is possible to know the material of the surface at that location and its film thickness. Note that 3i0. It has been explained that when Rg is irradiated with an electron beam, Si is detected, but this is because the above detection method clearly detects 3i of the two constituent elements of Sin, whereas 0. This is because it is almost impossible to detect.
本実施例ではこれを利用して、前述の如く連結器4にお
いて被処理試料の3i基板に電子線を照射し、発生する
二次電子と特性X線を検出することにより、被処理試料
表面に形成されたパターンの寸法やエツチングの過不足
等を検出する。この結果は直ちにフィードバンクされ、
第2のエツチング室6で当該試料に追加エツチングを施
すこと及びそのエツチング量を決定することや、当該試
料に引き続く被処理試料のエツチング量を調節するなど
、インライン処理によりドライエツチングを適切に制御
することか可能となる。しかもAIのように一旦空気に
さらすと表面の状態が変化してしまい、エツチング処理
がしにくくなるものであっても、本実施例の検査方法は
ドライエツチング処理を施した後、被処理試料を大気中
に取り出すことなく真空中において実施することができ
るので、エツチング処理を追加することが容易である。In this embodiment, by utilizing this, as described above, the 3i substrate of the sample to be processed is irradiated with an electron beam in the coupler 4, and the generated secondary electrons and characteristic X-rays are detected, thereby exposing the surface of the sample to be processed. It detects the dimensions of the formed pattern and the excess or deficiency of etching. This result is immediately feedbanked and
Dry etching is appropriately controlled by in-line processing, such as performing additional etching on the sample in the second etching chamber 6 and determining the etching amount, and adjusting the etching amount of the sample to be processed subsequent to the sample. It becomes possible. Moreover, even for materials such as AI, whose surface condition changes once exposed to air and makes it difficult to perform etching, the inspection method of this example involves performing dry etching and then testing the sample to be processed. Since it can be carried out in a vacuum without being taken out into the atmosphere, it is easy to add an etching process.
本発明は上記一実施例に限定されるものではなく、更に
種々変形して実施し得る。The present invention is not limited to the above-mentioned embodiment, but can be implemented with various modifications.
例えば上記一実施例では検査装置としてSEMとEPM
Aを用いたが、これに変えて電子銃−個と電子線検出器
とX線検出器とからなる専用の検査装置を製作して使用
してもよいことは勿論である。For example, in the above embodiment, SEM and EPM are used as inspection devices.
Although A was used, it goes without saying that a dedicated inspection device consisting of an electron gun, an electron beam detector, and an X-ray detector may be manufactured and used instead.
また本発明はAIのエツチングのみならす、通常実施さ
れる他のいかなる材料のドライエ・ノチングの検査にも
実施し得る。Furthermore, the present invention can be applied not only to the etching of AI, but also to the inspection of dry etching of any other commonly practiced materials.
以上説明した如く本発明によれば、ドライエツチング後
の検査工程をインライン化することが可能となり、半導
体装置の製造工程をインライン化が容易になる。また本
発明では一連の工程を真空中で一貫して行うため、被処
理試料を常に清浄に保ことが出来、製造工程が安定する
。更にエツチング結果が望ましくない場合には、その不
良モードに対応して検査装置から直ちにエツチング条件
の補正、変更、追加等のフィードパ・ツクが可能である
。As described above, according to the present invention, it is possible to carry out the inspection process after dry etching in-line, and it becomes easy to carry out in-line manufacturing processes for semiconductor devices. Further, in the present invention, since a series of steps are consistently performed in a vacuum, the sample to be processed can be kept clean at all times, and the manufacturing process is stabilized. Furthermore, if the etching results are undesirable, it is possible to immediately correct, change, or add etching conditions from the inspection device in response to the failure mode.
//
第1図は本発明の半導体装置の製造方法の一実施例を、
使用した製造装置と共に説明するための正面図、第2図
〜第5図は本実施例の検査方法を説明するための図で、
第2図及び@4図は被処理試料の検査対象位置の状態を
示す要部断面図、第3図及び第4図は検出されたXIt
Qスベク1ラムを上記検査対象位置の状態に対応して描
いである。
図において、1はエツチング室、5は検査装置、11は
半導体基板、12はSin、膜、I3は被処理膜のA1
層、14はホトレジスト膜、21〜25はX線ス/θ
第3図
−〉玉子ル代゛(にeV)
落 5 図
□エネル”J’ (KeV)FIG. 1 shows an embodiment of the method for manufacturing a semiconductor device of the present invention.
A front view for explaining the manufacturing equipment used, and FIGS. 2 to 5 are diagrams for explaining the inspection method of this example.
Figures 2 and 4 are cross-sectional views of the main parts showing the state of the inspection target position of the sample to be processed, and Figures 3 and 4 are the detected XIt
Qsubek1ram is drawn corresponding to the state of the above-mentioned inspection target position. In the figure, 1 is an etching chamber, 5 is an inspection device, 11 is a semiconductor substrate, 12 is a Sin film, and I3 is A1 of a film to be processed.
layer, 14 is a photoresist film, 21 to 25 are X-rays /θ
Claims (1)
のパターンを形成するに際し、被処理試料にドライエツ
チング処理を施した後、前記被処理試料を人気中に取り
出すに先立ち、前記被処理試料の被処理面に電子線を照
射して発生せしめた二次電子と特性X線を検知し、得ら
れた二次電子線像と特性X線像とを用いて、前記被処理
試料面上に形成されたパターンを検査する工程を含むこ
とを特徴とする半導体装置の製造方法。When forming a predetermined pattern on the surface of a sample to be processed by the dry etching method, after performing the dry etching process on the sample to be processed, and before taking out the sample to be processed, the surface of the sample to be processed is removed. Secondary electrons and characteristic X-rays generated by irradiating the surface to be treated with an electron beam are detected, and the obtained secondary electron beam image and characteristic 1. A method of manufacturing a semiconductor device, comprising a step of inspecting a pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56184570A JPS5885533A (en) | 1981-11-17 | 1981-11-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56184570A JPS5885533A (en) | 1981-11-17 | 1981-11-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5885533A true JPS5885533A (en) | 1983-05-21 |
Family
ID=16155512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56184570A Pending JPS5885533A (en) | 1981-11-17 | 1981-11-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885533A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05251392A (en) * | 1992-03-05 | 1993-09-28 | Nec Kyushu Ltd | Reactive ion etching device |
-
1981
- 1981-11-17 JP JP56184570A patent/JPS5885533A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05251392A (en) * | 1992-03-05 | 1993-09-28 | Nec Kyushu Ltd | Reactive ion etching device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6047083A (en) | Method of and apparatus for pattern inspection | |
JP4601295B2 (en) | How to monitor and inspect the manufacture of contact openings | |
Saito et al. | Study of ADI (after develop inspection) using electron beam | |
KR100447713B1 (en) | Method and apparatus for showing scanning image of sample | |
US5783366A (en) | Method for eliminating charging of photoresist on specimens during scanning electron microscope examination | |
JP2005286161A (en) | Method and apparatus for shape restoration, and manufacturing method of semiconductor device using them | |
US4950498A (en) | Process for repairing pattern film | |
JP2004022318A (en) | Transmission electron microscope and sample analysis method | |
US7473911B2 (en) | Specimen current mapper | |
US6723650B1 (en) | TEM sample preparation using transparent defect protective coating | |
JPH08327514A (en) | Preparation of sample for transmission electron microscope and device therefor | |
US8242443B2 (en) | Semiconductor device inspection apparatus | |
JPS5885533A (en) | Manufacture of semiconductor device | |
JPH09219430A (en) | Manufacture of test piece for defect adjustment of semiconductor element | |
JP3467189B2 (en) | Elemental analysis method | |
JP3041405B2 (en) | Micro section observation method | |
JP2992682B2 (en) | Cross section observation method for integrated circuits | |
JP2900380B2 (en) | Method for manufacturing semiconductor device | |
JP2000055841A (en) | X-ray analysis method | |
JP2001343340A (en) | Photoelectron spectrophotometric device and measuring method | |
Muller et al. | Defect studies on single and bilayer resist systems | |
JP2006138856A (en) | Distance measuring method of testpiece | |
JPH09321114A (en) | Manufacture of semiconductor element | |
JPS61256554A (en) | Scanning-type electronic microscope | |
JP3243822B2 (en) | Mask inspection method and reticle mask |